Texas Instruments DS320PR410-RSC-EVM User manual

EVM User's Guide: DS320PR410-RSC-EVM
DS320PR410-RSC-EVM Evaluation Module
Description
The DS320PR410-RSC-EVM evaluation module
provides a complete high-bandwidth platform for
evaluating the signal conditioning features of
the Texas Instruments DS320PR410 Four-Channel
PCI-Express 5.0 Linear Redriver. This evaluation
board can be used for standard compliance
testing, performance evaluation, and initial system
prototyping.
Get Started
1. Order the DS320PR410-RSC-EVM on ti.com
2. Read through the instructions provided in this
User's Guide to understand the jumper options
provided on the DS320PR410-RSC-EVM and for
instructions to configure the EVM.
3. For EEPROM or SMBus / I2C programming, visit
the TI SigCon Architect download page to install
the Texas Instruments SigCon Architect GUI. To
download the DS320PR410 SigCon Architect GUI
profile, please contact your TI representative or
create a request using TI E2E.
Features
• PCIe x16 Riser Card option with eight 4-channel
unidirectional linear redrivers operating at rates up
to 32Gbps
• Linear equalization for seamless support of link
training and PCIe channel extension
• CTLE boosts up to 22 dB at 16 GHz
• Programmable device configuration through
EEPROM, GPIO, I2C, or SMBus
• Onboard 12-V to 3.3-V, 2-A step-down DC/DC
converter
• Industrial temperature range: –40°C to 85°C
• Flow-through layout in 4 mm × 6 mm, 40-pin, lead-
less WQFN 0.4-mm pitch package
Applications
• PCI Express Gen-1, 2, 3, 4, and 5
• High-speed interfaces up to 32Gbps
• Enterprise server motherboard, workstation
• Enterprise storage
• Enterprise add-in card, end-point
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Table of Contents
Description................................................................................................................................................................................. 1
Get Started..................................................................................................................................................................................1
Features......................................................................................................................................................................................1
Applications............................................................................................................................................................................... 1
1 Evaluation Module Overview................................................................................................................................................. 3
1.1 Introduction........................................................................................................................................................................ 3
1.2 Kit Contents........................................................................................................................................................................3
1.3 Specification.......................................................................................................................................................................3
1.4 Device Information............................................................................................................................................................. 3
2 Hardware................................................................................................................................................................................. 4
2.1 DS320PR410 5-Level I/O Control Inputs........................................................................................................................... 4
2.2 DS320PR410 Modes of Operation.....................................................................................................................................4
2.3 DS320PR410 SMBus or I2C Register Control Interface.................................................................................................... 5
2.4 DS320PR410 Equalization Control.................................................................................................................................... 6
2.5 DS320PR410 RX Detect State Machine............................................................................................................................7
2.6 DS320PR410 DC Gain Control..........................................................................................................................................7
2.7 DS320PR410 EVM Global Controls ..................................................................................................................................8
2.8 DS320PR410-RSC-EVM Downstream Devices Control....................................................................................................9
2.9 DS320PR410-RSC-EVM Upstream Devices Control...................................................................................................... 10
2.10 Quick-Start Guide (Pin Mode)........................................................................................................................................ 11
2.11 Quick-Start Guide (SMBus / I2C Secondary Mode)........................................................................................................12
3 Implementation Results....................................................................................................................................................... 14
3.1 Test Setup and Results.................................................................................................................................................... 14
4 Hardware Design Files......................................................................................................................................................... 15
4.1 Schematics.......................................................................................................................................................................15
4.2 Board Layout....................................................................................................................................................................22
4.3 Bill of Materials.................................................................................................................................................................23
5 Additional Information..........................................................................................................................................................27
6 References............................................................................................................................................................................ 28
List of Figures
Figure 1-1. DS320PR410-RSC-EVM Example Application Diagram.......................................................................................... 3
Figure 2-1. SigCon Architect DS320PR410 High-Level Page................................................................................................... 13
Figure 3-1. Example Test Setup................................................................................................................................................ 14
Figure 3-2. Example Test Results..............................................................................................................................................14
Figure 4-1. Control and Status Schematic Page....................................................................................................................... 15
Figure 4-2. Voltage Regulator Schematic Page.........................................................................................................................16
Figure 4-3. Gold Finger Connector Schematic Page.................................................................................................................17
Figure 4-4. Downstream Devices Schematic Page................................................................................................................... 18
Figure 4-5. Upstream Devices Schematic Page........................................................................................................................19
Figure 4-6. Straddle Connector Schematic Page...................................................................................................................... 20
Figure 4-7. Hardware Page....................................................................................................................................................... 21
Figure 4-8. Top Layer.................................................................................................................................................................22
Figure 4-9. Bottom Layer........................................................................................................................................................... 22
List of Tables
Table 2-1. Five-Level Control Pin Settings...................................................................................................................................4
Table 2-2. Modes of Operation.................................................................................................................................................... 4
Table 2-3. DS320PR410 SMBus Address Map........................................................................................................................... 5
Table 2-4. Equalization Control Settings......................................................................................................................................6
Table 2-5. Receiver Detect State Machine Settings.................................................................................................................... 7
Table 2-6. GAIN Control...............................................................................................................................................................7
Table 2-7. EVM Global Controls.................................................................................................................................................. 8
Table 2-8. EVM Downstream Devices Controls...........................................................................................................................9
Table 2-9. EVM Upstream Devices Controls............................................................................................................................. 10
Table 4-1. Bill of Materials..........................................................................................................................................................23
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1 Evaluation Module Overview
1.1 Introduction
The DS320PR410-RSC-EVM evaluation module features eight DS320PR410 linear redrivers that can extend the
transmission distance of a PCIe Gen-5 x16 bus. The evaluation module can directly be plugged into a PCIe slot
on a server or PC motherboard using one end of the board, and paired up with a PCIe add-in card using the
straddle mount connector attached to the other end of the board.
This user's guide describes the characteristics, operation, and use of the DS320PR410-RSC-EVM evaluation
module. The user's guide details how to set up and configure hardware and reviews various aspects of the
software operation. Throughout this document, the terms evaluation board, evaluation module, and EVM are
synonymous with the DS320PR410-RSC-EVM. This user's guide also provides information on the operating
procedure, input and output connections, an electrical schematic, printed circuit board (PCB) layout drawings,
and a Bill of Materials (BOM) for the EVM.
1.2 Kit Contents
The EVM kit contains one (1) DS320PR410-RSC-EVM. Contact the Texas Instruments Product Information
Center nearest you if any components are missing. TI highly recommends that users check the TI website at
ti.com to verify that the latest versions of the related software is being used.
1.3 Specification
The DS320PR410-RSC-EVM is targeted for applications where PCI-Express riser card slots (up to x16) are
available for test. Figure 1-1 shows the DS320PR410-RSC-EVM used with a system motherboard with a
PCI-Express Gen5.0 capable CPU and an Add-In Card Endpoint.
System Motherboard
x16
DS320PR410-RSC-EVM Redriver
Evaluation Module (EVM)
Add-In Card Endpoint
USB to
I2C Adapter
(optional)
CPU / Root
Complex
TI SigCon
Architect GUI for
DS320PR410
(optional)
Figure 1-1. DS320PR410-RSC-EVM Example Application Diagram
1.4 Device Information
The DS320PR410 is a four-channel low-power high-performance linear redriver designed to support PCI-
Express Gen5.0, CXL 2.0, UPI 2.0, and other interfaces up to 32Gbps. Each device is pin-strap, EEPROM,
or I2C / SMBus configurable.
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2 Hardware
The Hardware section details DS320PR410-RSC-EVM hardware control features, the SMBus / I2C control
interface, and quick-start guidelines.
2.1 DS320PR410 5-Level I/O Control Inputs
Each DS320PR410 features 5-level input pins (MODE, GAIN, RX_DET, EQ0 / ADDR0, and EQ1 / ADDR1) that
are used to control the configuration of the device. These 5-level inputs use a resistor divider to help set the four
valid levels to provide a wider range of control settings.
Table 2-1. Five-Level Control Pin Settings
PIN LEVEL PIN SETTING
L0 1 kΩ to GND
L1 8.25 kΩ to GND
L2 24.9 kΩ to GND
L3 75 kΩ to GND
L4 Float
2.2 DS320PR410 Modes of Operation
Each DS320PR410 can be configured to operate in either Pin Mode, SMBus with I2C Primary Mode (EEPROM
Mode), or SMBus with I2C Secondary Mode. The mode of operation of the DS320PR410 is determined by the
pin strap setting on the MODE pin as shown in Table 2-2.
Table 2-2. Modes of Operation
MODE PIN LEVEL MODE OF OPERATION
L0 Pin Mode
L1 SMBus Mode or I2C Primary
Mode (EEPROM Mode)
L2 SMBus Mode or I2C Secondary
Mode
L3 RESERVED
L4 RESERVED
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2.3 DS320PR410 SMBus or I2C Register Control Interface
Each DS320PR410 internal registers can be accessed through standard SMBus protocol. The DS320PR410
features one bank of channels, Channels 0–3. The SMBus secondary address pairs (one for each device) are
determined at power up based on the configuration of the EQ0 / ADDR0 and EQ1 / ADDR1 pins. The pin state is
read on power up, after the internal power-on reset signal is deasserted.
There are 16 unique SMBus secondary addresses that can be assigned to the device by placing external
resistor straps on the EQ0 / ADDR0 and EQ1 / ADDR1 pins as shown in Table 2-3. When multiple DS320PR410
devices are on the same SMBus interface bus, each device must be configured with a unique SMBus secondary
address.
Table 2-3. DS320PR410 SMBus Address Map
ADDR1 Pin Level ADDR0 Pin Level DS320PR410 7-Bit Address
[HEX]
L0 L0 0x18
L0 L1 0x1A
L0 L2 0x1C
L0 L3 0x1E
L0 L4 Reserved
L1 L0 0x20
L1 L1 0x22
L1 L2 0x24
L1 L3 0x26
L1 L4 Reserved
L2 L0 0x28
L2 L1 0x2A
L2 L2 0x2C
L2 L3 0x2E
L2 L4 Reserved
L3 L0 0x30
L3 L1 0x32
L3 L2 0x34
L3 L3 0x36
L3 L4 Reserved
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2.4 DS320PR410 Equalization Control
Each channel of the DS320PR410 features a continuous-time linear equalizer (CTLE) that applies high-
frequency boost and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects
of the passive channel. Table 2-4 shows available equalization boost through EQ control pins (EQ1 and EQ0)
when in Pin Control mode (MODE = L0).
Table 2-4. Equalization Control Settings
EQ INDEX EQ1 PIN LEVEL EQ0 PIN LEVEL CTLE BOOST AT 8 GHz
(dB)
CTLE BOOST AT 16 GHz
(dB)
0 L0 L0
For CTLE boost values at
8 GHz, please reference
the DS320PR410 data sheet
(SNLS739).
For CTLE boost values at
16 GHz, please reference
the DS320PR410 data sheet
(SNLS739).
1 L0 L1
2 L0 L2
5 L1 L0
6 L1 L1
7 L1 L2
8 L1 L3
9 L1 L4
10 L2 L0
11 L2 L1
12 L2 L2
13 L2 L3
14 L2 L4
15 L3 L0
16 L3 L1
17 L3 L2
18 L3 L3
19 L3 L4
The equalization gain of each channel of each device can also be set by writing to SMBus / I2C registers in I2C
Mode. Refer to the DS320PR410 Programming Guide for details.
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2.5 DS320PR410 RX Detect State Machine
Each DS320PR410 deploys an RX Detect state machine that governs the RX detection cycle as defined in the
PCI Express specification. At power up or after a manually triggered event, the redriver determines whether
or not a valid PCI Express termination is present at the far end of the link. When the DS320PR410 is in Pin
Mode (MODE = L0), the RX_DET pin of DS320PR410 provides additional flexibility to system designers to
appropriately set the device in their desired mode, according to Table 2-5.
Table 2-5. Receiver Detect State Machine Settings
PD PIN LEVEL RX_DET PIN LEVEL
DS320PR410 Channel
RX Common-mode
Impedance
DESCRIPTION
L L0 Always 50 Ω PCI Express RX detection state machine is disabled.
Recommended for non-PCI Express use cases.
L L1 Pre Detect: Hi-Z
Post Detect: 50 Ω Outputs poll until 3 consecutive valid detections.
L L2 Pre Detect: Hi-Z
Post Detect: 50 Ω Outputs poll until 2 consecutive valid detections.
L L3 N/A Reserved
L L4 (Float) Pre Detect: Hi-Z
Post Detect: 50 Ω
TX polls approx. every 150 μs until valid termination
is detected. Rx CM impedance held at Hi-Z until
detection. Reset by asserting PD high for 200 μs then
low.
H X Hi-Z Reset all DS320PR410 channels signal path and set
their Rx impedance state to Hi-Z.
The RX Detect state of each channel of each device can also be set by writing to SMBus / I2C registers in
Secondary or Primary Modes. Refer to the DS320PR410 Programming Guide for details.
2.6 DS320PR410 DC Gain Control
When operating in Pin Mode (MODE = L0), the GAIN pin can be used to set the overall data-path flat gain (DC
and AC) of the DS320PR410 for channels 0-3 as shown in Table 2-6.
Table 2-6. GAIN Control
GAIN/SDA PIN
LEVEL GAIN SETTING
L0 –6 dB (-5.6dB actual)
L1 –4 dB (-3.8dB actual)
L2 -2 dB (-1.2dB actual)
L3 +2 dB (+2.6dB actual)
L4 (Float) 0 dB (+0.6dB actual - recommended for most
use cases)
The DC gain of each channel of each device can also be set by writing to SMBus / I2C registers in Secondary or
Primary Modes. Refer to the DS320PR410 Programming Guide for details.
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2.7 DS320PR410 EVM Global Controls
Table 2-7 shows DS320PR410-RSC-EVM global controls that affect all devices on the board.
Table 2-7. EVM Global Controls
COMPONENT NAME FUNCTION / DESCRIPTION
J1 4x2 Header
MODE control tied to MODE pins of all eight DS320PR410 devices on the EVM
L0: All devices set to Pin Mode (Default)
L1: All devices set to SMBus / I2C Primary Mode (EEPROM Mode)
L2: SMBus / IC Secondary Mode
L3: Reserved
L4: Reserved
J2 4x2 Header
RX_DET control tied to RX_DET pins of all eight DS320PR410 devices on the
EVM
L0: RX Detect state machine disabled on all devices
L1: RX Detect state machine enabled on all devices (3 valid detections needed)
L2: RX Detect state machine enabled on all devices (2 valid detections needed)
L3: Reserved
L4: RX Detect state machine enabled on all devices (1 valid detection needed) -
Default
J3 5x2 Header SMBus / I2C interface. All eight DS320PR410 devices on the EVM are on the same
bus and can be accessed through this interface.
J4 3x2 Header
PWDN control tied to PD pins of all eight DS320PR410 devices on the EVM.
Remove shunt on J6 when using J4 to control PWDN.
PWDN tied to GND: All devices enabled (Default)
PWDN tied to PERST_INV: All device PD pins controlled by inverted PCIe Reset
(PERST#)
PWDN tied to 3.3V_REG: All devices disabled.
PWDN floating: Tie PCIe system PRSNT signal to PWDN using J6 for the PWDN
control (optional for PCIe use case)
J5 3x1 Header
Access point to the WP (write protect) pin of the onboard EEPROM devices.
WP tied to GND: I2C Access to the EEPROM enabled
WP floating: I2C Access to the EEPROM disabled (Default)
J6 2x1 Header
Alternative PWDN Control. Remove shunt on J4 when using J6 to control
PWDN.
PWDN floating: Use J4 for the PWDN control (Default)
PWDN tied to PRSNT: PRSNT signal controls PWDN (optional for PCIe use case).
J7, J8, J9, J10 3x1 Headers
PCIe PRSNT Signal Controls
Tie pins 1-2 on J7, J8, J9, and J10: Allow support any PCIe bus width (Default)
Tie pins 2-3 of J7, leave J8, J9, and J10 floating: Force x1 PCIe bus width.
Tie pins 2-3 of J8, leave J7, J9, and J10 floating: Force x4 PCIe bus width.
Tie pins 2-3 of J9, leave J7, J8, and J10 floating: Force x8 PCIe bus width.
Tie pins 2-3 of J10, leave J7, J8, and J9 floating: Force x16 PCIe bus width.
J11 2x1 Header
Onboard regulator input. Apply 12 V when using the EVM as a standalone system.
DO NOT APPLY power if plugging the EVM into a system as the power is provided
through the gold finger connector (CONN1).
J12 2x1 Header Access point to the GND reference.
J13 2x1 Header Onboard 3.3 V output.
J38 3x1 Header Select I2C adapter to plug into Connector J3.
Tie pins 1-2 for TI USB2ANY Adapter
Tie pins 2-3 for Aardvark Adapter (Default)
Select the appropriate jumper position for the selected adapter to avoid
damaging the EVM.
J41 3x1 Header READ_EN_N select
Tie pins 1-2 to tie READ_EN_N to GND and initiate EEPROM read (EEPROM
mode only) - Default
Tie pins 2-3 to tie READ_EN_N to disable EEPROM read
J44 2x1 Header SMDAT header to connect global SMBus Data line (Pin 1) to local SMDAT/SDA
(Pin 2). Remove shunt to disconnect global SMDAT from local SMDAT/SDA.
J45 2x1 Header SMCLK header to connect global SMBus Clock line (Pin 1) to local SMCLK/SCL
(Pin 2). Remove shunt to disconnect global SMCLK from local SMCLK/SCL.
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2.8 DS320PR410-RSC-EVM Downstream Devices Control
Table 2-8 shows the DS320PR410-RSC-EVM downstream device controls that affect DS1, DS2, DS3, and DS4
devices on the board.
Table 2-8. EVM Downstream Devices Controls
COMPONENT NAME FUNCTION / DESCRIPTION
J14 4x2 Header
Gain Controls tied to GAIN pins of all downstream device banks (GAIN_DS)
L0: –6 dB Gain Setting
L1: –4 dB Gain Setting
L2: -2 dB Gain Setting
L3: +2 dB Gain Setting
L4: 0 dB Gain Setting (Default)
J15 17x2 Header
Pin Mode (Default): EQ1 controls for each downstream device and device bank.
Use pins 1–8 for configuring EQ1 pin of DS1 device.
Use pins 9–16 for configuring EQ1 pin of DS2 device.
Use pins 17–24 for configuring EQ1 pin of DS3 device.
Use pins 25–32 for configuring EQ1 pin of DS4 device.
SMBus, I2C Modes: ADDR1 controls for each downstream device.
Use pins 1–8 for configuring ADDR1 pin of DS1 device.
Use pins 9–16 for configuring ADDR1 pin of DS2 device.
Use pins 17–24 for configuring ADDR1 pin of DS3 device.
Use pins 25–31 for configuring ADDR1 pin of DS4 device.
Install a shunt to achieve L0, L1, L2 or L3 level on the pin. Leave floating to
achieve L4 level on the pin.
J16 17x2 Header
Pin Mode (Default): EQ0 controls for each downstream device and device bank.
Use pins 1–8 for configuring EQ0 pin of DS1 device.
Use pins 9–16 for configuring EQ0 pin of DS2 device.
Use pins 17–24 for configuring EQ0 pin of DS3 device.
Use pins 25–32 for configuring EQ0 pin of DS4 device.
SMBus, I2C Modes: ADDR0 controls for each downstream device.
Use pins 1–8 for configuring ADDR0 pin of DS1 device.
Use pins 9–16 for configuring ADDR0 pin of DS2 device.
Use pins 17–24 for configuring ADDR0 pin of DS3 device.
Use pins 25–31 for configuring ADDR0 pin of DS4 device.
Install a shunt to achieve L0, L1, L2 or L3 level on the pin. Leave floating to
achieve L4 level on the pin.
J17 3x1 Header
GAIN / SDA Dual Function Pin Provision for DS1 Device.
Install shunt across pins 1-2 for operation in Pin Mode (Default)
Install shunt across pins 2-3 for operation in SMBus, I2C Modes
J18 3x1 Header
RX_DET / SCL Dual Function Pin Provision for DS1 Device.
Install shunt across pins 1-2 for operation in Pin Mode (Default)
Install shunt across pins 2-3 for operation in SMBus, I2C Modes
J19 3x1 Header
GAIN / SDA Dual Function Pin Provision for DS2 Device.
Install shunt across pins 1-2 for operation in Pin Mode (Default)
Install shunt across pins 2-3 for operation in SMBus, I2C Modes
J20 3x1 Header
RX_DET / SCL Dual Function Pin Provision for DS2 Device.
Install shunt across pins 1-2 for operation in Pin Mode (Default)
Install shunt across pins 2-3 for operation in SMBus, I2C Modes
J21 3x1 Header
GAIN / SDA Dual Function Pin Provision for DS3 Device.
Install shunt across pins 1-2 for operation in Pin Mode (Default)
Install shunt across pins 2-3 for operation in SMBus, I2C Modes
J22 3x1 Header
RX_DET / SCL Dual Function Pin Provision for DS3 Device.
Install shunt across pins 1-2 for operation in Pin Mode (Default)
Install shunt across pins 2-3 for operation in SMBus, I2C Modes
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Table 2-8. EVM Downstream Devices Controls (continued)
COMPONENT NAME FUNCTION / DESCRIPTION
J23 3x1 Header
GAIN / SDA Dual Function Pin Provision for DS4 Device.
Install shunt across pins 1-2 for operation in Pin Mode (Default)
Install shunt across pins 2-3 for operation in SMBus, I2C Modes
J24 3x1 Header
RX_DET / SCL Dual Function Pin Provision for DS4 Device
Install shunt across pins 1-2 for operation in Pin Mode (Default)
Install shunt across pins 2-3 for operation in SMBus, I2C Modes
2.9 DS320PR410-RSC-EVM Upstream Devices Control
Table 2-9 shows DS320PR410-RSC-EVM upstream devices controls that affect US1, US2, US3, and US4
devices on the board.
Table 2-9. EVM Upstream Devices Controls
COMPONENT NAME FUNCTION / DESCRIPTION
J26 4x2 Header
Gain Controls tied to GAIN pins of all downstream device banks (GAIN_US)
L0: –6 dB Gain Setting
L1: –4 dB Gain Setting
L2: -2 dB Gain Setting
L3: +2 dB Gain Setting
L4: 0 dB Gain Setting (Default)
J27 17x2
Pin Mode (Default): EQ1 controls for each downstream device and device bank.
Use pins 1–8 for configuring EQ1 pin of US1 device.
Use pins 9–16 for configuring EQ1 pin of US2 device.
Use pins 17–24 for configuring EQ1 pin of US3 device.
Use pins 25–32 for configuring EQ1 pin of US4 device.
SMBus, I2C Modes: ADDR1 controls for each downstream device.
Use pins 1–8 for configuring ADDR1 pin of US1 device.
Use pins 9–16 for configuring ADDR1 pin of US2 device.
Use pins 17–24 for configuring ADDR1 pin of US3 device.
Use pins 25–31 for configuring ADDR1 pin of US4 device.
Install a shunt to achieve L0, L1, L2 or L3 level on the pin. Leave floating to
achieve L4 level on the pin.
J28 17x2 Header
Pin Mode (Default): EQ0 controls for each downstream device and device bank.
Use pins 1–8 for configuring EQ0 pin of US1 device.
Use pins 9–16 for configuring EQ0 pin of US2 device.
Use pins 17–24 for configuring EQ0 pin of US3 device.
Use pins 25–32 for configuring EQ0 pin of US4 device.
SMBus, I2C Modes: ADDR0 controls for each downstream device.
Use pins 1–8 for configuring ADDR0 pin of US1 device.
Use pins 9–16 for configuring ADDR0 pin of US2 device.
Use pins 17–24 for configuring ADDR0 pin of US3 device.
Use pins 25–31 for configuring ADDR0 pin of US4 device.
Install a shunt to achieve L0, L1, L2 or L3 level on the pin. Leave floating to
achieve L4 level on the pin.
J29 3x1 Header
GAIN / SDA Dual Function Pin Provision for US1 Device.
Install shunt across pins 1-2 for operation in Pin Mode (Default)
Install shunt across pins 2-3 for operation in SMBus, I2C Modes
J30 3x1 Header
RX_DET / SCL Dual Function Pin Provision for US1 Device.
Install shunt across pins 1-2 for operation in Pin Mode (Default)
Install shunt across pins 2-3 for operation in SMBus, I2C Modes
J31 3x1 Header
GAIN / SDA Dual Function Pin Provision for US2 Device.
Install shunt across pins 1-2 for operation in Pin Mode (Default)
Install shunt across pins 2-3 for operation in SMBus, I2C Modes
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Table 2-9. EVM Upstream Devices Controls (continued)
COMPONENT NAME FUNCTION / DESCRIPTION
J32 3x1 Header
RX_DET / SCL Dual Function Pin Provision for US2 Device.
Install shunt across pins 1-2 for operation in Pin Mode (Default)
Install shunt across pins 2-3 for operation in SMBus, I2C Modes
J33 3x1 Header
GAIN / SDA Dual Function Pin Provision for US3 Device.
Install shunt across pins 1-2 for operation in Pin Mode (Default)
Install shunt across pins 2-3 for operation in SMBus, I2C Modes
J34 3x1 Header
RX_DET / SCL Dual Function Pin Provision for US3 Device.
Install shunt across pins 1-2 for operation in Pin Mode (Default)
Install shunt across pins 2-3 for operation in SMBus, I2C Modes
J35 3x1 Header
GAIN / SDA Dual Function Pin Provision for US4 Device.
Install shunt across pins 1-2 for operation in Pin Mode (Default)
Install shunt across pins 2-3 for operation in SMBus, I2C Modes
J36 3x1 Header
RX_DET / SCL Dual Function Pin Provision for US4 Device
Install shunt across pins 1-2 for operation in Pin Mode (Default)
Install shunt across pins 2-3 for operation in SMBus, I2C Modes
2.10 Quick-Start Guide (Pin Mode)
Check that the shunts are at the following positions as follows:
1. The redrivers are configured to operate in Pin Mode (MODE pins tied to L0 using J1 header).
2. RX Detect state machine of all redrivers is enabled by leaving J2 open (L4 - floating).
3. The redrivers are enabled (PWDN pins tied to GND by placing a shunt between pins 5-6 on the J4 header).
Alternatively, for PCIe sideband signal control, the PWDN pins can be driven by PCIe Present (PRSNT1#)
signal by leaving J4 open and placing a shunt across pins 1 and 2 of J6, or by inverted PCIe Reset
(PERST#) signal by placing a shunt between pins 3-4 on J4 and by leaving J6 open.
4. The redrivers are connected to RX_DET and GAIN using the dual function pins at headers J17-J24 and
J29-J36 in Table 2-7. Set the shunts for these headers to connect pins 1-2.
5. The board is configured for any PCIe bus width (PRSNTx# signal controls set as 'default' in Table 2-7 using
J7, J8, J9 and J10 headers). Shunts need to be placed between pins 1-2 on headers J7, J8, J9, and J10.
6. DC Gain of all redrivers is set to 0 dB by leaving J14 open for the downstream redrivers and by leaving J26
open for the upstream redrivers.
7. EQ level of the RX CTLEs of all redrivers is set to 10 dB at 16 GHz by using J15 and J16 for the downstream
redrivers and J27 and J28 for the upstream redrivers (EQ1 = L2, EQ0 = L0).
8. If necessary, adjust EQ levels of the downstream redrivers, or upstream redrivers, or both, by arranging
shunts on J15 and J16 for downstream redrivers and J27 and J28 for the upstream redrivers.
9. Plug the EVM into a PCIe x16 server motherboard slot. Make sure the motherboard is powered down before
installing the EVM or configured for hot-plug operation.
10. Install a compatible PCIe endpoint card into the straddle connector of the EVM.
11. Power-up the motherboard.
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2.11 Quick-Start Guide (SMBus / I2C Secondary Mode)
1. Configure all devices to operate in the SMBus Secondary Mode by setting their MODE pins to the L2 level.
This is accomplished by placing a shunt on J1 L2 location.
2. Set a unique SMBus Secondary address for each device by placing shunts in the following arrangement:
• On J15 connector, place shunts in L0 locations for all downstream devices (DS1, DS2, DS3, and DS4) to
set the ADDR1 level for each downstream DS320PR410.
• On J16 connector, place shunts in L0 location for DS1, L1 location for DS2, L2 location for DS3, and in L3
location for DS4 to set the ADDR0 level for each downstream DS320PR410.
• On J27 connector, place shunts in L1 locations for all upstream devices (US1, US2, US3, and US4) to set
the ADDR1 level for each upstream DS320PR410 device.
• On J28 connector, place shunts in L0 location for US1, L1 location for US2, L2 location for US3, and in L3
location for US4 to set the ADDR0 level for each upstream DS320PR410.
• The above arrangement sets the 7-bit SMBus secondary addresses of the DS320PR410 devices as:
– DS1: 0x18
– DS2: 0x1A
– DS3: 0x1C
– DS4: 0x1E
– US1: 0x20
– US2: 0x22
– US3: 0x24
– US4: 0x26
3. Move shunts from pins 1-2 to pins 2-3 on J17-J24, J29-J36 to connect the dual function redriver pins to the
SMBus / I2C bus. Please reference Table 2-7 for guidance on the dual function pins.
4. Make sure all devices by pulling their PWDN pins to GND. This is accomplished by placing a shunt on J4
between pins 5-6 (PWDN and GND). Alternatively, for PCIe sideband signal control, the PWDN pins can be
driven by PCIe Present (PRSNT1#) signal by leaving J4 open and placing a shunt across pins 1 and 2 of
J6, or by inverted PCIe Reset (PERST#) signal by placing a shunt between pins 3-4 on J4 and by leaving J6
open.
5. Select the appropriate adapter using J38 (shunt position 1-2 for USB2ANY or 2-3 for Aardvark). Please
make sure that the correct shunt setting is selected for your adapter. Otherwise, there is risk of damage to
the EVM.
6. Connect a USB2ANY Adapter or Aardvark Adapter to J3 (Note that neither is not supplied with the
DS320PR410-RSC-EVM).
7. Install the latest SigCon Architect application and the DS320PR410 profile. Please contact a local FAE for
download instructions.
8. Plug the EVM into a PCIe x16 server motherboard slot. Make sure the motherboard is powered down before
installing the EVM or configured for hot-plug operation.
9. Install a compatible PCIe endpoint card into the straddle connector of the EVM.
10. Power-up the motherboard.
11. Start the SigCon Architect application.
12. Select the DS320PR410 Configuration Page and click the Apply box to enable the device profile. If
necessary, edit the devices SMBus addresses in the Edit Device Addresses box, then click Apply.
13. In the DS320PR410 High Level Page, select Block Diagram as shown in Figure 2-1.
14. Select the desired EQ Settings.
15. Select devices you want to apply the selected settings and click Apply to All Channels.
Note
To observe the effects of programmed DS320PR410 EQ settings on PCIe lane performance (lane
margin, BER, etc.), the PCIe link must be re-trained by toggling PERST# or by performing a warm
reset (without removing power to the DS320PR410).
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Figure 2-1. SigCon Architect DS320PR410 High-Level Page
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3 Implementation Results
3.1 Test Setup and Results
Figure 3-1 shows a typical system setup with the DS320PR410-RSC-EVM placed between a CPU on a server
motherboard and a PCIe end point (Network Interface Card or NIC). Additional Extender cards are inserted to
increase the channel loss and demonstrate the ability of the redriver to extend the reach.
NIC
7" Extender Card
9" Extender Card
Redriver RSC-EVM
PCIe Gen5.0 CPU
11" Extender Card
Motherboard
Figure 3-1. Example Test Setup
Figure 3-2 is a typical test result achieved with a system shown in Figure 3-1. As the result indicates, the end
point (Nvidia / Mellanox NIC) with the DS320PR410-RSC-EVM placed in the data path achieves a stable Gen5,
x16 PCIe link.
Figure 3-2. Example Test Results
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4 Hardware Design Files
4.1 Schematics
Figure 4-1 through Figure 4-7 illustrate the EVM schematics.
MODE
J6
PRSNT1 PRSNT1
PWDN
GND
3_3V_REG
PRSNT2_1_C PRSNT2_3_C
1
2
3
J7
1
2
3
J9
PRSNT2_1 PRSNT2_3
EEPROM_WP
1uF
C1
PRSNT1PRSNT1
A0
1
A1
2
A2
3
VSS
4SDA 5
SCL 6
WP 7
VCC 8
U1
AT24C02D-SSHM
— T
SCL
RX_DET
SDA
PRSNT2_4_CPRSNT2_2_C
GNDGND 1
2
3
J8
1
2
3
J10
PRSNT2_2 PRSNT2_4
PRSNT1 PRSNT1
GND
3_3V_REG
PWDN
GND 3_3V_REG
249R12
1
2
3
J5
EEPROM_WP
3_3V_REG
GND
3_3V_REG
GND
READ_EN_N
VCC
14 GND 7
U2E
1uF
C2
1
2 3
U2A
3_3V_REG
PGOOD GND
Sample_85_Ohm_P
2 1
D1
330
R14
1
2
J40
2.2k
R3
4
5 6
U2B
GND
SMDAT SDA
DONE_N 3_3V_REG
21
D2
330
R15
3_3V_REG 10
89
U2C
Sample_85_Ohm_N1
2
J39
GND
2 1
D3
330
R16
2.2k
R4
GND
SCL
SMCLK
3_3V_REG
10.0k
R13
GND
1112
13 U2D
124R5
1.02kR6
3.09kR7
9.31kR98
124R8
1.02kR9
3.09kR10
9.31kR99
PERST#
10.0k
R32
3_3V_REG
10.0k
R31
GND
PERST_INV
PWDN PERST_INV
1 2
3 4
5 6
J4
TSW-103-07-G-D
1 2
3 4
5 6
7 8
9 10
J3
5103311-1
S2B
1S2A
2
S3B
3S3A
5
EN
6
S1A
12
S1B
13
VDD
16
D3 4
VSS 7
GND 8
SEL3 9
SEL2 10
SEL1 11
D1 14
D2 15
TMUX1133PWR
U4
1
2
3
J38
SCL
SDA
GND
1.0k
R29
SDA
SCL
GND
3_3V_REG
1.0k
R30
GND
1.0k
R11
1 4
2 3
SW1
1
2
3
J41
MODE
RX_DET
PRSNT2_1
PRSNT2_2
PRSNT2_3
PRSNT2_4
1
2
J42
GND
1
2
J43
GND
PGOOD
DONE_N
SMDAT
SMCLK
1
2
J44
1
2
J45
1 2
3 4
5 6
7 8
J1
5-146256-4
1 2
3 4
5 6
7 8
J2
5-146256-4
Global Controls EEPROM Loader PRSNT and PWDN Logic
Status LEDs
Te st Traces - should be 8 5 Ohmhigh -speed dif fer entialimpedence
Five-level select: - divided by 8
or M ODE and RX_DET, as
ey are global to 8 devices
DS320PR410 Pin StrapL evels:
L0: 1k to GND
L1: 8.25k to GND
L2: 24.9k to GND
L3: 75k to GND
L4: Float
MODE and RX_DET global pin
strap levels (8 de vices):
L0: 124 to GND
L1: 1.02k to GND
L2: 3.09k to GND
L3: 9.31k to GND
L4: Float
PWDNLo gic:
1-2: Pull high (device powere d off)
3-4: Contr ol with PERST_INV
5-6: Pull low (de vice powered on)
I2C Adapter Select
1-2 = USB2ANY
2-3 = Aardvark
C Connector
Force EEPROM Read Button
READ_EN_N:
1-2 = PU
2-3 = GND
Figure 4-1. Control and Status Schematic Page
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12V +/-20%, 0.5A MAX
J11
12V
VSENSE trace goes to furthest DS320PR410
3.3V, 2A MAX3_3V_REG J13
165k
R17
22uF
C4
22uF
C5
1uF
C7
0.1uF
C9 PGOOD PGOOD
100uF
C3
4.7uF
C6
120k
R18
3_3V_REG
6.8uH
L1
J12
10.0k
R27
PGOOD
GND 100k
R19
100k
R21
100k
R23
105k
R25
10uF
C13
1µF
C15
100uF
C10
100uF
C11
4.7uF
C14
470nF
C16
100nF
C17
NU
1
NU
2
NU
3
EN_UVLO
4
BOOT 5
NC 6
NC 7
SW 8
SW 9
SW 10
SW 11
SW 12
PGND 13
PGND 14
PGND 15
PGND 16
PGND 17
PGND 18
PGND 19
PGND 20
PVIN
21
PVIN
22
PVIN
23
PVIN
24
PVIN
25
NC 26
NC 27
VDD
28
DRGND
29
AGND
30
BP
31
FSEL
32
VSEL
33
MODE
34
PGOOD
35
ILIM
36
RESV_TRK
37
RSN 38
RSP 39
VOSNS 40
PAD 41
TPS548B22RVFR
U3
4.7uF
C8
5.76k
R28
165k
R20
37.4k
R22
42.2k
R24
2.05k
R26
GND
GND
47uF
C12
Figure 4-2. Voltage Regulator Schematic Page
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3_3VGND
12V
PER9_C_N PER9_C_P PER10_C_P PER11_C_P PER10_C_N PER7_C_P PER6_C_N PER7_C_N PER8_C_N PER8_C_P PER14_C_N PER14_C_P PER15_C_P PER1_C_N PER15_C_N PER12_C_P PER11_C_N PER12_C_N PER13_C_N PER13_C_P REFCLK_P PERST# REFCLK_N PER0_C_N PER0_C_P PER4_C_N PER4_C_P PER5_C_P PER6_C_P PER5_C_N PER2_C_P PER1_C_P PER2_C_N PER3_C_N PER3_C_P JTAG2 JTAG3 JTAG4 JTAG5 PRSNT1 RSVD1 RSVD3 RSVD4 RSVD5
GND GND GND
GND GND
0.22uF C50
0.22uF C51
0.22uF C52
0.22uF C53
0.22uF C57
0.22uF C58
0.22uF C59
0.22uF C60
0.22uF C65 0.22uF C66
0.22uF C67
0.22uF C68
0.22uF C69
0.22uF C74
0.22uF C75
0.22uF C76
0.22uF C77
0.22uF C78
0.22uF C79
0.22uF C80 0.22uF C81 0.22uF C82
0.22uF C83
0.22uF C84
0.22uF C85
0.22uF C86
0.22uF C87
0.22uF C88
0.22uF C89
0.22uF C90
0.22uF C91
0.22uF C92
GND GND GND
GND GND GND
GND GND GND GND GND GND GND GND
GND GND
GND GND GND GND GND GND
GND GND
GND GND GND GND GND
RSVD1 RSVD3
RSVD4 RSVD5
PERC0_P PERC8_N PERC9_P
PERC9_N PERC8_P PERC6_N PERC7_P
PERC7_N PERC15_P PERC12_P PERC11_P
PERC11_N PERC12_N PERC10_P PERC15_N PERC10_N PERC6_P PERC0_N PERC1_P
PERC1_N PERC14_P PERC13_P
PERC13_N PERC14_N PERC2_P PERC5_N
PERC5_P PERC4_N
PERC4_P PERC2_N PERC3_P
PERC3_N
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
ONN1A
EN5_ PCI e- x 1 6_ EDGE_CONN
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
CONN1B
GEN5_ PCI e- x 1 6_ EDGE_CONN
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
CONN1C
GEN5_ PCI e- x 1 6_ EDGE_CONN
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
ONN1D
EN5_ PCI e- x 1 6_ EDGE_CONN
GND
RSVD CLKREQ
12V
PRSNT2_1 PRSNT2_2 PRSNT2_3 PRSNT2_4 RSVD2
PET10_P
PET9_N
PET11_P
PET10_N
PET9_P PET7_N PET7_P PET8_N PET8_P
PET14_N
PET14_P
PET15_N
PET15_P
PET13_N
PET12_P
PET11_N
PET13_P
PET12_N
PET1_P PET0_N PET2_P PET1_N PET0_P
SMDAT
SMCLK
CLKREQ
WAKE
PET5_N PET5_P PET6_N PET6_P PET4_N PET3_P PET2_N PET4_P PET3_N
RSVD
JTAG1
PRSNT2_1
PRSNT2_2 PRSNT2_3 PRSNT2_4
RSVD2
3_3VAUX
3_3V GND
RSVD
1pFC54 1pFC61 1pFC70
PRSNT2_2
43
R87
43
R90
43
R94
RSVD5
CLKREQ
1pFC55 1pFC62 1pFC71
PRSNT2_3
43
R88
43
R91
43
R95
RSVD2
1pFC56 1pFC63 1pFC72
PRSNT2_1PRSNT2_4
43
R89
43
R92
43
R96
RSVD3
1pFC64 1pFC73
43
R93
43
R97
RSVD1RSVD4
GND GNDGND
Trace im pe den ce f o r st atic s ignals
bein g termin ated wit h 1pF and 43
Oh ms ho uld b e 50 Ohm s (up t o th e
43 Oh m res is to r)
Figure 4-3. Gold Finger Connector Schematic Page
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GND
GAIN_DS
GAIN_DS
1
2
3
J17
GAIN_SDA_DS1
SDA
RX_DET
1
2
3
J18
RX_DET_SCL_DS1
SCL
GAIN_DS
1
2
3
J19
GAIN_SDA_DS2
SDA
RX_DET
1
2
3
J20
RX_DET_SCL_DS2
SCL
GAIN_DS
1
2
3
J21
GAIN_SDA_DS3
SDA
RX_DET
1
2
3
J22
RX_DET_SCL_DS3
SCL
GAIN_DS
1
2
3
J23
GAIN_SDA_DS4
SDA
RX_DET
1
2
3
J24
RX_DET_SCL_DS4
SCL
RX_DET_SCL_DS1
PET0_P
PET0_N
PET1_P
PET1_N
PET2_P
PET2_N
PET3_P
PET3_N
PET0_C_P
PET0_C_N
PET1_C_P
PET1_C_N
PET2_C_P
PET2_C_N
PET3_C_P
PET3_C_N
VCC
14
VCC
15
VCC
34
VCC
35
TX0N 19
TX0P 20
TX1N 16
TX1P 17
TX2N 12
TX2P 13
TX3N 9
TX3P 10
EQ0/ AD DR0
23
EQ1/ AD DR1
24
RX0N
30 RX0P
29
RX1N
33 RX1P
32
RX2N
37 RX2P
36
RX3N
40 RX3P
39
RX_DET/ SCL
26
DONE
7
READ_EN 22
GAI N/ SDA
27
MODE
25
PD
6
SEL 2
NC 3
NC 4
NC 5
GND 1
GND 8
GND 11
GND 18
GND 21
GND 28
GND 31
GND 38
THERMAL_PAD 41
DS320PR410RNQ
DS1
GND
MODE
SCL
SDA
PWDN
READ_EN_N
SCL
SDA
READ_EN_N
PWDN
MODE
DONE_N_DS DONE_N_DS
RX_DET RX_DET
MODE
READ_EN_N
GAIN_SDA_DS1
PWDN
4.70k
R57
3_3V_REG
0.1uF
C28
0.1uF
C26
1uF
C125
GND
0.1uF
C29
0.1uF
C27
1uF
C126
GND
0.1uF
C19
0.1uF
C18
1uF
C22
GND
0.1uF
C24
0.1uF
C23
1uF
C35
GND
3_3V_REG
3_3V_REG
DONE_N_DS1
RX_DET_SCL_DS2
PET4_P
PET4_N
PET5_P
PET5_N
PET6_P
PET6_N
PET7_P
PET7_N
PET4_C_P
PET4_C_N
PET5_C_P
PET5_C_N
PET6_C_P
PET6_C_N
PET7_C_P
PET7_C_N
VCC
14
VCC
15
VCC
34
VCC
35
TX0N 19
TX0P 20
TX1N 16
TX1P 17
TX2N 12
TX2P 13
TX3N 9
TX3P 10
EQ0/ AD DR0
23
EQ1/ AD DR1
24
RX0N
30 RX0P
29
RX1N
33 RX1P
32
RX2N
37 RX2P
36
RX3N
40 RX3P
39
RX_D ET/ SCL
26
DONE
7
READ_EN 22
GAI N/ SDA
27
MODE
25
PD
6
SEL 2
NC 3
NC 4
NC 5
GND 1
GND 8
GND 11
GND 18
GND 21
GND 28
GND 31
GND 38
THERMAL_PAD 41
DS320PR410RNQ
DS2
GND
MODE
DONE_N_DS1
GAIN_SDA_DS2
PWDN
4.70k
R58
3_3V_REG
3_3V_REG
DONE_N_DS2
RX_DET_SCL_DS3
PET8_P
PET8_N
PET9_P
PET9_N
PET10_P
PET10_N
PET11_P
PET11_N
PET8_C_P
PET8_C_N
PET9_C_P
PET9_C_N
PET10_C_P
PET10_C_N
PET11_C_P
PET11_C_N
VCC
14
VCC
15
VCC
34
VCC
35
TX0N 19
TX0P 20
TX1N 16
TX1P 17
TX2N 12
TX2P 13
TX3N 9
TX3P 10
EQ0/ AD DR0
23
EQ1/ AD DR1
24
RX0N
30 RX0P
29
RX1N
33 RX1P
32
RX2N
37 RX2P
36
RX3N
40 RX3P
39
RX_D ET/ SCL
26
DONE
7
READ_EN 22
GAI N/ SDA
27
MODE
25
PD
6
SEL 2
NC 3
NC 4
NC 5
GND 1
GND 8
GND 11
GND 18
GND 21
GND 28
GND 31
GND 38
THERMAL_PAD 41
DS320PR410RNQ
DS3
GND
MODE
DONE_N_DS2
GAIN_SDA_DS3
PWDN
4.70k
R59
3_3V_REG
3_3V_REG
DONE_N_DS3
RX_DET_SCL_DS4
PET12_P
PET12_N
PET13_P
PET13_N
PET14_P
PET14_N
PET15_P
PET15_N
PET12_C_P
PET12_C_N
PET13_C_P
PET13_C_N
PET14_C_P
PET14_C_N
PET15_C_P
PET15_C_N
VCC
14
VCC
15
VCC
34
VCC
35
TX0N 19
TX0P 20
TX1N 16
TX1P 17
TX2N 12
TX2P 13
TX3N 9
TX3P 10
EQ0/ AD DR0
23
EQ1/ AD DR1
24
RX0N
30 RX0P
29
RX1N
33 RX1P
32
RX2N
37 RX2P
36
RX3N
40 RX3P
39
RX_DET/ SCL
26
DONE
7
READ_EN 22
GAI N/ SDA
27
MODE
25
PD
6
SEL 2
NC 3
NC 4
NC 5
GND 1
GND 8
GND 11
GND 18
GND 21
GND 28
GND 31
GND 38
THERMAL_PAD 41
DS320PR410RNQ
DS4
GND
MODE
DONE_N_DS3
GAIN_SDA_DS4
PWDN
4.70k
R64
3_3V_REG
3_3V_REG
DONE_N_DS
EQ1_AD1_DS1 1.00kR33
8.25kR34
24.9kR35
75.0kR101
EQ1_AD1_DS2 1.00kR36
8.25kR37
24.9kR38
75.0kR102
EQ1_AD1_DS3
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15
17
19
21
23
25
27
29
31
16
18
20
22
24
26
28
30
32
33 34
J15
TSW-117-08-L-D
1.00kR39
8.25kR40
24.9kR41
75.0kR103
EQ1_AD1_DS4 1.00kR42
8.25kR43
24.9kR44
75.0kR104
GND
EQ0_AD0_DS1 1.00kR45
8.25kR46
24.9kR47
75.0kR105
EQ0_AD0_DS2 1.00kR48
8.25kR49
24.9kR50
75.0kR106
EQ0_AD0_DS3
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15
17
19
21
23
25
27
29
31
16
18
20
22
24
26
28
30
32
33 34
J16
TSW-117-08-L-D
1.00kR51
8.25kR52
24.9kR53
75.0kR107
EQ0_AD0_DS4 1.00kR54
8.25kR55
24.9kR56
75.0kR108
GND
EQ0_AD0_DS3
EQ1_AD1_DS3
EQ0_AD0_DS2
EQ1_AD1_DS2
EQ0_AD0_DS1
EQ1_AD1_DS1
EQ0_AD0_DS4
EQ1_AD1_DS4
249R60
2.05kR61
6.19kR62
18.7kR63
1 2
3 4
5 6
7 8
J14
5-146256-4
0.1uF
C30
0.1uF
C32
0.1uF
C31
0.1uF
C33
0.1uF
C20
0.1uF
C21
0.1uF
C25
0.1uF
C34
1uF
C133
1uF
C134
1uF
C135
1uF
C136
1uF
C137
1uF
C138
1uF
C139
1uF
C140
Device Power Decoupling. Place close to pin of each DS320PR410.
Downstreamp in-mode settingsDownstream Device-Specific Settings
Global I/Os
Figure 4-4. Downstream Devices Schematic Page
Hardware Design Files www.ti.com
18 DS320PR410-RSC-EVM Evaluation Module SNLU334 – DECEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

GND
GAIN_US
GAIN_US
1
2
3
J29
GAIN_SDA_US1
SDA
RX_DET
1
2
3
J30
RX_DET_SCL_US1
SCL
GAIN_US
1
2
3
J31
GAIN_SDA_US2
SDA
RX_DET
1
2
3
J32
RX_DET_SCL_US2
SCL
GAIN_US
1
2
3
J33
GAIN_SDA_US3
SDA
RX_DET
1
2
3
J34
RX_DET_SCL_US3
SCL
GAIN_US
1
2
3
J35
GAIN_SDA_US4
SDA
RX_DET
1
2
3
J36
RX_DET_SCL_US4
SCL
RX_DET_SCL_US1
PER0_P
PER0_N
PER1_P
PER1_N
PER2_P
PER2_N
PER3_P
PER3_N
PER0_C_P
PER0_C_N
PER1_C_P
PER1_C_N
PER2_C_P
PER2_C_N
PER3_C_P
PER3_C_N
VCC
14
VCC
15
VCC
34
VCC
35
TX0N 19
TX0P 20
TX1N 16
TX1P 17
TX2N 12
TX2P 13
TX3N 9
TX3P 10
EQ0/ AD DR0
23
EQ1/ AD DR1
24
RX0N
30 RX0P
29
RX1N
33 RX1P
32
RX2N
37 RX2P
36
RX3N
40 RX3P
39
RX_DET/ SCL
26
DONE
7
READ_EN 22
GAI N/ SDA
27
MODE
25
PD
6
SEL 2
NC 3
NC 4
NC 5
GND 1
GND 8
GND 11
GND 18
GND 21
GND 28
GND 31
GND 38
THERMAL_PAD 41
DS320PR410RNQ
US1
GND
MODE
SCL
SDA
PWDN
DONE_N_DS
SCL
SDA
DONE_N_DS
PWDN
MODE
DONE_N DONE_N
RX_DET RX_DET
MODE
DONE_N_DS
GAIN_SDA_US1
PWDN
4.70k
R65
3_3V_REG
0.1uF
C37
0.1uF
C36
1uF
C40
GND
0.1uF
C42
0.1uF
C41
1uF
C45
GND
0.1uF
C47
0.1uF
C46
1uF
C127
GND
0.1uF
C129
0.1uF
C128
1uF
C132
GND
3_3V_REG
3_3V_REG
DONE_N_US1
RX_DET_SCL_US2
PER4_P
PER4_N
PER5_P
PER5_N
PER6_P
PER6_N
PER7_P
PER7_N
PER4_C_P
PER4_C_N
PER5_C_P
PER5_C_N
PER6_C_P
PER6_C_N
PER7_C_P
PER7_C_N
VCC
14
VCC
15
VCC
34
VCC
35
TX0N 19
TX0P 20
TX1N 16
TX1P 17
TX2N 12
TX2P 13
TX3N 9
TX3P 10
EQ0/ AD DR0
23
EQ1/ AD DR1
24
RX0N
30 RX0P
29
RX1N
33 RX1P
32
RX2N
37 RX2P
36
RX3N
40 RX3P
39
RX_D ET/ SCL
26
DONE
7
READ_EN 22
GAI N/ SDA
27
MODE
25
PD
6
SEL 2
NC 3
NC 4
NC 5
GND 1
GND 8
GND 11
GND 18
GND 21
GND 28
GND 31
GND 38
THERMAL_PAD 41
DS320PR410RNQ
US2
GND
MODE
DONE_N_US1
GAIN_SDA_US2
PWDN
4.70k
R66
3_3V_REG
3_3V_REG
DONE_N_US2
RX_DET_SCL_US3
PER8_P
PER8_N
PER9_P
PER9_N
PER10_P
PER10_N
PER11_P
PER11_N
PER8_C_P
PER8_C_N
PER9_C_P
PER9_C_N
PER10_C_P
PER10_C_N
PER11_C_P
PER11_C_N
VCC
14
VCC
15
VCC
34
VCC
35
TX0N 19
TX0P 20
TX1N 16
TX1P 17
TX2N 12
TX2P 13
TX3N 9
TX3P 10
EQ0/ AD DR0
23
EQ1/ AD DR1
24
RX0N
30 RX0P
29
RX1N
33 RX1P
32
RX2N
37 RX2P
36
RX3N
40 RX3P
39
RX_D ET/ SCL
26
DONE
7
READ_EN 22
GAI N/ SDA
27
MODE
25
PD
6
SEL 2
NC 3
NC 4
NC 5
GND 1
GND 8
GND 11
GND 18
GND 21
GND 28
GND 31
GND 38
THERMAL_PAD 41
DS320PR410RNQ
US3
GND
MODE
DONE_N_US2
GAIN_SDA_US3
PWDN
4.70k
R67
3_3V_REG
3_3V_REG
DONE_N_US3
RX_DET_SCL_US4
PER12_P
PER12_N
PER13_P
PER13_N
PER14_P
PER14_N
PER15_P
PER15_N
PER12_C_P
PER12_C_N
PER13_C_P
PER13_C_N
PER14_C_P
PER14_C_N
PER15_C_P
PER15_C_N
VCC
14
VCC
15
VCC
34
VCC
35
TX0N 19
TX0P 20
TX1N 16
TX1P 17
TX2N 12
TX2P 13
TX3N 9
TX3P 10
EQ0/ AD DR0
23
EQ1/ AD DR1
24
RX0N
30 RX0P
29
RX1N
33 RX1P
32
RX2N
37 RX2P
36
RX3N
40 RX3P
39
RX_DET/ SCL
26
DONE
7
READ_EN 22
GAI N/ SDA
27
MODE
25
PD
6
SEL 2
NC 3
NC 4
NC 5
GND 1
GND 8
GND 11
GND 18
GND 21
GND 28
GND 31
GND 38
THERMAL_PAD 41
DS320PR410RNQ
US4
GND
MODE
DONE_N_US3
GAIN_SDA_US4
PWDN
4.70k
R110
3_3V_REG
3_3V_REG
DONE_N
EQ1_AD1_US1 1.00kR72
8.25kR73
24.9kR74
75.0kR75
EQ1_AD1_US2 1.00kR76
8.25kR77
24.9kR78
75.0kR79
EQ1_AD1_US3
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15
17
19
21
23
25
27
29
31
16
18
20
22
24
26
28
30
32
33 34
J27
TSW-117-08-L-D
1.00kR80
8.25kR81
24.9kR82
75.0kR83
EQ1_AD1_US4 1.00kR84
8.25kR85
24.9kR86
75.0kR100
GND
EQ0_AD0_US1 1.00kR109
8.25kR111
24.9kR112
75.0kR113
EQ0_AD0_US2 1.00kR114
8.25kR115
24.9kR116
75.0kR117
EQ0_AD0_US3
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15
17
19
21
23
25
27
29
31
16
18
20
22
24
26
28
30
32
33 34
J28
TSW-117-08-L-D
1.00kR119
8.25kR120
24.9kR121
75.0kR122
EQ0_AD0_US4 1.00kR123
8.25kR124
24.9kR125
75.0kR126
GND
EQ0_AD0_US3
EQ1_AD1_US3
EQ0_AD0_US2
EQ1_AD1_US2
EQ0_AD0_US1
EQ1_AD1_US1
EQ0_AD0_US4
EQ1_AD1_US4
249R68
2.05kR69
6.19kR70
18.7kR71
1 2
3 4
5 6
7 8
J26
5-146256-4
0.1uF
C38
0.1uF
C39
0.1uF
C43
0.1uF
C44
0.1uF
C48
0.1uF
C49
0.1uF
C130
0.1uF
C131
1uF
C141
1uF
C142
1uF
C143
1uF
C144
1uF
C145
1uF
C146
1uF
C147
1uF
C148
Device Power Decoupling. Place close to pin of each DS320PR410.
Upstreamp in-mode settingsUpstream Device-Specific Settings
Global I/Os
Figure 4-5. Upstream Devices Schematic Page
www.ti.com Hardware Design Files
SNLU334 – DECEMBER 2023
Submit Document Feedback
DS320PR410-RSC-EVM Evaluation Module 19
Copyright © 2023 Texas Instruments Incorporated

12V PET6C_N PET6_C_N
0.22uF
C106
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
CONN2A
10 1 6310 6 - A4 1410 HLF
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
CONN2B
10 1 6310 6 - A4 1410 HLF
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
CONN2D
10 1 63 10 6- A4 1 41 0HLF
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
CONN2C
10 1 63 10 6- A4 1 41 0HLF
PRSNT1
12V PER6_P
PER6_N
PET7_C_P
PET7C_P
0.22uF
C107 PET7_C_N
PET7C_N
SMCLK 0.22uF
C108
JTAG2
SMDATPER7_PJTAG3
PRSNT2_3_CPER7_NJTAG4
3_3V
JTAG5
PET8_C_P3_3V PET8C_P
0.22uF
C109
JTAG1RSVD5
PET8C_N PET8_C_N3_3VAUX 0.22uF
C110
PERST# WAKEPER8_P
PER8_N CLKREQ
PET9_C_PREFCLK_P PET9C_P 0.22uF
C111
PET9C_N
PET0_C_P
PET0C_P
REFCLK_N PET9_C_N
0.22uF
C93
0.22uF
C112
PET0_C_NPER9_P PET0C_N 0.22uF
C94
PER9_NPER0_P
PET10C_P PET10_C_PPER0_N PRSNT2_1_C 0.22uF
C113 PET10_C_N
PET10C_N
0.22uF
C114
PET1C_P PET1_C_PPER10_P
0.22uF
C95
RSVD1
PET1C_N PET1_C_NPER10_N 0.22uF
C96 PET11C_P
PER1_P PET11_C_P
0.22uF
C115
PET11C_N
PER1_N PET11_C_N
0.22uF
C116
PER11_P PET2C_P PET2_C_P
0.22uF
C97
PET2C_N PET2_C_NPER11_N 0.22uF
C98
PER2_P PET12_C_P
PET12C_P 0.22uF
C117
PET12C_N
PER2_N PET12_C_N
0.22uF
C118
PET3C_P
PER12_P PET3_C_P
0.22uF
C99
PER12_N PET3_C_N
PET3C_N
0.22uF
C100 PET13_C_PPER3_P PET13C_P
0.22uF
C119
PER3_N PET13_C_N
PET13C_N
0.22uF
C120
RSVD2
PER13_P PRSNT2_2_C
PER13_NRSVD3
PET14_C_PPET4_C_P
PET4C_P PET14C_P0.22uF
C101
0.22uF
C121
RSVD4
PET14C_NPET4C_N PET14_C_NPET4_C_N
0.22uF
C102
0.22uF
C122
PER14_PPER4_P
PER14_NPER4_N
PET5_C_P PET15_C_P
PET5C_P PET15C_P0.22uF
C103
0.22uF
C123
PET15_C_N
PET15C_N
PET5_C_N
PET5C_N
0.22uF
C104
0.22uF
C124
PER15_PPER5_P
PER15_N PRSNT2_4_CPER5_N
PET6C_P PET6_C_P RSVD
0.22uF
C105
GND
GND GNDGND
Figure 4-6. Straddle Connector Schematic Page
Hardware Design Files www.ti.com
20 DS320PR410-RSC-EVM Evaluation Module SNLU334 – DECEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated