Texas Instruments DS90UB960-Q1EVM User manual

User’s Guide
DS90UB960-Q1EVM User's Guide
Davor Glisic
ABSTRACT
The Texas Instruments DS90UB960-Q1EVM Evaluation Module (EVM) is a functional board design for
evaluating the DS90UB960-Q1 FPD-Link III and TDES960 V3Link deserializer hubs, which convert serialized
sensor data to MIPI CSI-2 for processing. It is configured for communication with up to four DS90UB953-Q1
or TSER953 serializers using a Quad Mini-Fakra to 4x Single FAKRA cable assembly. An on-board MSP430
coupled with Analog LaunchPAD GUI tool enables interface to a PC for easy device evaluation.
Table of Contents
1 Introduction.............................................................................................................................................................................3
2 Features...................................................................................................................................................................................4
3 Application Diagram...............................................................................................................................................................4
4 Major Components................................................................................................................................................................. 5
5 Quick Start Guide....................................................................................................................................................................6
6 Board Connections.................................................................................................................................................................7
6.1 Power Supply..................................................................................................................................................................... 7
6.2 Power Over Coax Interface................................................................................................................................................7
6.3 MIPI CSI-2 Output Signals................................................................................................................................................. 9
6.4 FPD-Link III Signals......................................................................................................................................................... 12
6.5 I2C Interface..................................................................................................................................................................... 12
6.6 Control Interface...............................................................................................................................................................13
7 Enable and Reset..................................................................................................................................................................14
8 ALP Software Setup..............................................................................................................................................................15
8.1 System Requirements......................................................................................................................................................15
8.2 Download Contents..........................................................................................................................................................15
8.3 Installation of the ALP Software....................................................................................................................................... 15
8.4 Startup - Software Description......................................................................................................................................... 16
8.5 Information Tab................................................................................................................................................................ 17
8.6 Registers Tab................................................................................................................................................................... 18
8.7 Registers Tab - Address 0x00 Selected........................................................................................................................... 18
8.8 Registers Tab - Address 0x00 Expanded.........................................................................................................................19
8.9 Scripting Tab.................................................................................................................................................................... 20
8.10 Sample ALP Python Script.............................................................................................................................................20
8.10.1 Initialization..............................................................................................................................................................20
9 Troubleshooting ALP Software........................................................................................................................................... 23
9.1 ALP Loads the Incorrect Profile....................................................................................................................................... 23
9.2 ALP does not detect the EVM.......................................................................................................................................... 25
10 Typical Connection and Test Equipment..........................................................................................................................27
11 Termination Device............................................................................................................................................................. 27
12 Typical Test Setup...............................................................................................................................................................27
13 Equipment References.......................................................................................................................................................28
14 Cable References................................................................................................................................................................28
15 Bill of Materials................................................................................................................................................................... 29
16 PCB Schematics................................................................................................................................................................. 36
17 Board Layout.......................................................................................................................................................................43
18 Revision History................................................................................................................................................................. 48
List of Figures
Figure 1-1. DS90UB960-Q1EVM.................................................................................................................................................3
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Figure 3-1. Applications Diagram................................................................................................................................................ 4
Figure 4-1. Interfacing to the EVM...............................................................................................................................................5
Figure 5-1. DS90UB960-Q1EVM Jumper and Switch Configuration...........................................................................................6
Figure 6-1. Power-over-Coax Network Compatible with DS90UB935-Q1 and DS90UB953-Q1.................................................7
Figure 6-2. Power-over-Coax Network Compatible with DS90UB913A-Q1, DS90UB933-Q1, DS90UB935-Q1, and
DS90UB953-Q1....................................................................................................................................................................... 8
Figure 8-1. Launching ALP........................................................................................................................................................ 16
Figure 8-2. Initial ALP Screen....................................................................................................................................................16
Figure 8-3. Follow-up Screen.................................................................................................................................................... 17
Figure 8-4. ALP Information Tab................................................................................................................................................17
Figure 8-5. ALP Registers Tab...................................................................................................................................................18
Figure 8-6. ALP Device ID Selected.......................................................................................................................................... 18
Figure 8-7. ALP Device ID Expanded........................................................................................................................................19
Figure 8-8. ALP Scripting Tab....................................................................................................................................................20
Figure 9-1. USB2ANY Setup..................................................................................................................................................... 23
Figure 9-2. Remove Incorrect Profile.........................................................................................................................................23
Figure 9-3. Add Correct Profile.................................................................................................................................................. 24
Figure 9-4. Finish Setup............................................................................................................................................................ 24
Figure 9-5. ALP No Devices Error............................................................................................................................................. 25
Figure 9-6. Windows 7, ALP USB2ANY Driver..........................................................................................................................25
Figure 9-7. ALP in Demo Mode................................................................................................................................................. 26
Figure 9-8. ALP Preferences Menu........................................................................................................................................... 26
Figure 12-1. Typical Test Setup for Application......................................................................................................................... 27
Figure 12-2. Typical Test Setup for Evaluation.......................................................................................................................... 27
Figure 17-1. Top View Composite..............................................................................................................................................43
Figure 17-2. Layer 1: Top Signal Layer......................................................................................................................................43
Figure 17-3. Layer 2: GND 1 Layer........................................................................................................................................... 44
Figure 17-4. Layer 3: Inner Signal 1 Layer................................................................................................................................ 44
Figure 17-5. Layer 4: GND 2 Layer........................................................................................................................................... 45
Figure 17-6. Layer 5: GND 3 Layer........................................................................................................................................... 45
Figure 17-7. Layer 6: Inner Signal 2 Layer................................................................................................................................ 46
Figure 17-8. Layer 7: GND 4 Layer........................................................................................................................................... 46
Figure 17-9. Layer 8: Bottom Signal Layer................................................................................................................................ 47
Figure 17-10. Bottom Overlay....................................................................................................................................................47
List of Tables
Table 6-1. Power Supply..............................................................................................................................................................7
Table 6-2. Required PoC Network Updates for Compatibility to DS90UB913A-Q1 and DS90UB933-Q1 Serializers.................9
Table 6-3. Power-Over-Coax Power Supply Feed Configuration................................................................................................ 9
Table 6-4. MIPI CSI-2 (TX Port 0) Output Signals - J1 Pinout................................................................................................... 10
Table 6-5. MIPI CSI-2 (TX Port 1) Output Signals - J3 Pinout................................................................................................... 10
Table 6-6. MIPI CSI-2 Output Signals - J2 Pinout......................................................................................................................11
Table 6-7. FPD-Link III Signals.................................................................................................................................................. 12
Table 6-8. IDx I2C Device Address Select - J34........................................................................................................................ 12
Table 6-9. Primary I2C Interface Header - J4.............................................................................................................................12
Table 6-10. Secondary I2C Interface Header - J5...................................................................................................................... 12
Table 6-11. I2C VDDIO Interface Header - J30.......................................................................................................................... 13
Table 6-12. VDDIO Interface Header - J1..................................................................................................................................13
Table 6-13. GPIO Interface Header - J8.................................................................................................................................... 13
Table 6-14. CMLOUTP Output Signals......................................................................................................................................13
Table 6-15. Mode SW-DIP4 - S1 ...............................................................................................................................................13
Table 6-16. Control SW-DIP2 - SW1..........................................................................................................................................13
Table 6-17. LEDs....................................................................................................................................................................... 13
Table 15-1. BOM for DS90UB960-Q1EVM ...............................................................................................................................29
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1 Introduction
The Texas Instruments DS90UB960-Q1EVM evaluation module (EVM) is a functional board design for
evaluating the DS90UB960-Q1, which is a versatile deserializer hub capable of connecting serialized sensor
data received from up to 4 independent data streams through an FPD-Link III interface using standard coaxial
cables. When coupled with DS90UB953-Q1 serializer, the DS90UB960-Q1 receives data from 2-Megapixel
imagers supporting full HD 1080p resolution at 60 Hz frame rates. The DS90UB960-Q1 merges and manages
multiple data streams into a MIPI CSI-2 compliant output for interconnect to a downstream processor.
The DS90UB960-Q1EVM is configured for communication with up to four DS90UB953-Q1 serializers. It features
a quad mini-FAKRA connector, a Quad Mini-Fakra to 4x Single FAKRA cable assembly, and configurable
power-over-coax voltage for connecting up to four camera modules (not included). Each of the FPD-Link III
interfaces also includes a separate low latency bi-directional control channel that conveys control information
from an I2C port. General purpose I/O signals such as those required for camera synchronization and functional
safety features also make use of this bi-directional control channel to program registers in the DS90UB960-Q1
as well as the connected serializers and any remote I2C device attached to the serializers. The EVM also
features an on-board MSP430 which functions as a USB2ANY bridge for interfacing with a PC for evaluation.
The USB2ANY interfaces with the Analog LunchPAD GUI tool.
Note
The EVM is not intended for EMI testing. The EVM was designed for easy accessibility to device
pins with tap points for monitoring or applying signals, additional pads for termination, and multiple
connector options.
Figure 1-1. DS90UB960-Q1EVM
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2 Features
The major components of the DS90UB960-Q1EVM are:
• DS90UB960-Q1
– Aggregates data from up to 4 cameras over FPD-Link III interface
– Supports 2-Megapixel sensors with HD 1080p resolution at 30/60Hz frame rate (when paired w/
DS90UB953-Q1)
– Multi-camera synchronization
– Supports MIPI DPHY 1.2 / CSI-2 Version 1.3 compliant
• 2x CSI-2 output ports
• Supports 1, 2, 3, 4 data lanes per CSI-2 port
• CSI-2 data rate scalable for 400 Mbps / 800 Mbps / 1.2 Gbps / 1.6 Gbps per data lane
• Programmable data types
• Four Virtual Channels
• ECC and CRC generation
– Supports Single-ended Coax cable and Power-Over-Coax
– Adaptive receive equalization
– I2C with Fast-mode Plus up to 1 Mbps
– Flexible GPIOs for camera sync and functional safety
• On-board Power-over-Coax (POC) interface
• Quad Mini-Fakra connector and Quad Mini-Fakra to 4x Fakra coax cable assembly for FPD-Link III interfaces
• Samtec QSH type connectors for CSI-2 interfaces
• On-board I2C programming interface
3 Application Diagram
MIPI CSI-2
Processor
SoC
DS90UB960-Q1
FPD-Link III HUB
FPD-Link III
Serializer
I2C
FPD-Link III
Coax or STP
FPD-Link III
Serializer
FPD-Link III
Serializer
FPD-Link III
Serializer
TX Port0:
Up to 4 Lanes
TX Port1:
Up to 4 Lanes
GPIO
INTB
Figure 3-1. Applications Diagram
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4 Major Components
Figure 4-1 illustrates major DS90UB960-Q1EVM components.
1. Quad Mini-Fakra connector for FPD-Link III interfaces. There is also a Quad Mini-Fakra to 4x Single Fakra
coax cable assembly (not shown) for interfacing the EVM to up to four sensor modules
2. Samtec QSH type connectors for interfacing the CSI-2 I/Os to downstream processors
3. Switches for configuring DS90UB960-Q1 functional modes
4. USB2ANY connector for interfacing the EVM to a PC
5. Connectors for accessing DS90UB960-Q1 I2C Ports
6. Connectors for accessing DS90UB960-Q1 GPIOs
7. Barrel jack type connector for powering the DS90UB960-Q1EVM from a single 12V/1A supply
8. Connectors for selecting PoC voltage source
FPD-LINK III I/O
MIPI CSI-2 OUTPUTS
FUNCTION CONTROLS
USB2ANY CONNECTOR
I2C BUS
1
2
3
4
5
GPIO6
POWER SUPPLY7
POC CONFIGURATION8
1
2
2
345
6
7
8
Figure 4-1. Interfacing to the EVM
To demonstrate the functionality, the following components are also required (not included):
1. At least one DS90UB953-Q1EVM or a camera module (Up to four may be used)
2. USB to Mini USB cable OR I2C host controller that support clock stretching (Such As USB2ANY)
3. Power supply capable of supporting 12V, 1A load
4. Optional: MIPI-CSI-2 output analyzer or Host Processor
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5 Quick Start Guide
1. Ensure all jumpers and switches are placed and configured as shown in Figure 5-1
Figure 5-1. DS90UB960-Q1EVM Jumper and Switch Configuration
2. Connect mini USB J37 to USB port for register programming
3. Optional: Connect an external I2C host adapter I2C signals on J9 port for register programming
4. Connect DS90UB953-Q1EVM boards or camera modules to one of the channels on CN1 using Quad
Mini-Fakra to 4x Single Fakra cable assembly
5. Optional: Interface MIPI CSI-2 output signals (J1 or J3) to application processor
6. Provide power to the board. TI recommends using current limited bench supply to provide power to J30
(barrel jack) or J26 (+12VDC)
a. Optional +1.1VDC power supply on J28
b. Optional +1.8VDC power supply on J34
c. Optional +3.3VDC power supply on J35
7. Open Analog LaunchPAD. See Section 8 for details on installing and using Analog LaunchPAD.
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6 Board Connections
6.1 Power Supply
Table 6-1. Power Supply
Reference Signal Description
J30.1 or J26.1 +12V
Main Power
Single +12VDC (nominal) power connector that supplies power to
the entire board.
J28.1 (Optional) +1.1V 1.1V ±5%
Alternative to Main Power
J34.2 (Optional) +1.8V 1.8V ±5%
Alternative to Main Power
J35.2 (Optional) +3.3V 3.3V ±5%
Alternative to Main Power
6.2 Power Over Coax Interface
The DS90UB960-Q1EVM offers four Power-over-Coax interfaces (PoC) to connect cameras through a coaxial
cable with FAKRA connectors. Power is delivered on the same conductor that is used to transmit video and
control channel between the host and the camera. By default, 9V power supply is applied over the coax cable
from a 1A LDO (Max 250 mA per PoC interface). Refer to Table 6-3 for other PoC configurations.
Each PoC interface uses a filter network as shown in Figure 6-1. The PoC network frequency response
corresponds to the bandwidth compatible with DS90UB935-Q1 and DS90UB953-Q1 serializers.
VPoC
L1C1
FB3
FB2
FB1
0.1 PF
C2
>10 PF
R2
RIN+
RIN-
CAC1
CAC2
33 nF ±100 nF
15 nF ±47 nF
49.9 :
4.02 k:
R1
10 PH
Figure 6-1. Power-over-Coax Network Compatible with DS90UB935-Q1 and DS90UB953-Q1
WARNING
Verify that the power voltage is properly set before plugging into CN1. Power supply is not fused.
Over-voltage will cause damage to boards directly connected due to incorrect input power supplies.
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When interfacing to DS90UB913A-Q1 and DS90UB933-Q1 serializers, the PoC filter needs to be adjusted to
match the circuit shown in Figure 6-2. The required updates are summarized in Table 6-2.
VPoC
L1C1
2 k:- 4 k:
FB3
0.1 PF
C2
10 PF
R3
RIN+
RIN-
CAC1
CAC2
100 nF
47 nF
49.9 :
L2
4.7 PH ±22 PH
R1
100 PH
R2
2 k:- 4 k:
FB2
FB1
Figure 6-2. Power-over-Coax Network Compatible with DS90UB913A-Q1, DS90UB933-Q1, DS90UB935-
Q1, and DS90UB953-Q1
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Table 6-2. Required PoC Network Updates for Compatibility to DS90UB913A-
Q1 and DS90UB933-Q1 Serializers
RX Port Description of the Required Change
RX Port0
Install L11 (100 µH).
Update R90 to 4.02 kΩ
Update C70 to 100 nF, C72 to 47 nF
RX Port1
Install L13 (100 µH).
Update R92 to 4.02 kΩ
Update C71 to 100 nF, C73 to 47 nF
RX Port2
Install L23 (100 µH).
Update R96 to 4.02 kΩ
Update C82 to 100 nF, C84 to 47 nF
RX Port3
Install L25 (100 µH).
Update R98 to 4.02 kΩ
Update C83 to 100 nF, C85 to 47 nF
Table 6-3. Power-Over-Coax Power Supply Feed Configuration
Reference Signal Description
J19 VFEED_POC1
Power Over Coax Power Feed Selection 1
Short pins 1-2: +9V power supply from VFEED_LDO1 (Default)
Short pins 2-3: +5V power supply from 5V_SW
J22 VFEED_POC2
Power Over Coax Power Feed Selection 2
Short pins 1-2: +9V power supply from VFEED_LDO2 (Default)
Short pins 2-3: +5V power supply from 5V_SW
J15 VDD_EXT
Power Over Coax Power Feed using +12V Main Power (J21)
Note: J16 and J14 must be left OPEN if using this configuration
Short pins 1-2: +12V power supply to VFEED_POC1
Short pins 2-3: +12V power supply to VFEED_POC2
J11.1 VFEED1
Remote power supply connection to CN1
Short J11.1-2: VFEED_POC1 (Default)
Short J11.1 & J12.1: VFEED_POC2
J11.3 VFEED2
Remote power supply connection to CN2
Short J11.3-4: VFEED_POC1 (Default)
Short J11.3 & J12.2: VFEED_POC2
J11.5 VFEED3
Remote power supply connection to CN3
Short J11.5-6: VFEED_POC1 (Default)
Short J11.5 & J12.3: VFEED_POC2
J11.7 VFEED4
Remote power supply connection to CN4
Short J11.7-8: VFEED_POC1 (Default)
Short J11.7 & J12.4: VFEED_POC2
6.3 MIPI CSI-2 Output Signals
Provided on the DS90UB960-Q1EVM, J1 and J3 are Samtec QSH-type connectors that can be mated with
a matching QTH type connector on the top. This Samtec connector provides a means to route CSI-2 signals
out of the DS90UB960-Q1. The J1 and J3 corresponds to CSI0 Port and CSI1 Port output connection signals
respectively, and includes access to I2C and other miscellaneous GPIO signals. Zero ohm resistor pads are
available if a connection to other signals is required. The mating connector part number is QTH-020-01-H-D-DP-
A.
There are third party solutions like the HDR-128291-XX breakout board from Samtec which can be used. The
HDR- 128291-XX is a breakout board with a mating connector to J1 & J3 and standard SMA male connectors.
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More info on this breakout board can be obtained from Samtec website. Another third party option is the ZX100
by Zebax Technologies. More information on this board can be obtained from Zebax website.
Table 6-4. MIPI CSI-2 (TX Port 0) Output Signals - J1 Pinout
Pin # Signal Name Pin # Signal Name
1 NC 2 EXT_SCL0
(I2C_SCL or I2C_SCL2)
3 NC 4
EXT_SDA0
(I2C_SDA or
I2C_SDA2)
5 CSI0_CLK_P 6 NC
7 CSI0_CLK_N 8 NC
9 CSI0_D0_P 10 EXP_REF_CLK0
(REFCLK)
11 CSI0_D0_N 12 GND
13 CSI0_D1_P 14 RESETn_0
(PDB)
15 CSI0_D1_N 16 GND
17 CSI0_D2_P 18 SPI_MOSI_0
(GPIO0 or GPIO3)
19 CSI0_D2_N 20 SPI_SCLK_0
(GPIO1 or GPIO4)
21 CSI0_D3_P 22 SPI_CSn_0
(GPIO2 or GPIO5)
23 CSI0_D3_N 24 GND
25 NC 26 NC
27 NC 28 NC
29 NC 30 VDD_3V3
31 NC 32 VDD_3V3
33 NC 34 VDD_3V3
35 NC 36 VDD_3V3
37 NC 38 VDD_1V8
39 NC 40 VDD_1V8
Table 6-5. MIPI CSI-2 (TX Port 1) Output Signals - J3 Pinout
Pin # Signal Name Pin # Signal Name
1 NC 2 EXT_SCL1
(I2C_SCL or I2C_SCL2)
3 NC 4
EXT_SDA1
(I2C_SDA or
I2C_SDA2)
5 CSI1_CLK_P 6 NC
7 CSI1_CLK_N 8 NC
9 CSI1_D0_P 10 EXP_REF_CLK1
(REFCLK)
11 CSI1_D0_N 12 GND
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Table 6-5. MIPI CSI-2 (TX Port 1) Output Signals - J3 Pinout (continued)
Pin # Signal Name Pin # Signal Name
13 CSI1_D1_P 14 RESETn_1
(PDB)
15 CSI1_D1_N 16 GND
17 CSI1_D2_P 18 SPI_MOSI_1
(GPIO0 or GPIO3)
19 CSI1_D2_N 20 SPI_SCLK_1
(GPIO1 or GPIO4)
21 CSI1_D3_P 22 SPI_CSn_1
(GPIO2 or GPIO5)
23 CSI1_D3_N 24 GND
25 NC 26 NC
27 NC 28 NC
29 NC 30 VDD_3V3
31 NC 32 VDD_3V3
33 NC 34 VDD_3V3
35 NC 36 VDD_3V3
37 NC 38 VDD_1V8
39 NC 40 VDD_1V8
Table 6-6. MIPI CSI-2 Output Signals - J2 Pinout
Pin # Signal Name Pin # Signal Name
1 NC 2 EXP_SCL0
(I2C_SCL or I2C_SCL2)
3 NC 4
EXP_SDA0
(I2C_SDA or
I2C_SDA2)
5 CSI0_CLK_P 6 NC
7 CSI0_CLK_N 8 NC
9 CSI0_D0_P 10 EXP_REF_CLK0
(REFCLK)
11 CSI0_D0_N 12 GND
13 CSI0_D1_P 14 RESETn_0
(PDB)
15 CSI0_D1_N 16 GND
17 CSI0_D2_P 18 SPI_MOSI_0
(GPIO0 or GPIO3)
19 CSI0_D2_N 20 SPI_SCLK_0
(GPIO1 or GPIO4)
21 CSI0_D3_P 22 SPI_CSn_0
(GPIO2 or GPIO5)
23 CSI0_D3_N 24 GND
25 CSI1_CLK_P 26 NC
27 CSI1_CLK_N 28 NC
29 CSI1_D0_P 30 VDD_3V3
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Table 6-6. MIPI CSI-2 Output Signals - J2 Pinout (continued)
Pin # Signal Name Pin # Signal Name
31 CSI1_D0_N 32 VDD_3V3
33 CSI1_D1_P 34 VDD_3V3
35 CSI1_D1_N 36 VDD_3V3
37 NC 38 VDD_1V8
39 NC 40 VDD_1V8
Note
* Remove R7, R9, R11, R12, R15, R16, R17, R19, R21, R22, R25, R27, R31, R33, R35, R37, R40
and R42 for CSI-2 source connected to J1/J3 (Default) *
** Populate R7, R9, R11, R12, R15, R16, R17, R19, R21, R22, R25, R27, R31, R33, R35, R37, R40
and R42 when source connected through J2 **
6.4 FPD-Link III Signals
Table 6-7. FPD-Link III Signals
Reference Signal Description
CN1.1 RIN0+ Quad Mini-FAKRA connector
CN1.2 RIN1+ Quad Mini-FAKRA connector
CN1.3 RIN2+ Quad Mini-FAKRA connector
CN1.4 RIN3+ Quad Mini-FAKRA connector
6.5 I2C Interface
A standalone external I2C host can connect throughJ9, J10 for programming purposes. Examples of external I2C
host controllers are Texas Instruments USB2ANY and Total Phase Aardvark I2C/SPI host adapter (Total Phase
Part#: TP240141).
Optional access to I2C signals are also available throughCSI-2 connectors J1, J2, or J3. I2C signal levels can be
configured through J30 to be at 1.8V or 3.3V when the I2C interface is accessed through connectors J4, J5.
Table 6-8. IDx I2C Device Address Select - J34
Reference Signal Description
J7 IDX
Selects I2C Device Address
Open: 0x30 (7'b) or 0x60 (8'b)
Short: 0x3D (7'b) or 0x7A (8'b) (Default)
Table 6-9. Primary I2C Interface Header - J4
Reference Signal Description
J9.1 VDD_I2C External I2C bus voltage
J9.2 I2C_SCL I2C Clock Interface for primary I2C bus
J9.3 I2C_SDA I2C Data Interface for primary I2C bus
J9.4 GND Ground
Table 6-10. Secondary I2C Interface Header - J5
Reference Signal Description
J10.1 VDD_I2C External I2C bus voltage
J10.2 I2C_SCL2 I2C Clock Interface for secondary I2C bus
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Table 6-10. Secondary I2C Interface Header - J5 (continued)
Reference Signal Description
J10.3 I2C_SDA2 I2C Data Interface for secondary I2C bus
J10.4 GND Ground
Table 6-11. I2C VDDIO Interface Header - J30
Reference Signal Description
J36 VDD_I2C
Selects I2C IO bus voltage
Short pins 1-2: 3.3V IO (Default)
Short pins 2-3: 1.8V IO
6.6 Control Interface
Table 6-12. VDDIO Interface Header - J1
Reference Signal Description
J4 VDDIO
Selects VDDIO bus voltage
Short pins 1-2: 3.3V IO (Default)
Short pins 2-3: 1.8V IO
Table 6-13. GPIO Interface Header - J8
Reference Signal Description
J8.2 GPIO0 General Purpose Input/Output 0
J8.4 GPIO1 General Purpose Input/Output 1
J8.6 GPIO2 General Purpose Input/Output 2
J8.8 GPIO3 General Purpose Input/Output 3
J8.10 GPIO4 General Purpose Input/Output 4
J8.12 GPIO5 General Purpose Input/Output 5
J8.14 GPIO6 General Purpose Input/Output 6
J8.16 GPIO7 General Purpose Input/Output 7
Table 6-14. CMLOUTP Output Signals
Reference Signal Description
TP1 CMLOUTP Test Pad for Channel Monitor Loop-through Driver
TP2 CMLOUTN Test Pad for Channel Monitor Loop-through Driver
Table 6-15. Mode SW-DIP4 - S1
Reference Mode Description
S1.1 1 CSI Mode (DS90UB953 compatible) (Default)
S1.2 2 RAW12 / LF (DS90UB913A / 933 compatible)
S1.3 3 RAW12 / HF (DS90UB913A / 933 compatible)
S1.4 4 RAW10 (DS90UB913A / 933 compatible)
Table 6-16. Control SW-DIP2 - SW1
Reference Signal Input = L Input = H Description
SW1.1 TESTEN For Normal operation (Default) Test Mode enable Test Mode
SW1.2 PDB Device is powered down Device is enabled (Default) Power-down Mode
Table 6-17. LEDs
Reference LED Name Description
D1 GPIO0 Illuminates if GPIO0 is ON
D2 GPIO1 Illuminates if GPIO1 is ON
D3 GPIO2 Illuminates if GPIO2 is ON
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Table 6-17. LEDs (continued)
Reference LED Name Description
D4 GPIO3 Illuminates if GPIO3 is ON
D5 GPIO4 Illuminates if GPIO48 is ON
D6 GPIO5 Illuminates if GPIO5 is ON
D7 GPIO6 Illuminates if GPIO6 is ON
D8 GPIO7 Illuminates if GPIO7 is ON
D11 VDD_EXT Illuminates if 12V Power is applied to DC-IN J30
D12 VDD5V Illuminates on +5V
D13 VFEED_POC Illuminates if VFEED_POC Power is ON
D14 VDDIO Illuminates on VDDIO Power
7 Enable and Reset
There are two device enable and reset/power-down options for the EVM.
• RC timing option: The C57 external capacitor and R78 pull-up resistor connected to the PDB pin ramp time
after the device is powered on.
• External control option: A push-button (S2) or SW1 position 2 is available for the manual control of the PBD
signal.
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8 ALP Software Setup
8.1 System Requirements
Operating System: Windows 7 64-bit
USB: USB2ANY
USB2ANY Firmware Version: 2.5.2.0
USB: Aardvark I2C/SPI host adapter
p/n TP240141
8.2 Download Contents
Latest TI Analog LaunchPAD can be downloaded from: http://www.ti.com/tool/alp.
Download and extract the zip file to a temporary location that can be deleted later.
The following installation instructions are for a PC running Windows 7 64-bit Operating System.
8.3 Installation of the ALP Software
Execute the ALP Setup Wizard program called “ALPF_setup_v_x_x_x.exe” that was extracted to a temporary
location on the local drive of your PC.
There are 7 steps to the installation once the setup wizard is started:
1. Select the "Next" button.
2. Select “I accept the agreement” and then select the “Next” button.
3. Select the location to install the ALP software and then select the “Next” button.
4. Select the location for the start menu shortcut and then select the “Next” button.
5. There will then be a screen that allows the creation of a desktop icon. After selecting the desired choices
select the “Next” button.
6. Select the “Install” button, and the software will then be installed to the selected location.
7. Uncheck “Launch Analog LaunchPAD” and select the “Finish” button. The ALP software will start if “Launch
Analog LaunchPAD” is checked, but it will not be useful until the USB driver is installed and board is
attached.
Power the DS90UB960-Q1 EVM board with a 12 VDC power supply.
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8.4 Startup - Software Description
Make sure all the software has been installed and the hardware is powered on and connected to the PC.
Execute “Analog LaunchPAD” shortcut from the start menu. The default start menu location is under All
Programs > Texas Instruments > Analog LaunchPAD vx.x.x > Analog LaunchPAD to start MainGUI.exe.
Figure 8-1. Launching ALP
The application must come up in the state shown in Figure 8-2. If it does not, see Section 9, “Troubleshooting
ALP Software”.
Under the Devices tab click on “DS90UB960” or "DS90UB960_ENG" to select the device and open up the
device profile and its associated tabs.
Figure 8-2. Initial ALP Screen
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After selecting the “DS90UB960” or "DS90UB960_ENG", the following screen shown in Figure 8-3 must appear
provided four camera modules with DS90UB953-Q1 are connected to the EVM.
Figure 8-3. Follow-up Screen
8.5 Information Tab
The Information tab is shown below.
Figure 8-4. ALP Information Tab
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8.6 Registers Tab
The Register tab is shown in Figure 8-5.
Figure 8-5. ALP Registers Tab
8.7 Registers Tab - Address 0x00 Selected
Address 0x00 selected as shown in Figure 8-6. Note that the “Value:” box, , will now show the hex
value of that register.
Figure 8-6. ALP Device ID Selected
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8.8 Registers Tab - Address 0x00 Expanded
By double clicking on the Address bar
or a single click on . Address 0x00 expanded reveals contents by bits. Any register address displayed can be
expanded.
Figure 8-7. ALP Device ID Expanded
Any RW Type register, , can be written into by writing the hex value into the “Value:” box, or
putting the pointer into the individual register bit(s) box by a left mouse click to put a check mark (indicating a “1”)
or unchecking to remove the check mark (indicating a “0”). Click the “Apply” button to write to the register, and
“refresh” to see the new value of the selected (highlighted) register.
The box toggles on every mouse click.
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8.9 Scripting Tab
The Scripting tab is shown below.
Figure 8-8. ALP Scripting Tab
The script window provides a full Python scripting environment which can be for running scripts and interacting
with the device in an interactive or automated fashion.
WARNING
Directly interacting with devices either through register modifications or calling device support library
functions can effect the performance and/or functionality of the user interface and may even crash
the ALP Framework application.
8.10 Sample ALP Python Script
8.10.1 Initialization
# 960_RX0_init_CSI0.py
# board.devAddr = 0x7a
# To configure GPIO0 to bring out Lock for Port0,
print "configure GPIO0 to bring out Lock for Port0"
board.WriteReg(0x10,0x81)
time.sleep(0.1)
# To configure GPIO1 to bring out Lock for Port1,
print "configure GPIO1 to bring out Lock for Port1"
board.WriteReg(0x11,0x85)
time.sleep(0.1)
# To configure GPIO2 to bring out Lock for Port2,
print "configure GPIO2 to bring out Lock for Port2"
board.WriteReg(0x12,0x89)
time.sleep(0.1)
# To configure GPIO3 to bring out Lock for Port3,
print "configure GPIO3 to bring out Lock for Port3"
board.WriteReg(0x13,0x8D)
time.sleep(0.1)
print "CSI_PORT_SEL"
board.WriteReg(0x32,0x01) # CSI0 select
time.sleep(0.1)
print "CSI_PLL_CTL"
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