Texas Instruments ADS131B26Q1EVM-PDK User manual

User’s Guide
ADS131B26Q1EVM-PDK Evaluation Module
ABSTRACT
Figure 1-1. ADS131B26Q1EVM-PDK Evaluation Module
This user's guide describes the design and operation of the ADS131B26Q1EVM-PDK. This evaluation
module (EVM) is an evaluation board for the ADS131B26-Q1, a complete analog front-end (AFE) for
automotive electrical vehicle (EV) battery management systems (BMS) that integrates two pairs of simultaneous-
sampling, high-precision, 24-bit analog-to-digital converter (ADC) channels to redundantly measure battery
current and battery pack voltage with high resolution and accuracy. The EVM allows evaluation of all
aspects of the ADS131B26-Q1. This user's guide covers the operation of the ADS131B26Q1EVM-PDK.
Throughout this document, the terms evaluation board, evaluation module, and EVM are synonymous with
the ADS131B26Q1EVM-PDK. The terms PHI controller, PHI, and host are synonymous with the precision host
interface (PHI) controller board that interfaces the EVM to the PC. Complete circuit descriptions, schematic
diagrams, and bill of materials are included in this document.
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Table of Contents
1 EVM Overview......................................................................................................................................................................... 4
1.1 ADS131B26Q1EVM-PDK Features................................................................................................................................... 4
1.2 ADS131B26Q1EVM-PDK Quick-Start Guide.....................................................................................................................5
2 Analog Interface......................................................................................................................................................................5
2.1 Terminal Blocks and Test Points........................................................................................................................................ 6
2.2 ADC1A and ADC1B........................................................................................................................................................... 7
2.3 ADC2A and ADC2B........................................................................................................................................................... 7
2.4 ADC3A and ADC3B........................................................................................................................................................... 8
3 Digital Interface.......................................................................................................................................................................9
3.1 Connection to the PHI Controller....................................................................................................................................... 9
3.2 Digital Header.................................................................................................................................................................. 10
3.3 Clock Options...................................................................................................................................................................10
4 Power Supplies..................................................................................................................................................................... 11
4.1 DC/DC Converter Circuit.................................................................................................................................................. 11
4.2 ADC Power Supplies........................................................................................................................................................12
4.3 Power Supply and Voltage Reference Decoupling.......................................................................................................... 12
5 ADS131B26Q1EVM-PDK Initial Setup.................................................................................................................................13
5.1 Default Jumper Settings...................................................................................................................................................13
5.2 EVM Graphical User Interface (GUI) Software Installation.............................................................................................. 14
6 ADS131B26Q1EVM-PDK Software Reference....................................................................................................................16
6.1 Global Settings for ADC Control...................................................................................................................................... 16
6.2 Register Map Configuration............................................................................................................................................. 17
6.3 Analysis Tools.................................................................................................................................................................. 19
7 ADS131B26Q1EVM-PDK Bill of Materials, PCB Layout, and Schematics.......................................................................24
7.1 Bill of Materials (BOM)..................................................................................................................................................... 24
7.2 PCB Layout...................................................................................................................................................................... 28
7.3 Schematics.......................................................................................................................................................................29
List of Figures
Figure 1-1. ADS131B26Q1EVM-PDK Evaluation Module...........................................................................................................1
Figure 1-1. ADS131B26Q1EVM-PDK PHI Connection and LED Indicators................................................................................5
Figure 2-1. ADC1A Current Input Circuit (Schematic)................................................................................................................. 7
Figure 2-2. ADC2A Sequencer Input Circuits (Schematic)..........................................................................................................7
Figure 2-3. ADC3A Voltage Input Circuit (Schematic)................................................................................................................. 8
Figure 3-1. External ADC Clock Options (Schematic)............................................................................................................... 10
Figure 4-1. DC/DC Converter and Transformer Driver Circuit (Schematic)............................................................................... 11
Figure 4-2. ADC Analog and Digital Supply Options (Schematic)............................................................................................. 12
Figure 5-1. ADS131B26Q1-PDK Jumper Default Settings........................................................................................................13
Figure 5-2. ADS131B26-Q1 Software Installation Prompt.........................................................................................................14
Figure 5-3. Device Driver Installation Wizard Prompts.............................................................................................................. 15
Figure 5-4. LabVIEW Run-Time Engine Installation.................................................................................................................. 15
Figure 6-1. EVM GUI Global Input Parameters......................................................................................................................... 16
Figure 6-2. Register Map Configuration.....................................................................................................................................17
Figure 6-3. Channel Configurations Register Page................................................................................................................... 18
Figure 6-4. Sequencer Configurations Register Page............................................................................................................... 19
Figure 6-5. Time Domain Display Tool ......................................................................................................................................20
Figure 6-6. Spectral Analysis Tool............................................................................................................................................. 21
Figure 6-7. Histogram Analysis Tool.......................................................................................................................................... 22
Figure 6-8. Sequencer Analysis Tool......................................................................................................................................... 23
Figure 7-1. Top Silkscreen......................................................................................................................................................... 28
Figure 7-2. Top Layer.................................................................................................................................................................28
Figure 7-3. Ground Layer.......................................................................................................................................................... 28
Figure 7-4. Power Layer............................................................................................................................................................ 28
Figure 7-5. Bottom Layer........................................................................................................................................................... 28
Figure 7-6. Bottom Silkscreen................................................................................................................................................... 28
Figure 7-7. Analog Inputs, ADC Power, and Interface Connections..........................................................................................29
Figure 7-8. Digital Isolators, DC/DC Power Supply, External Clock, and PHI Controller...........................................................30
List of Tables
Table 1-1. Related Documentation.............................................................................................................................................. 4
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Table 2-1. Analog Input Terminal Blocks (J1 - J5)....................................................................................................................... 6
Table 2-2. Key Voltage Test Points.............................................................................................................................................. 6
Table 3-1. PHI Connector Pin Functions......................................................................................................................................9
Table 3-2. DEBUG Header Pins (J7)......................................................................................................................................... 10
Table 5-1. Default Jumper Settings............................................................................................................................................13
Table 5-2. Nominal Voltages: Default Configuration.................................................................................................................. 14
Table 7-1. ADS131B26Q1EVM-PDK Bill of Materials................................................................................................................24
Trademarks
LabVIEW® is a registered trademark of National Instruments.
All trademarks are the property of their respective owners.
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1 EVM Overview
The evaluation kit includes the ADS131B26Q1EVM-PDK board and the precision host interface (PHI) controller
board. The PHI board enables the accompanying computer software to communicate with the ADC over the
universal serial bus (USB) for data capture and analysis.
The PHI board primarily serves three functions:
• Provides a communication interface between the EVM and the computer through a USB port
• Provides the digital input and output signals necessary to communicate with the ADS131B26Q1EVM-PDK
• Supplies power to all active circuitry on the ADS131B26Q1EVM-PDK board
The following related documents are available for download through the Texas Instruments web site at
www.ti.com.
Table 1-1. Related Documentation
Device Literature Number
ADS131B26-Q1 SBASA22
SN6505B-Q1 SLLSF95
ISO7762-Q1 SLLSEU7
ISO7761-Q1 SLLSEU7
TMP61-Q1 SNIS210
LMT84-Q1 SNIS178
1.1 ADS131B26Q1EVM-PDK Features
The ADS131B26-Q1 evaluation module kit includes the following features:
• Contains all support circuitry needed for the ADS131B26-Q1
• USB powered: No external power supply is required
• Analog-to-digital converter (ADC) voltage supply options:
– DC/DC converter output provides APWR and DPWR supplies, which the ADC uses to generate AVDD
and DVDD with the respective integrated low-dropout regulators (LDOs)
– APWR and DPWR can be provided externally while still using the respective integrated LDOs when the
external supply is between 4 V and 16 V
– APWR and DPWR can be shorted to the respective LDO outputs if the external supply is between 3 V and
3.6 V
• Clock options: Internal ADC clock, onboard 8.192-MHz crystal oscillator, or external clock with a subminiature
version A (SMA) connector
• Input signals provided by terminal blocks connect to various application circuits for voltage, current, and
temperature measurements
• Digital inputs and outputs are connected to a dual-row DEBUG header for connections to a logic analyzer or
external controller
• EVM GUI includes a complete register map page for ease of device configuration and a built-in analysis tool
suite complete with scope, FFT, and histogram displays
• Two 16-bit multiplexed ADC channels allow for measuring multiple single-ended and pseudo-differential
inputs in a specified sequence in conjunction with the four 24-bit simultaneous-sampling ADC channels
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1.2 ADS131B26Q1EVM-PDK Quick-Start Guide
The following instructions are a step-by-step guide to connecting the ADS131B26Q1EVM-PDK to the computer
and evaluating the performance of the ADS131B26-Q1:
1. Review the default jumper settings in Section 5.1 and GUI software installation in Section 5.2.
2. Connect the ADS131B26Q1EVM-PDK to the PHI controller. Install the two screws as indicated in Figure 1-1.
3. Connect the PHI controller to your PC using the provided USB micro cable. Three LEDs illuminate on the
PHI controller to indicate connectivity to the PC.
a. LED D5 lights up solid, indicating that the PHI is powered up.
b. LEDs D1 and D2 start blinking at different rates to indicate that the PHI is booted up and communicating
with the PC. Figure 1-1 shows the resulting LED indicators.
D1 and D2
Remove post
Install D5
Figure 1-1. ADS131B26Q1EVM-PDK PHI Connection and LED Indicators
4. Launch the ADS131B26Q1EVM-PDK GUI software and power is supplied to the EVM. The default
installation path is C:\Program Files (x86)\Texas Instruments\ADS131B26-Q1 EVM.
5. When the GUI finishes loading and is connected to the EVM hardware, the screen appears as illustrated in
Figure 6-1. The GUI consists of multiple Pages, which include:
• Register Map Config
• Time Domain Display
• Spectral Analysis
• Histogram Analysis
• Channel Configurations
• Sequencer Configurations
Below the Pages section are the basic SPI op-code commands, the Data Capture Configuration controls,
and the current Clocks and Data Rate information. Section 6.1 details the EVM GUI pages and data capture
controls.
2 Analog Interface
The ADS131B26Q1EVM-PDK is designed for easy and complete evaluation of the ADS131B26-Q1 using
external voltage, current, and temperature sensor inputs. This section details the analog front-end circuitry,
including jumper configurations, terminal block connectors, and test points for different input test signals.
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2.1 Terminal Blocks and Test Points
Analog inputs to the EVM can be connected to either terminal block associated with each ADC channel. The
screw terminal blocks (J1 through J5) can interface directly with the leads of an external source. Table 2-1 lists
the supported input options. Table 2-2 lists key test points.
An input must not be applied such that the voltage on the input pins of the ADS131B26-Q1 exceeds the absolute
maximum ratings. For more details, see the ADS131B26-Q1 data sheet.
Table 2-1. Analog Input Terminal Blocks (J1 - J5)
Terminal
Block Pin Function Input Range ADS131B26-Q1 Input Pins
J1
1 Unipolar voltage input 0 V to 10 V (Gain = 1) V1A
2 Unipolar voltage input 0 V to 1.25 V (Gain = 1) V0A
3 Differential voltage, positive input or
general-purpose digital input/output
–10 V to 10 V (Gain = 4) VPA/GPIO0A
4 Differential voltage, negative input or
general-purpose digital input/output
Shorted to AGND (default) VNA/GPIO1A
5 Differential current, positive input 0 mA to 12.5 mA (Gain = 1) CPA
6 Differential current, negative input Shorted to AGND (default) CNA
J2 1 AGND －AGND, AGNDA, and AGNDB
2 AGND －AGND, AGNDA, and AGNDB
J3
1Differential voltage, negative input or
general-purpose digital input/output Shorted to AGND (default) VNB/GPIO1B
2 Differential voltage, positive input or
general-purpose digital input/output
–10 V to 10 V (Gain = 4) VPB/GPIO0B
3 Differential current, negative input Shorted to AGND (default) CNB
4 Differential current, positive input 0 mA to 12.5 mA (Gain = 1) CPB
5 Unipolar voltage input 0 V to 1.25 V (Gain = 1) V0B
6 Unipolar voltage input 0 V to 10 V (Gain = 1) V1B
J4
1 Unipolar voltage input 0 V to 10 V (Gain = 1) V2B
2 Unipolar voltage input –10 V to 10 V (Gain = 4) V3B
3 Unipolar voltage input –10 V to 10 V (Gain = 4) V4B
4 Unipolar voltage input –8.5 V to 10 V (Gain = 2) V5B
5 Unipolar voltage input –8.5 V to 10 V (Gain = 2) V6B
6 Unipolar voltage input V7B
J5
1 Unipolar voltage input V7A
2 Unipolar voltage input –8.5 V to 10 V (Gain = 2) V6A
3 Unipolar voltage input –8.5 V to 10 V (Gain = 2) V5A
4 Unipolar voltage input –10 V to 10 V (Gain = 4) V4A
5 Unipolar voltage input –10 V to 10 V (Gain = 4) V3A
6 Unipolar voltage input 0 V to 10 V (Gain = 1) V2A
Table 2-2. Key Voltage Test Points
Test Point Function Input Range ADS131B26-Q1 Input Pins
TP1 Probe VNA or GPIO0A –10 V to 10 V (Gain = 4) VPA/GPIO0A
TP2 Probe VPB or GPIO0B –10 V to 10 V (Gain = 4) VPB/GPIO0B
TP3 Ground clip for scope / multimeter －AGND, AGNDA, and AGNDB
TP4 Ground clip for scope / multimeter －AGND, AGNDA, and AGNDB
TP5 Probe VNA or GPIO1A Shorted to AGND (default) VNA/GPIO1A
TP6 Probe VNB or GPIO1B Shorted to AGND (default) VNB/GPIO1B
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2.2 ADC1A and ADC1B
The ADS131B26-Q1 features two high-precision, 24-bit ADC channels that are intended for battery current-shunt
measurements (ADC1A and ADC1B). For demonstration purposes, the EVM includes a 100-Ω, 1206-footprint
resistor on ADC1A and ADC1B to function as a current-shunt resistor (R8 and R9, respectively). A more realistic
application uses a much smaller shunt resistor value (that is, 50 μΩ) that is not practical to include on the EVM
hardware. A small current up to 12.5 mA at gain = 1 can be applied to the positive channel input (CPA and
CPB), and the low-side of the shunt resistor is connected to AGND by default. Figure 2-1 shows the current input
schematic for ADC1A.
Figure 2-1. ADC1A Current Input Circuit (Schematic)
2.3 ADC2A and ADC2B
The ADS131B26-Q1 features two multiplexed, 16-bit ADC channels that are intended to measure shunt
temperature using external temperature sensors and other voltages in the system. For demonstration purposes,
the EVM includes multiple resistor divider ratios to support unipolar and bipolar single-ended and pseudo-
differential input measurements.
The V7A and V7B signals can serve as the common-mode voltage when measuring V5A and V6A or V5B and
V6B, respectively. Alternatively, an external common-mode voltage can be generated from the analog supply
voltage (ADC_AVDD) by installing the optional external VCM circuit shown in Figure 2-2. Figure 2-2 shows the
input connections and resistor divider circuits for ADC2A.
Figure 2-2. ADC2A Sequencer Input Circuits (Schematic)
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2.4 ADC3A and ADC3B
The ADS131B26-Q1 features two high-precision, 24-bit ADC channels that are intended for battery stack voltage
measurements (ADC3A and ADC3B). For demonstration purposes, the EVM includes a resistor divider circuit
with an approximate ratio of 1 / 32.5. At gain = 4, which allows an input voltage from –10 V to 10 V on the
positive voltage measurement inputs (VPA and VPB). The negative voltage measurement inputs (VNA and VNB)
are connected to AGND by default. Figure 2-3 shows the voltage input schematic for ADC3A.
Figure 2-3. ADC3A Voltage Input Circuit (Schematic)
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3 Digital Interface
As noted in Section 1, the EVM interfaces with the PHI controller and communicates with the PC over USB.
There are two devices on the EVM with which the PHI controller communicates: the ADS131B26-Q1 (by SPI)
and the EEPROM (by I2C). The EEPROM comes preprogrammed with the information required to configure and
initialize the ADS131B26Q1EVM-PDK GUI software. When the hardware is initialized, the EEPROM is no longer
used.
3.1 Connection to the PHI Controller
The ADS131B26Q1EVM-PDK communicates with the PHI controller through a shrouded, 60-pin connector (J9).
There are two round standoffs next to J9 with Phillips-head screws. To connect the PHI controller to the EVM,
remove the screws, attach the PHI controller to the EVM, and replace the screws into the standoffs. The screws
secure the EVM to the PHI and makes sure the connection between the two boards is complete.
Table 3-1 lists the different PHI connection and their functions.
Table 3-1. PHI Connector Pin Functions
PHI Connector Pin Name PHI Connector Pin Function
EVM_REG_5.5V J9[1] Boosted 5.5-V supply from the USB (not used)
EVM_RAW_5V J9[2] Raw USB 5-V supply; optional supply for the DC/DC input
ISO_GND J9[3] Ground connection for the isolated host controller side of the EVM
ISO_GPIO0/MHD J9[6] General-purpose digital input/output 0 or missing host detect output
ISO_GPIO1 J9[8] General-purpose digital input/output 1
ISO_GPIO2/FAULT J9[10] General-purpose digital input/output 2 or fault output
ISO_GPIO3/OCCA J9[12] General-purpose digital input/output 3 or overcurrent comparator A
output
ISO_GPIO4/OCCB J9[14] General-purpose digital input/output 4 or overcurrent comparator B
output
ISO_SDI J9[18] SPI: Serial data input to the ADC
ISO_CSn J9[22] SPI: Chip-select input from the PHI controller; active low
ISO_SCLK J9[24] SPI: Serial data clock input
ISO_CAPCLK J9[26, 28] PHI clock signal to synchronize SPI transactions with the
propagation delay from the EVM
ISO_DRDYn J9[30] SPI: Data-ready output from the ADC; active low
ISO_SDO J9[38] SPI: Serial data output from the ADC
ISO_RESETn J9[46] Reset input; active low
WP J9[49] Write protection for the EEPROM
ISO_3V3 J9[50] Power-supply source for the isolated host controller side of the EVM
and default supply input to the DC/DC circuit
EVM_ID_SDA J9[56] I2C serial data for the EEPROM
EVM_ID_SCL J9[58] I2C serial clock for the EEPROM
ID_PWR J9[59] Power-supply source for the EEPROM
ISO_GND J9[60] Ground connection for the isolated host controller side of the EVM
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3.2 Digital Header
In addition to the PHI connector, header J7 on the EVM is connected to the digital inputs and outputs between
the ADS131B26-Q1 and the PHI connector. Each row is shorted across both pins to allow access to an external
logic analyzer or oscilloscope and an external controller simultaneously. Table 3-2 lists the digital header pins.
Table 3-2. DEBUG Header Pins (J7)
Signal Name Digital Header Pins
GPIO0/MHD J7[1-2]
CSn J7[3-4]
SDI J7[5-6]
SDO J7[7-8]
SCLK J7[9-10]
DRDYn J7[11-12]
GPIO1 J7[13-14]
GPIO2/FAULT J7[15-16]
GPIO3/OCCA J7[17-18]
RESETn J7[19-20]
GPIO4/OCCB J7[21-22]
DGND J7[23-24]
3.3 Clock Options
The ADS131B26-Q1 uses an internal oscillator by default after power-up. The internal oscillator frequency (fCLK)
has a nominal frequency of 8.192 MHz and serves as the primary timing reference for both analog and digital
circuitry inside the device. The ADC modulator frequency (fMOD) is equal to one-half the clock frequency (fMOD =
fCLK / 2) and controls the timing of the input sample-and-hold switches inside each delta-sigma ADC modulator.
In addition to the internal oscillator, the EVM allows the user to provide an external clock frequency to the ADC
CLK input pin. The external clock signal can either come from:
1. The onboard crystal oscillator (Y1), which has a nominal frequency of 8.192 MHz
2. An external clock source connected to the SMA connector (J10)
One advantage to using either external ADC clock option on the EVM is the ability to synchronize the DC/DC
converter switching frequency with a null in the ADC digital sinc3 filter. For more information, see Section 4.1.
Figure 3-1 shows a schematic of the external clock options.
Figure 3-1. External ADC Clock Options (Schematic)
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4 Power Supplies
This section details the EVM power supplies, ADC analog and digital supply options, and the PCB layout and
decoupling guidelines.
4.1 DC/DC Converter Circuit
As mentioned previously in Section 1, power to the EVM can be supplied entirely by the PHI controller through
connector J9. For information about the PHI pins and power connections, see Table 3-1.
A 3.3-V LDO output on the PHI (ISO_3V3) is used to power the controller side of the isolation barrier, including
the digital isolators, onboard 8.192-MHz oscillator, and D flip-flop clock divider circuit. ISO_3V3 is also the
default option to power the transformer driver (SN6505B-Q1, U6) and generate the supplies used on the ADC
side of the isolation barrier. U6 can also be powered by the raw USB supply (EVM_RAW_5V) by uninstalling
R96 and installing R97.
By default, the SN6505B-Q1 uses an internal 420-kHz clock to set the transformer switching frequency. This
clock operates asynchronously to the ADS131B26-Q1 internal clock (CLK = 8.192 MHz). However, the EVM
also supports an external ADC clock, which can be provided either by enabling the onboard oscillator (Y1) or by
connecting a clock from an external source to the onboard SMA connector (J10). When an external clock is used
for the ADC, this signal is divided by a factor of 16 using the dual D-type flip-flops (U7 and U8) and shared with
the SN6505B-Q1 CLK input. The SN6505B-Q1 internally divides this clock input by another factor of 2, resulting
in a transformer switching frequency that is synchronous with the ADC clock. Any remaining switching noise at
the transformer output detected by the ADS131B26-Q1 aligns with a null in the ADC sinc3 digital filter response
and be significantly attenuated. Figure 4-1 shows the DC/DC converter and transformer driver circuits.
Figure 4-1. DC/DC Converter and Transformer Driver Circuit (Schematic)
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4.2 ADC Power Supplies
The transformer output is connected to two rectification diodes (D1 and D2) to provide the main high-side supply
voltage (VADC_HV). JP2 and JP3 connect VADC_HV to the ADC APWR and DPWR supply pins, respectively.
The ADS131B26-Q1 uses two internal LDOs to generate the primary analog and digital supplies (AVDD and
IOVDD). When JP2 and JP3 are installed in the [2-3] position, VADC_HV is nominally approximately 5.1 V. To
evaluate the ADS131B26-Q1 with an external APWR and DPWR supply, uninstall the jumpers on JP2 and JP3
and connect the external supply to the corresponding terminal block inputs (J6 and J8). Alternatively, the ADC
internal LDOs can be completely bypassed by moving both JP2 and JP3 jumpers to the [1-2] position. In this
configuration, APWR must be between 3 V and 3.6 V, and DPWR must be between 3 V and 5.5 V. Figure 4-2
shows the analog and digital ADC supply options.
Figure 4-2. ADC Analog and Digital Supply Options (Schematic)
4.3 Power Supply and Voltage Reference Decoupling
The power supply and ADC voltage reference pins for the ADS131B26-Q1 are bypassed with ceramic capacitors
placed close to the supply pins. Additionally, the EVM layout uses thick traces or large copper fill areas, where
possible, between bypass capacitors and loads to minimize inductance along the load current path.
The EVM schematic lists the analog and digital grounds (AGND and DGND) as separate net names for the
purpose of circuit illustration. However, these two nets are connected on the EVM by a net-tie on the bottom
signal layer. Proper component placement and solid ground pours are important to make sure that the lowest
noise and highest accuracy is used in any precision ADC application. See Section 7.2 for more suggested layout
practices.
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5 ADS131B26Q1EVM-PDK Initial Setup
This section explains the initial hardware and software setup procedure that must be completed in order to
properly operate the ADS131B26Q1EVM-PDK.
5.1 Default Jumper Settings
After unpacking, the EVM is configured with the default jumper settings. Figure 5-1 shows the locations for the
default jumpers and Table 5-1 shows the functions of the default shunts.
Figure 5-1. ADS131B26Q1-PDK Jumper Default Settings
Table 5-1. Default Jumper Settings
Designator Position Function
JP1 [1-2] RCAPA is selected as bias voltage for the TMP61
JP2 [2-3] Selects the transformer output as the APWR supply
JP3 [2-3] Selects the transformer output as the DPWR supply
JP4 Not installed The transformer driver is enabled
JP5 Installed The onboard crystal oscillator is disabled
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Table 5-2 lists the nominal voltages that result from the default configuration.
Table 5-2. Nominal Voltages: Default Configuration
Supply Name Voltage
ISO_VCC 3.3 V
ISO_3V3 3.3 V
VADC_HV 5.1 V
APWR 5.1 V
DPWR 5.1 V
AVDD 3.3 V
DVDD 3.3 V
RCAPA 1.25 V
RCAPB 1.25 V
Note
Voltages are measured with respect to the local ground on the same side of the isolation barrier.
5.2 EVM Graphical User Interface (GUI) Software Installation
Download the latest version of the EVM GUI installer from the Tools and Software folder of the
ADS131B26Q1EVM-PDK and run the GUI installer to install the EVM GUI software on your computer.
CAUTION
Manually disable any antivirus software running on the computer before downloading the EVM GUI
installer onto the local hard disk. Depending on the antivirus settings, an error message may appear
the executable file may be deleted.
Accept the license agreements and follow the on-screen instructions shown in Figure 5-2 to complete the
installation.
Figure 5-2. ADS131B26-Q1 Software Installation Prompt
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As part of the ADS131B26-Q1 EVM GUI installation, a prompt with a device driver installation (as shown in
Figure 5-3) appears on the screen. Click Next to proceed.
Figure 5-3. Device Driver Installation Wizard Prompts
Note
A notice may appear on the screen stating that Windows cannot verify the publisher of this driver
software. Select Install this driver software anyway.
The ADS131B26Q1EVM-PDK requires the LabVIEW® run-time engine and may prompt for the installation of this
software, as shown in Figure 5-4, if not already installed.
Figure 5-4. LabVIEW Run-Time Engine Installation
Verify that C:\Program Files (x86)\Texas Instruments\ADS131B26Q1EVM-PDK is available after these
installations.
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6 ADS131B26Q1EVM-PDK Software Reference
6.1 Global Settings for ADC Control
Figure 6-1 displays the default view of the ADS131B26-Q1 EVM GUI after start-up and successful connection to
the EVM hardware. The EVM connection status can be verified by observing the green light indicator next to HW
Connected at the bottom of the screen.
The Pages section at the top-left corner of the window lists the multiple register map controls and data analysis
tools supported in this GUI. Section 6.2.1 through Section 6.2.3 detail the pages that configure the ADS131B26-
Q1 register settings. Section 6.3.1 through Section 6.3.4 detail the pages that display and analyze the raw
conversion data from the high-resolution, 24-bit ADC channels and the 16-bit sequencer ADC channels.
Below the Pages section is an abbreviated list of device commands, which execute the RESET, LOCK, and
UNLOCK SPI op-codes. The RESET command restores the device register configuration to the power-on default
settings. The LOCK command locks the interface to prevent unwanted commands from changing the state of the
device. The UNLOCK command unlocks the interface to allow device configuration changes.
In the Data Capture Configuration section are basic settings and controls to initiate a data capture from the
main ADC channels. OSR13A and OSR13B allow data rates to be configured for ADC1A, ADC1B, ADC3A, and
ADC3B. DRDYn Driving Source selects which ADC channel generates the data-ready interrupt used for data
collection. The Samples drop-down menu allows the user to choose from a prepopulated list of sample sizes or
to enter a custom sample quantity. The number of samples are collected contiguously in a single data set when
the Capture button is clicked from any of the analysis tool pages.
The CLK Frequency (Hz) and Data Rate (SPS) fields display the current clock frequency and ADC data rate
based on the current OSR settings. If a target SCLK frequency (Hz) is specified, the GUI tries to match this
frequency as closely as possible by changing the PHI PLL settings.
The GUI is switched between hardware mode and simulation mode by checking and unchecking the Connect to
Hardware box in the top-right area of the screen at any time.
Pages
Device
Commands
Data Capture
Con gura on
Clocks and
Data Rate
Connec on
Status
Figure 6-1. EVM GUI Global Input Parameters
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6.2 Register Map Configuration
This section describes how to use the Register Map Configuration tools in the ADS131B26-Q1 EVM GUI. The
GUI provides control over the device register settings via three pages:
1. Register Map Config: This page is the main register map configuration space in the GUI, which provides
access to all device registers.
2. Channel Configurations: This page displays all register settings from multiple addresses that configure
ADC1A, ADC1B, ADC3A, and ADC3B. The same register settings can also be configured in the main
Register Map Config page.
3. Sequencer Configurations: This page displays all register settings from multiple addresses that configure
ADC2A and ADC2B. The same register settings can also be configured in the main Register Map Config
page.
6.2.1 Register Map Basics
The register map configuration tool (Figure 6-2) allows the user to view and modify the registers of the
ADS131B26-Q1. This tool can be selected by clicking on Register Map Config under the Pages section of
the left window pane. On power-up, the values on this page correspond to the ADC default register settings
described in the ADS131B26-Q1 data sheet.
The Register Map Configuration tool has three distinct views that summarize the current register map
configuration. At the top of the window is a tabular view where registers are listed in order of ascending
hexadecimal address to display the Register Name, Address, Default value, Mode (R = Read-only, R/W =
Read/Write), and register Size. To the right, the current register value is also displayed in both hexadecimal and
binary formats. The register value can be modified either by entering the desired hexadecimal value in the Value
column, or by clicking on the individual bits (read-only bits are listed in gray and cannot be edited).
Below the table is the Field View and Register Description. The Field View on the bottom-left lists the designated
bit fields that are grouped together to configure a particular setting. Depending on the bit field, the current setting
can be modified either by selecting the corresponding drop-down menu or entering the desired hexadecimal
value. The Register Description view on the bottom-right describes the function and settings of the bit fields in
the selected register, as described in the ADS131B26-Q1 data sheet.
Figure 6-2. Register Map Configuration
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6.2.2 ADC1A, ADC3A and ADC1B, ADC3B Configuration
Figure 6-3 displays the Channel Configurations register map page. These register controls allow the user to
configure the register settings for ADC1A, ADC1B, ADC3A, and ADC3B in a more user-friendly interface.
The page is partitioned into ADC1A and ADC3A settings on the left and ADC1B and ADC3B settings on the
right. At the top of each section are Global Settings for ADC1A and ADC3A and Global Settings for ADC1B
and ADC3B, which contain the register settings from addresses 82h and C2h, respectively.
Below the global channel settings are individual ADC controls to figure the following settings:
• ADC enable
• Channel gain
• Channel Mux
• Current Source or Sink Mux
• Current Source or Sink Value
• Offset Calibration
• Gain Calibration
Figure 6-3. Channel Configurations Register Page
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6.2.3 ADC2A and ADC2B Configuration
Figure 6-4 displays the Sequencer Configurations register map page. These register controls allow the register
settings to be configured for ADC2A and ADC2B through a more user-friendly interface.
The page is partitioned into ADC2A settings on the left and ADC2B settings on the right. At the top of each
section are Global Settings for ADC2A and Global Settings for ADC2B, which contain the register settings from
addresses 8Bh and CBh, respectively.
Below the global channel settings are ADC2A Steps Configurations and ADC2B Steps Configurations to
configure each of the individual sequencer steps. Steps 0 through 7 are displayed on the page by default,
and steps 8 through 15 can be displayed by selecting the corresponding tab on the bottom of each section. Each
step allows the following settings to be configured:
• Sequence step enable
• Gain
• Negative input
• Positive input
Figure 6-4. Sequencer Configurations Register Page
6.3 Analysis Tools
This section describes the analysis tools included with the ADS131B26Q1EVM-PDK GUI. These tools include
Time Domain Display, Spectral Analysis, Histogram Analysis, and Sequencer Analysis. Section 6.3.1 through
Section 6.3.3 describe the data collection and analysis features of the ADS131B26-Q1 EVM GUI.
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6.3.1 Time Domain Display
The Time Domain Display tool allows visualization of the ADC conversion data for ADC1A, ADC1B, ADC3A, and
ADC3B. This tool is useful for both studying the circuit behavior and debugging any gross problems with the
ADC or input source.
The Data Capture Configuration panel on the left side of the window allows the user to independently specify the
oversampling ratio (OSR) used by ADC1A, ADC3A and ADC1B, ADC3B by configuring OSR13A and OSR13B,
respectively. In addition, ADC1A or ADC1B can be selected as the driving channel source to generate the
DRDYn interrupt. If the data rates differ, and the faster channel is selected as the DRDYn driving source, the
GUI collects data until the faster channel reaches the specified number of samples. In this case, the slower
channel ends up with fewer samples than specified. If the slower channel is selected as the DRDYn driving
source, the GUI collects the specified number of samples for all channels, but some conversion data are missed
from the faster channels, reducing the effective data rate.
Initiate a data capture by specifying the number of samples and clicking the Capture button at the bottom of the
Data Capture Configuration panel. The raw ADC conversion data is then displayed on the graph with a statistical
summary of each channel in the Measurements table below the plot. The Units radio buttons configure the plot
y-axis and the summary table results as either Codes or Voltage (V). When Voltage (V) is selected, the values
are input-referred based on the channel gain setting. Figure 6-5 shows an example of the Time Domain Display
window and relevant controls. Switching pages to any of the other Analysis tools described in the subsequent
sections exports the same data for viewing without having to recollect the data.
Figure 6-5. Time Domain Display Tool
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