Texas Instruments ADS1271EVM-PDK User manual

User's Guide
SBAU107C–November 2004–Revised November 2014
ADS1271EVM and ADS1271EVM-PDK User's Guide
ADS1271EVM-PDK
This user's guide describes the characteristics, operation, and use of the ADS1271EVM, both by itself and
as part of the ADS1271EVM-PDK. This EVM is a 24-bit analog-to-digital converter evaluation module.
This document includes an EVM Quick Start, hardware and software details, bill of materials, and
schematic.
The following related documents are available through the Texas Instruments web site at www.ti.com.
Table 1. EVM-Compatible Device Data Sheets
Literature
Device Number
ADS1271 SBAS306
OPA350 SBOS099B
OPA1632 SBOS286
REF1004 SBVS002
REF3125 SBVS046A
SN74AVC1T45 SCES530C
SN74AVC2T45 SCES531D
SN74LVC1G125 SCES223L
SN74LVC2G66 SCES325G
SN74LVC2G157 SCES207I
TPS71550 SLVS338H
1
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1 EVM Overview
1.1 Features
ADS1271EVM Features:
• Contains all support circuitry needed for the ADS1271
• Two ADS1271 converters on board illustrate use of daisy-chain mode
• Onboard reference and oscillator circuits
• Compatible with the TI Modular EVM System
ADS1271EVM-PDK includes the ADS1271EVM board with the DSP-based MMB0 motherboard, that can
be used with provided software to quickly evaluate the device.
This manual covers the operation of the ADS1271EVM-PDK. Throughout this document, the abbreviation
EVM and the term evaluation module are synonymous with the ADS1271EVM.
Microsoft, Windows are registered trademarks of Microsoft Corporation.
SPI is a trademark of Motorola, Inc.
I2C is a trademark of NXP Semiconductors.
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2 Quick Start
This section provides a Quick Start guide to quickly begin evaluating the ADS1271EVM.
2.1 Default Jumper/Switch Configuration
Figure 1 shows the jumpers found on the EVM and locations of left,middle and right for switch settings
in the following discussion.
Figure 1. ADS1271EVM Default Configuration
Table 2 lists the jumpers and switches and the factory default conditions
Table 2. Default Jumper/Switch Configuration
Switch Default Position Switch Description
S1 Up Analog input from aux header (J4) connected to buffer
S2 Up Analog input from aux header (J5) connected to buffer
S3 Left 2.5V reference connection to CH2 reference
S4 Left Buffer connected to CH2 input
S5 Left 2.5V reference connection to CH1 reference
S6 Left Buffer connected to CH1 input
S7 Left Hardware control of Format is floating
J6 AV1 Installed AVDD connection for ADC1
DV1 Installed DVDD connection for ADC1
AV2 Installed AVDD connection for ADC2
DV2 Installed DVDD connection for ADC2
+1.8V Uninstalled Do not connect 1.8V to DVDD (misc ICs and switches)
+3.3V Installed Connect 3.3V to DVDD (misc ICs and switches)
AGND Uninstalled Do not connect AGND to EVM ground
DGND Installed Connect DGND to EVM ground
J7 Installed 1-2 (FMT) SPI Format controlled by software or hardware (S7)
Installed 3-4 (MODE) ADS1271 MODE pin controlled via software
3
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2.2 ADS1271EVM-PDK Operation
Follow these steps to evaluate the ADS1271 with the ADS1271EVM-PDK:
1. Verify that the jumpers on the ADS1271EVM are as shown in Figure 1 (note that these settings are the
factory-configured settings for the EVM).
2. Verify that the MMB0 jumpers are in the default position.
• MMB0 J13A →Open
• MMB0 J13B →Short
3. Plug the ADS1271EVM onto the MMB0 (if not already connected). Connectors J1B, J2B, and J3B
(female connectors on the bottom side) on the EVM align with male connectors J7, J4, and J5
respectively on the MMB0.
CAUTION
Do not misalign the pins when plugging the ADS1271EVM into the MMB0.
Check the pin alignment of the connectors carefully before applying power to
the PDK.
4. Complete the following steps to install the evaluation software onto your PC.
NOTE: This software is designed to run on Microsoft®Windows®XP. Other operating systems
are not supported.
(a) Download the software from the ADS1271EVM-PDK product folder. Unzip the file and locate the
Setup program on the disk and execute it. The Setup program installs the ADS1271 evaluation
software on your PC. Follow the instructions and prompts given.
(b) After the main program is installed, a dialog box appears with instructions for installing NI-VISA 3.1
Runtime.
(i) Click OK to proceed.
(ii) Click Unzip and the archive extracts itself and automatically runs the NI-VISA 3.1 Runtime
installer.
(c) Follow the instructions in the NI-VISA 3.1 Runtime Installer. When prompted for which features to
install, do the following:
(i) Click on the disk icon next to NI-VISA 3.1
(ii) Select, Do not install this feature.
(iii) Click on the disk icon next to USB.
(iv) Select the option which installs this feature.
(v) Click Next.
(vi) Accept the license agreement, and continue the installation.
(vii) When the installation completes, click Finish on the ADS1271EVM installer window. You may
be prompted to restart your computer.
5. When installation is complete, attach a USB cable from your PC to the MMB0.
6. Connect the included AC adapter to the MMB0.
7. If you intend to utilize the analog signal buffers on the EVM, connect ±15V and ground via J14 terminal
connections +VA, -VA, and GND on the MMB0. Otherwise, skip this step.
8. Start the software on your PC. The software should automatically find the ADS1271EVM, and a screen
similar to the one in Figure 2 should appear.
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Figure 2. Default Software Screen
3 Quick Reference
Table 3 provides a quick summary of the connections required for operation of the EVM as a stand-alone
board.
Table 3. Critical Connections
Pin
Function Header/Pin Description
Name
SCLK J2.5 CLKR SPI Serial Clock
DIN J2.13 (Top) DR SPI Data Input to ADC (MOSI)
SPI DOUT J2.13 (Bottom) DR SPI Data Output from ADC (MISO)
J2.9 Top FSOUT SPI new conversion indication (see
DRDY/FSYNC Section 5.6.2)
J2.9 Bottom FSR
1.8V J3.7 +1.8VD 1.8V supply for ADC DVDD (option)
3.3V J3.9 +3.3VD 3.3V supply for ADC DVDD (option)
5.0V J3.3 +5VA 5.0V supply for ADC AVDD
Positive supply for buffers (+15V)
AVDD (EVM supply) J3.1 +VA
Power (only required when using analog buffers)
Negative supply for buffers (-15V)
AVSS (EVM supply) J3.2 -VA (only required when using analog buffers)
DGND J3.5 DGND Digital ground from MMB0
AGND J3.6 AGND Analog ground from MMB0
Analog Inputs Analog inputs and external reference J4/5 Various Analog inputs and external reference to
ADC
5
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4 Software
Once the ADS1271EVM-PDK software (described in Step 4) is installed, evaluation and development with
the ADS1271 can begin.
4.1 Basic Usage
Once the evaluation software is started, it checks to see whether an MMB0 is connected. If hardware is
connected and recognized, the program downloads the firmware to it, and continues to operate. If no
hardware is detected, a dialog box is displayed telling you that it cannot find an MMB0. If you see this,
make sure the MMB0 is connected and powered on and click Retry. If the software cannot find the
hardware, you can click Cancel to quit the application.
After the program loads the MMB0 successfully, you will see a screen similar to that shown in Figure 2.
The top portion of the display shows an FFT of the ADC data and certain AC analysis numbers.
Immediately below the FFT graph (middle portion of the display) are a number of controls and meters. At
the bottom of the display is a set of tabs, which show either a histogram, a picture of the incoming
waveform, or the data recording controls.
To exit the program, select File →Exit from the menu bar.
When the program starts, it will be in idle mode. You can put it in either Acquire Mode or Record Mode.
4.1.1 Acquire Mode
In Acquire mode, the ADS1271EVM software collects data from the board in 2,048-sample blocks and
performs the appropriate analysis. Both AC and DC analyses are performed.
To put the program into Acquire mode, click the Acquire button.
In Acquire mode, you can only view the data from one channel at a time. To choose channels, use the
Channel box.
4.1.1.1 AC Analysis
The basic AC analysis consists of the FFT graph and THD calculations. The THD analyzer uses an
automatic tone-detection algorithm, which searches for the highest harmonic to use for the THD analysis.
The detected frequency is shown in the indicator marked Tone Freq.
NOTE: For the THD analysis to work, the input must be a sine wave below half the Nyquist
frequency, since the THD analyzer needs at least one harmonic for correct operation.
4.1.1.2 Time Domain Analysis
The ADC data is plotted as a waveform in the time domain on the Waveform tab located at the bottom of
the screen.
4.1.1.3 DC Analysis
For DC analysis, the middle section of the application provides DC RMS noise (standard deviation), peak
amplitude, and a DC level meter.
A histogram of the ADC data is plotted on the Histogram tab located at the bottom of the screen. Basic
DC measurements work best when the ADC is driven by an amplifier, stable voltage source, or by shorting
the inputs.
4.1.2 Record Mode
To record/save ADC data, go to the Record To File tab and do the following:
1. If Acquire is on, turn it off. You must stop acquisition before the record feature can be enabled.
2. Enter acquisition settings using the Conversion Mode drop-down control and Sample Rate field. The
Channel selector can be ignored since it has no effect during data recording.
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3. Enter a path in the Destination File field. You can use the folder icon to browse for the file with a
standard file dialog. If the file you enter cannot be opened or created, the record button will be
disabled. If the path points to an existing file, the file will be overwritten when you activate recording.
4. Enter the number of ADC samples to record to the file. You can enter this in time duration or number
of samples; the controls will update automatically to match. The number of samples is limited by
available memory on the MMB0 to a minimum of 2048 samples and a maximum of approximately
2,700,00 points.
5. Click the Record button. You will see the Samples Retrieved bar graph increase. When it reaches the
number of samples you selected, recording will stop and the record button will be turned off.
The data file is a comma-separated values (CSV) file containing comma-delimited decimal ADC values.
The first data column is Channel 1 followed by Channel 2. The data file can be imported into a
spreadsheet for future inspection and analysis.
4.2 Configuration
Sample rate and conversion mode are set to the same for both ADS1271 devices on the EVM.
The three ADS1271 conversion modes are selectable from the drop-down control, Conversion Mode.
The ADS1271 clock is generated by a PLL synthesizer on the MMB0. The synthesizer will generate a
clock/data rate that is as close as possible to the requested frequency, but the data rate may be slightly
different.
The data rate is limited for each of the possible device modes. For high-speed mode, the maximum data
rate is approximately 105kSPS. For other modes, it is approximately 52.5kSPS. The application will
automatically reduce the data rate to the maximum allowed for that mode that is selected.
7
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5 ADS1271EVM Hardware Details
The ADS1271EVM is designed to easily interface with multiple control platforms. Dual-row, header/socket
combinations of J1 and J2 allow connection to external circuitry for evaluation and debug.
5.1 Jumpers and Switches
The jumpers and switches functions are shown below in Table 4
Table 4. Jumper and Switch Descriptions
Jumper/Switch Functions Descriptions
Primary analog input/external reference connectors (from
J1 Analog inputs/external reference (primary) MMB0)
J2 Digital Interface signals Serial Interface and GPIO signals (from MMB0)
J3 Power Power supply connections (from MMB0)
J4 Analog inputs/external reference (aux) Auxiliary analog input/eternal reference connector for U7
J5 Analog inputs/external reference (aux) Auxiliary analog input/eternal reference connector for U7
J6 Power Power selection and supply monitoring
J7 Format/Mode Selection Connection of Format and Mode controls to ADCs
Selection of which analog signal header to connect to buffer,
S1 Analog input to buffer U5
Selection of which analog signal header to connect to buffer,
S2 Analog input to buffer U6
S3 U7 Reference selector Select source of reference for U7
S4 U7 Analog Input selector Select source of analog input for U7
S5 U8 Reference selector Select source of reference for U8
S6 U8 Analog Input selector Select source of analog input for U8
S7 Interface selector Select interface type (FORMAT)
5.2 Analog Connections
5.2.1 Analog Interface, J1, J4, and J5
The ADS1271EVM features several analog input options. Signals can be routed directly to the converters
or can pass through the onboard buffer amplifiers (U5, U6). Signals can be applied to the board through
the standard modular EVM analog connector (J1) or brought in through the auxiliary input connectors (J4,
J5). A set of switches selects which analog connector source is used and whether the buffer amplifiers are
in the signal path. These switches enable several configurations for evaluation. Switch operation and
analog path configuration are described in Section 5.2.2,Table 6 , and Table 7.
For maximum flexibility, the ADS1271EVM is designed for easy interfacing to multiple analog sources.
Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin, dual-
row, header/socket combination at J1. This header/socket provides access to the analog input pins of the
ADS1271.
Table 5. Analog Interface Pinout (J1)
Pin Number Signal Description
J1.1 AIN0N ADS1271 (U7) AINN
J1.2 AIN0P ADS1271 (U7) AINP
J1.3 AIN1N ADS1271 (U8) AINN
J1.4 AIN1P ADS1271 (U8) AINP
J1.5 Unused
J1.6 Unused
J1.7 Unused
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Table 5. Analog Interface Pinout (J1) (continued)
Pin Number Signal Description
J1.8 Unused
J1.15 Unused
J1.18 REF(-) External reference source low side
J1.20 REF(+) External reference source input (2.5V NOM)
J1.9-J1.19 (odd) GND Analog ground connections (except J1.15)
J1.10-J1.16 Unused
(even)
Table 6. Auxiliary Analog Input 1 Pinout (J4)
Pin Number Signal Description
J4.1 AUX1P Auxiliary Signal Input 1 - Positive terminal
J4.2 AUX1N Auxiliary Signal Input 1 - Negative terminal
J4.3 AUXREF1P Auxiliary Reference Input 1 - Positive terminal
J4.4 AUXREF1N Auxiliary Reference Input 1 - Negative terminal
J4.5 GND Ground
Table 7. Auxiliary Analog Input 2 Pinout (J5)
Pin Number Signal Description
J5.1 AUX2P Auxiliary Signal Input 2 - Positive terminal
J5.2 AUX2N Auxiliary Signal Input 2 - Negative terminal
J5.3 AUXREF2P Auxiliary Reference Input 2 - Positive terminal
J5.4 AUXREF2N Auxiliary Reference Input 2 - Negative terminal
J5.5 GND Ground
5.2.2 Analog Input Selection
The analog input signals can be routed directly to the two ADS1271s on the EVM or they can be routed
through an optional buffer amplifier stage built around U5 or U6. Consult the ADS1271 data sheet to
determine the maximum analog input range. Table 8 summarizes the position of switches S1 and S2. S4
and S6 can be used to select the routing of the ADS1271 analog inputs as shown in Table 9.
Table 8. Buffer Amplifier Options - S1 and S2
S1/S2 Position Analog Inputs
Top Input from J1
Middle Input from J4/J5 auxiliary inputs
Bottom No connection
Table 9. ADC Analog Input Options - S4 and S6
S4/S6 Position Analog Inputs
Left Input from Buffer Amplifier
Middle Input from J1
Right Input from J4/J5 auxiliary inputs
9
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5.2.2.1 Buffer Amplifiers
The buffer amplifiers on this EVM are OPA1632s (U5, U6). These amplifiers are optimized for ac
performance and are configured as fully-differential unity gain buffers. They require ±15V supplies, which
are provided from J3 pins 1 and 2.
The OPA1632 requires a common-mode voltage, which is provided on this EVM by U2 and U3. Some
users may not wish to use the buffer amplifier section and provide the ±15V supplies. If the ±15V supplies
are not connected, then having a voltage on the VOCM pins of the amplifiers would exceed their maximum
ratings. Thus, U2 and U3 provide a separate 2.5V reference for the buffer amplifier section rather than
using the same reference as the ADS1271, which would always be powered. For this reason, U2 and U3
power is provided through a separate regulator, U11.
5.3 Digital Interface, J2
The ADS1271EVM is designed to easily interface with multiple control platforms. Samtec part numbers
SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin, dual-row, header/socket
combination at J2. This header/socket provides access to the digital control and serial data pins of the
ADS1271.
Because the ADS1271 devices are capable of daisy-chaining, this EVM has been designed to permit
stacking; up to four EVMs can be stacked, allowing for eight devices to be placed in a signal chain. To
accommodate stacking of EVMs, J2 has some different connections on the top and the bottom side of the
board. Differences between top and bottom connectors are highlighted in Table 10.
Table 10. Digital Interface Pinout (J2)
Pin Number Signal Description
J2.1 SYNC Synchronization Control
J2.2 MODE0 0 = High-Speed Mode
1 = Low-Power Mode
(In either case, only if Mode1=0)
J2.3 CLKX CLKXMODE = 1: master clock output
CLKXMODE = 0: no connection
J2.4 DGND Digital ground
J2.5 SCLK Serial Clock
J2.6 MODE1 0 = Mode determined by MODE0
1 = High-Resolution Mode
J2.7 Unused.
J2.8 FSDIR Indicates FSR direction:
0 = Output (DRDY in SPI™ mode)
1 = Input (FSYNC mode)
J2.9 Top: FSOUT FSOUT: in FSYNC mode, copy of FSR; in SPI mode, not connected
Bottom: FSR FSR: in FSYNC mode, frame-sync input; in SPI mode, DRDY output from U8
J2.10 DGND Digital ground
J2.11 Unused
J2.12 CLKRMODE 0 = Use CLKR for SPI Clock
1 = Use ADC Clock for SPI clock
J2.13 Top: DIN Top: Serial data input
Bottom: DOUT Bottom: Serial data output
J2.14 CLKXMODE 0 = CLKX is High Z
1 = CLKX outputs ADC master clock
J2.15 Unused
J2.16 SCL I2C™ bus serial clock
J2.17 EXTCLK External ADC clock input
J2.18 DGND Digital ground
J2.19 OBCLKSEL Onboard Clock Select:
High to select onboard clock instead of external clock.
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