Texas Instruments bq24295EVM-549 User manual

User's Guide
SLUUAO5B–August 2013–Revised April 2014
bq24295EVM-549 (PWR549) User’s Guide
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Contents
1 Introduction ................................................................................................................... 2
1.1 EVM Features....................................................................................................... 2
1.2 Design Considerations............................................................................................. 2
1.3 General Descriptions............................................................................................... 2
1.4 I/O Description ...................................................................................................... 3
2 Test Summary................................................................................................................ 4
2.1 Equipment ........................................................................................................... 4
2.2 Equipment Setup.................................................................................................... 4
2.3 Procedure............................................................................................................ 6
2.4 Charge Voltage and Current Regulation of VIN and Device ID Verification ................................ 6
3 PCB Layout Guideline ..................................................................................................... 10
4 PCB Thermal Design ...................................................................................................... 10
5 Board Layout, Schematic, and Bill of Materials ........................................................................ 11
5.1 Board Layout....................................................................................................... 11
5.2 Schematic .......................................................................................................... 13
List of Figures
1 OTG Boost Mode 5-V Output Load Regulation Versus PCB Layer Thickness - Default Setting ................. 2
2 Connections of the HPA172 Kit............................................................................................ 5
3 Original Test Setup for PWR549 (bq24295 EVM) ...................................................................... 5
4 Main Window of the bq2429x Evaluation Software ..................................................................... 6
5 Main Window with Enable Termination Unchecked..................................................................... 7
6 Buck Mode Switch Node Waveform, VBUS = 5 V, VBAT = 3.7 V .................................................... 8
7 Buck Mode Input PMID Ripple, VBUS = 5 V, VBAT = 3.7 V........................................................... 8
8 Buck Mode Output Ripple, VBUS = 5 V, VBAT = 3.7 V................................................................ 8
9 Boost Mode Ripple and Duty Cycle; VBAT = 3.7 V..................................................................... 9
10 bq24295 EVM Top Layer.................................................................................................. 11
11 bq24295 EVM Bottom Layer.............................................................................................. 11
12 bq24295 EVM Top Assembly............................................................................................. 12
13 bq24295 EVM Schematic ................................................................................................. 13
List of Tables
1 EVM Connections............................................................................................................ 3
2 Jumper Connections ........................................................................................................ 3
3 Switch Settings............................................................................................................... 3
4 Recommended Operating Conditions..................................................................................... 3
5 Device ID...................................................................................................................... 9
6 Bill of Materials ............................................................................................................. 14
Microsoft, Windows are registered trademarks of Microsoft Corporation.
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Output Load (A)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
2 Layer, 15 mils
2 Layer, 62 mils
2 Layer, 31 mils
2 Layer, 24 mils
OTG Output Voltage (V)
5.2
5.15
5.1
5.05
5
4.95
4.9
4.85
4.8
4.75
4 Layer, 2 x 15 mils
Introduction www.ti.com
1 Introduction
1.1 EVM Features
Refer to the data sheet (SLUSBC1) for detailed features and operation.
1.2 Design Considerations
1. Install the JP1 shunt for proper operation.
2. Disable the watchdog timer if not using the WDG Timer Reset button (illustrated in Figure 4), so the
programmed setting does not reset.
3. The GUI STATUS and FAULT block are helpful in troubleshooting, if the design is having issues.
4. In Boost mode, if not using a battery or power supply with short leads, extra capacitance at J5
(BAT/GND) may be needed.
5. The OTG Low box has to be unchecked and the Enable OTG box must be checked to get into Boost
mode.
6. PWB thickness affects the “On-the-GO” (OTG) Boost Output regulation at load currents over 0.75 A.
An evaluation was performed using different thicknesses of PCBs with the Load Regulation results
shown in Figure 1.
TI recommends using a 4-layer PCB constructed with two 15-mil, 2-oz Cu/layer boards fixed together,
for a total thickness of 31 mils. The 4-layer PCB, has a stack up of a component/routing layer, GND
layer, routing layer and a GND layer. A second choice is a 2-layer, 24-mil PCB, or thinner, with a
component/routing layer and a GND plane layer. The bq24295EVM-549 REV B EVM is built on a 24-
mil thick PCB.
Figure 1. OTG Boost Mode 5-V Output Load Regulation Versus PCB Layer Thickness - Default Setting
1.3 General Descriptions
The bq24295 evaluation module is a complete charger module for evaluating an I2C Controlled single
NVDC-1 charge using the bq2419x devices. For details, see bq24295 data sheet (SLUSBC1).
The bq24295 EVM doesn’t include the USB-to-GPIO interface board. To evaluate the bq24295 EVM, the
USB-to-GPIO interface board must be ordered separately. Search ti.com for "USB-to-GPIO".
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www.ti.com Introduction
1.4 I/O Description
Table 1 contains the EVM connections.
Table 1. EVM Connections
Jack Description
J1-PMID PMID pin connection or power bank output
J1-GND Ground
J2-VBUS Input: positive terminal
J2-GND Input: negative terminal (ground terminal)
J3-SYS Connected to system
J3-GND Ground
J4 USB-to-GPIO connector (USB Interface
Adapter Connector - HPA172)
J5-BAT+ Connected to battery pack
J5-GND Ground
J6 Mini_USB connector
J7-INT INT pin connection
J7-OTG OTG pin connection
J7-CE CE pin connection
J7-GND Ground
Table 2 lists the jumper connections for this EVM.
Table 2. Jumper Connections
Jack Description Factory Setting
JP1 VSYS pull-up for STAT, PG, INT, CE, SCL, SDA Shunt installed
JP2 200-Ωshort between D+ and D– Shunt not installed
JP3 TS1 to GND fault Shunt not installed
Table 3 lists the switch settings for the EVM.
Table 3. Switch Settings
Switch Description Procedure Setting
S2-1 OTG switched to GND: ON OFF
S2-2 CE switched to GND: ON OFF
S2-3 TS 10 kΩswitched to GND: ON ON
S2-4 REGN switched to TS divider: ON ON
PSEL/PG (left) or D+/D– (Right)
S3 Right
Connection
Table 4 gives the recommended operating conditions for this EVM.
Table 4. Recommended Operating Conditions
Symbol Description MIN TYP MAX Unit
Supply voltage, VIN Input voltage from AC adapter input 3.9 5 6 V
Battery voltage, VBAT Voltage applied at VBAT terminal 3.7 4.25 V
Supply current, IAC Maximum input current from AC adapter input 3 A
Output current, IOUT Output current 4 A
Operating junction temperature range, TJ0 125 °C
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Test Summary www.ti.com
2 Test Summary
Section 2.1 –Section 2.3 explains the equipment, the equipment setup, and the test procedures.
2.1 Equipment
2.1.1 Power Supplies
Power supply #1 (PS#1): a power supply capable of supplying 5 V at 1 A is required. While this part can
handle a larger voltage and/or current, it is not necessary for this procedure.
2.1.2 Load #1 (Electronic Load, Constant Voltage < 4.5 V) - Battery Connection
A 0–20 V/0–5 A, > 30-W system, DC electronic load and setting as constant voltage load mode.
Or:
Kepco load: BOP 20–5M, DC 0 to ±20 V, 0 to ±5 A (or higher)
Or:
Real single-cell battery
2.1.3 Load #2 – Use with Boost Mode
PMID-to-GND load, 10 Ω, 5 W or greater
2.1.4 Meters
Five Fluke 75 multimeters, (equivalent or better)
Or:
Three equivalent voltage meters and two equivalent current meters.
The current meters must be capable of measuring 2 A of current.
2.1.5 Computer
A computer with at least one USB port and a USB cable. The bq2429xEVM evaluation software must be
properly installed.
2.1.6 USB-to-GPIO Communication Kit (HPA172-USB Interface Adapter)
2.1.7 Software
Unzip the bq2429xEVM_GUI.zip and double-click on the SETUP.EXE file. Follow the installation steps.
The software supports the Microsoft®Windows®XP and Windows 7 operating systems.
2.2 Equipment Setup
(A) Set PS#1 for 5-V DC, 1-A current limit and then turn off the supply.
(B) Connect the output of PS#1 in series with a current meter (multimeter) to J2 (VBUS and GND), as
shown in Figure 3.
(C) Connect a voltage meter across J2 (VBUS) and J2 (GND).
(D) Turn on the electron Load, set to constant voltage mode and output to 2.5 V. Turn off (disable) Load.
Connect Load to J5 (BAT+ and GND) as shown in Figure 3, via a current meter in the return line of the
load. Connect a voltage meter across J5 (BAT+ and GND).
(E) Connect a voltage meter across J3 (SYS and GND).
(F) Connect HPA172 USB interface adapter to the computer with a USB mini-cable and to J4 with the 10-
pin ribbon cable. The connections are shown in Figure 2.
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To Computer
USB Port
USB Interface
Adapter
I/O
USB
10-pin
Ribbon Cable
‘To EVM’
Texas Instruments
©2006
www.ti.com Test Summary
Figure 2. Connections of the HPA172 Kit
(G) Install jumpers as per Table 2.
(H) Set S2 toggle bits as per Table 3, procedure setting column.
Figure 3. Original Test Setup for PWR549 (bq24295 EVM)
(I) Turn on the computer. Launch the bq2429x evaluation software. The main window of the software is
shown in Figure 4.
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Test Summary www.ti.com
Figure 4. Main Window of the bq2429x Evaluation Software
2.3 Procedure
2.3.1 Current Settings
Make sure EQUIPMENT SETUP steps are followed.
1. ILIM Setting: Set the potentiometer to its lowest value for max input current. Turn the screw on the
potentiometer counterclockwise (Pot should make click sound when fully CCW).
2. Launch BQ2429x EVM GUI application on computer, if not already done.
3. Turn on PS#1
Measure →V (J3(SYS), J3(GND)) = 4.10 ±300 mV
2.4 Charge Voltage and Current Regulation of VIN and Device ID Verification
2.4.1 Software setup (all of these steps are done in the GUI):
• Device address: 6B
• Click the Read button two times, one second apart
• Select Disabled for I2C Watchdog Timer Limit
• Set Input Voltage Limit to 4.2 V
• Set Input Current Limit to 500 mA
• Set Charge Voltage Limit to 4.208 V
• Set Fast Charge Current, ICHG to 512 mA
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www.ti.com Test Summary
• Set Pre-Charge Current Limit to 256 mA
• Un-Check Enable Termination (see Figure 5)
Figure 5. Main Window with Enable Termination Unchecked
• Click the Read button three times, one second apart
Observe →Everything normal at FAULT box
Observe →D1 (STAT) is on
Enable Load #1 from Section 2.1.2. Measure the system and battery voltage.
Measure →V(J3(SYS), J3(GND)) = 3.5 V ±300 mV
Measure →V(J5(BAT), J5(GND)) = 2.5 V ±200 mV
Increase the Load #1 voltage to 3.7 V.
Measure →V(J3(SYS), J3(GND)) = 3.75 V ±200 mV
Measure →IBAT = 500 mA ±200 mA
Measure →V(J5(BAT), J5(GND)) = 3.75 V ±200 mV
In the Software, Select Fast Charge Current, “ICHG” to 1024 mA.
Measure →Iin = 500 mA ±200 mA
2.4.2 Verify the device ID and JEITA shown in the software matches the following table:
Assy Number EVM Part Number Device ID JEITA
PWR549-001 bq24295EVM-549 bq24295 Disabled
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Test Summary www.ti.com
2.4.3 Verify Scope Measurements (see Figure 6 through Figure 8 – 500 ns/div):
Connect scope probe ground lead to Ground J1-GND (make sure lead is short), probe and verify the
following waveforms, as shown in Figure 6 through Figure 8.
Figure 6) Buck Mode Switch Node Waveform - (2 VDC/div): TP left of inductor L1
Figure 7) Buck Mode Input PMID Ripple - (AC coupled 20 mV/div): Right side of C2 Cap
Figure 8) Buck Mode Output System Ripple – (AC coupled 50 mV/div): top side of C12 cap
Measure →Figure 6 – SW node Frequency between 1.25 MHz and 1.6 MHz,
Measure →Figure 6 – SW node Duty cycle between 71 and 81%.
Measure →Figure 7 - PMID AC Ripple < 15 mV excluding high frequency spikes
Measure →Figure 8 - SYS AC Ripple < 10 mV excluding high frequency spikes
Figure 6. Buck Mode Switch Node Waveform, VBUS = 5 Figure 7. Buck Mode Input PMID Ripple, VBUS = 5 V,
V, VBAT = 3.7 V VBAT = 3.7 V
Figure 8. Buck Mode Output Ripple, VBUS = 5 V, VBAT = 3.7 V
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www.ti.com Test Summary
2.4.4 Verify Device ID Using GUI Software and Table 5.
Table 5. Device ID
Assembly Number EVM Part Number Device ID
PWR549-001 bq24295EVM-549 bq24295
2.4.5 Switch to Boost Mode
1. Turn off and disconnect PS#1. May be used in step 2, if needed.
2. Move the voltmeter from J2 (VBUS/GND) to J1 (PMID/GND).
3. If the constant voltage supply connected between BAT+ and GND, from above, is not a 4 quadrant
supply (can source current) then this needs to be replaced with a power source set to 3.7 VDC that
can source current. Connect new power source, if necessary, that is set to 3.7 V and turn on.
4. Apply 10 ohms (5 W or greater) across J1 (PMID(+) to GND(–))
5. Click the GUI read button two times to make sure the latest data is read.
6. Disable the “I2C watchdog timer Limit” if set to a time.
7. Uncheck the “Enable Charge” Box if checked.
8. Uncheck the “OTG Low” box in the GUI.
9. Check the “Enable OTG” if un-checked.
10. Verify switch node waveform
11. Verify PMID to GND on J1 is between 4.9 V and 5.3 V (See Figure 9).
CH2 (5 V/div): SW Node – (Left Side of inductor to GND)
Measure →SW Frequency (TP2) - Frequency between 1.1 MHz and 1.5 MHz, (Period = 1 / fsw)
Measure →SW Duty cycle (TP2) - Duty cycle between 26 and 33%. (tVSW_LOW / period)
Figure 9. Boost Mode Ripple and Duty Cycle; VBAT = 3.7 V
2.4.6 Turn off Power Source connected to BAT+ and GND.
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PCB Layout Guideline www.ti.com
3 PCB Layout Guideline
Minimize the switching node rise and fall times for minimum switching loss. Proper layout of the
components minimizing high-frequency current path loop is important to prevent electrical and magnetic
field radiation and high frequency resonant problems. This PCB layout priority list must be followed in the
order presented for proper layout:
1. Place the input capacitor as close as possible to the PMID and GND pin connections and use the
shortest possible copper trace connection or GND plane.
2. Place the inductor input terminal as close to the SW pin as possible. Minimize the copper area of this
trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the
charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
3. Put an output capacitor near to the inductor and the IC. Tie ground connections to the IC ground with a
short copper trace connection or GND plane.
4. Route analog ground separately from power ground. Connect analog ground and connect power
ground separately. Connect analog ground and power ground together using power pad as the single
ground connection point or use a 0-Ωresistor to tie analog ground to power ground.
5. Use a single ground connection to tie the charger power ground to the charger analog ground just
beneath the IC. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise
coupling.
6. Place decoupling capacitors next to the IC pins and make the trace connection as short as possible.
7. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB
ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground
plane on the other layers.
8. The via size and number should be enough for a given current path.
See the EVM design for the recommended component placement with trace and via locations. For the
QFN information, refer to SCBA017 and SLUA271.
4 PCB Thermal Design
The IC is one of the major heat dissipation components on the EVM, and is cooled with thermal
PowerPAD vias connected to the bottom layer. The copper pour on the bottom layer is 1 in x 2 in
representing a thermal design of this size. Note how there are very few routing etches in the bottom layer
and that they are positioned to maximize (not impede) the flow of heat away from the IC. All good thermal
designs have at least one layer of 2-oz copper (without cuts) to spread the heat (conduction) across the
PCB so it can be dissipated into the air (convection) with minimal heat rise.
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