Texas Instruments SCAU020 User manual

10.9MHz–1175MHz Low Phase NoiseClock Evaluation Board
User's Guide
March 2007 Serial Link Products
SCAU020

2 SCAU020 – March 2007Submit Documentation Feedback

Contents
1 General Description ..................................................................................................... 52 Signal Path and Control Circuitry .................................................................................. 63 Block Description ........................................................................................................ 73.1 Block A ............................................................................................................ 73.2 Block B ............................................................................................................ 73.3 Block C ............................................................................................................ 73.4 Block D ............................................................................................................ 74 Software-Selectable Options ........................................................................................ 75 Installing the Software GUI and USB Driver .................................................................... 86 ChronosGUI ............................................................................................................... 96.1 Using Software-Enabled Automatic PLL Selection .......................................................... 96.2 Manual PLL Block Selection (Advanced Control) .......................................................... 117 Configuring the Board ............................................................................................... 137.1 Programming and Testing Configuration (USB Cable Attached)—Default Configuration............. 137.2 Programming Configuration (USB Cable Attached) ........................................................ 137.3 Testing Configuration from a Saved Configuration (with USB Cable Removed AfterProgramming) ................................................................................................... 138 Schematics and Layout .............................................................................................. 14
Important Notices ............................................................................................................... 20
SCAU020 – March 2007 Table of Contents 3Submit Documentation Feedback

List of Figures
1 CDCE421EVM Evaluation Board .......................................................................................... 52 CDCE421EVM Programming Blocks...................................................................................... 63 Software Installation Screen ................................................................................................ 84 Installation Prompt ........................................................................................................... 85 TI Chronos Software GUI ................................................................................................... 96 Chronos GUI—Loop Filter Configuration Pop-Up ...................................................................... 107 Chronos GUI—Manual PLL Block Selection Pop-Up .................................................................. 118 JP1 Setting for USB Programming Configuration ...................................................................... 139 CDCE421EVM Block Switch Off ......................................................................................... 1410 CDCE421EVM Board Schematic ........................................................................................ 1511 CDCE421EVM Board—Block A Schematic ............................................................................ 1612 CDCE421EVM Board—Block B Schematic ............................................................................ 1713 CDCE421EVM Board—Block C Schematic ............................................................................ 1814 CDCE421EVM Board—Block D Schematic ............................................................................ 19
4List of Figures SCAU020 – March 2007Submit Documentation Feedback

1 General Description
User's GuideSCAU020 – March 2007
10.9MHz–1175MHz Low Phase Noise Clock Evaluation
Board
Figure 1. CDCE421EVM Evaluation Board
Features:
•Easy-to-use evaluation module generates low phase noise clocks between10.9MHz—1175MHz
•Simple device programming via host-powered USB port•Fast configuration through provided software GUI•Total board power provided either through USB port or separate 3.3V and groundconnections
•LVCMOS input interface or crystal input•Standard 6-pin XO package connection available (for CDCE421-enabled XOdevices)
The CDCE421 is a high-performance, low phase noise clock generator. It has two fully integrated,low-noise, liquid crystal (LC)-based voltage-controlled oscillators (VCOs) that operate in the1.75GHz–2.35GHz range.
The CDCE421 has an integrated crystal oscillator circuitry that operates in conjunction with an externalAT-cut crystal to produce a stable frequency reference for the PLL-based frequency synthesizer. A 3.3VLVCMOS level input can also be used instead of a crystal to provide a PLL frequency reference.
The evaluation module (EVM) is designed to quickly demonstrate the electrical performance of the device.This fully assembled and factory-tested EVM allows complete validation of all device functions for a varietyof applications. Throughout this document, the acronym EVM and the phrases evaluation module andevaluation board are synonymous with the CDCE421EVM. Figure 1 illustrates the CDCE421EVM.
For optimum performance, the board is equipped with 50 ΩSMA connectors and well-controlled 50 Ωimpedance microstrip transmission lines.
Windows, Windows XP are registered trademarks of Microsoft Corporation.All other trademarks are the property of their respective owners.
SCAU020 – March 2007 10.9MHz–1175MHz Low Phase Noise Clock Evaluation Board 5Submit Documentation Feedback

www.ti.com
2 Signal Path and Control Circuitry
Signal Path and Control Circuitry
The CDCE421 can accept a 27MHz—38.33MHz frequency input from either an LVCMOS source (up to3.3V) or a crystal in the same frequency range.
The CDCE421EVM is divided into four blocks. The programming section and device power for each sectorcan be enabled or disabled through individual switches provided for each block. For example, in order toenable power and programming for Block A, the switch must be in the setting shown in Figure 2 . Theother blocks are enabled and disabled with the respective switches in the same manner.
The CDCE421 output frequency is always an integer multiple or integer divide of the input frequency, andis determined through selection of VCO1 or VCO2 and the appropriate prescalar and output divider, basedon the CDCE421 data sheet.
The loop filter selection affects the output frequency phase noise and should be considered in conjunctionwith the type of input used.
In LVDS mode, the device can achieve up to 500MHz output. In LVPECL mode, the device can achieve1175MHz output. The output signaling level and LVPECL termination are selectable through the softwareinterface.
Figure 2. CDCE421EVM Programming Blocks
10.9MHz–1175MHz Low Phase Noise Clock Evaluation Board6 SCAU020 – March 2007Submit Documentation Feedback

www.ti.com
3 Block Description
3.1 Block A
3.2 Block B
3.3 Block C
3.4 Block D
4 Software-Selectable Options
Block Description
This section discusses the four EVM blocks.
Block A includes a CDCE421 QFN device that accepts an LVCMOS reference input through the verticalSMA input connector (Ref Input) which is ac-coupled onto the board.
This block includes a CDCE421 QFN device that uses an AT-cut crystal. This block can be used as eitheran XO or a VCXO. For use as an XO or VCXO, the crystal should be mounted on either of the two crystalfootprints on the board. A vertical SMA input connector must also be installed on the provided footprint tobe used as the control voltage input for use as a VCXO.
Block C includes a CDCE41 device in its bare die form, packaged within a 5x7 oscillator. The oscillatorpackage also includes a fixed frequency crystal with a specified load and range. Oscillators with differentfrequency crystals that contain a CDCE421 device can be obtained through Pletronics.
The fourth block, D, includes a socket fitting the oscillator part used in Block C.
The provided EVM software is controlled through a graphical user interface (GUI). The software allowsusers to easily send commands to the CDCE421 through the host-powered USB interface. The EVMincludes a slave USB controller that transmits the commands to the single-pin programming interfaceincluded on the CDCE421. DC power for the USB controller can be provided either from the 5V power pinin the USB cable or by using an external 5V ac adapter (plugged into the slot available on the EVM).
In addition to writing commands to the CDCE421 SRAM while the board is powered, software commandscan also be stored in either the nonvolatile USB microcontroller memory or the EEPROM included withinthe CDCE421. This architecture allows users to start the EVM in the desired state without requiringadditional programming at power-up.
Note that the CDCE421 does have a permanent EEPROM lock mode. When this mode is selected, theembedded EEPROM in the CDCE421 cannot be changed. This mode is useful when setting finalconfigurations.
SCAU020 – March 2007 10.9MHz–1175MHz Low Phase Noise Clock Evaluation Board 7Submit Documentation Feedback

www.ti.com
5 Installing the Software GUI and USB Driver
Installing the Software GUI and USB Driver
The CDCE421EVM software can be installed on a PC running the Microsoft Windows
®
2000 operatingsystem or higher (including Windows XP
®
).
To start software installation, run the ChronosSetup.msi file (available on the CD shipped with the EVM).Figure 3 appears. Be sure to note the installation folder; the USB driver must be installed in the same aftersetup completes and the USB cable is connected. See Figure 4 .
Figure 3. Software Installation Screen
Note the program file location; the USB controller driver is in the same location.
Figure 4. Installation Prompt
810.9MHz–1175MHz Low Phase Noise Clock Evaluation Board SCAU020 – March 2007Submit Documentation Feedback

www.ti.com
6 ChronosGUI
6.1 Using Software-Enabled Automatic PLL Selection
ChronosGUI
After the setup wizard completes, start the GUI interface from the Start menu (Start →TexasInstruments →Chronos Eval →TIChronosGUI.exe).
Connect the USB cable to the EVM. If Microsoft Windows prompts you for an appropriate driver, do notuse the automatic search option. Select a manual installation. When prompted for the driver location,browse to the Chronos GUI file folder that was created during installation. (If the operating system doesnot ask for a driver, no additional action is needed.)
Once the USB driver installation completes, the GUI software should connect properly and be ready foruse. A green light in the USB communication box indicates a good USB connection; a red light indicates afaulty USB connection. If the connection is not established, attempt to re-install the drivers.
Figure 5 shows the Chronos GUI used to navigate the EVM software.
Figure 5. TI Chronos Software GUI
The software illustration Figure 5 shows the on-chip PLL structure of the CDCE421. Through this screen,the user can change the Input Frequency, PFD Charge Pump, Loop Filter, and Output Type. The otherfeatures are selected by the software; user-selectable options are described in this section.Step 1. IC Block Configuration and Input Calculator.Before programming the PLL, the specific EVM block that is being programmed must be selected inthe IC Block Config section of the GUI. For any block in the EVM being used, the first row ofcalculations is useful when trying to investigate the input frequency to the CDCE421 needed to obtaina desired output frequency. The input frequency is obtained by pressing the Calculate button.Step 2. Store Crystal Frequency.If a crystal input is used for Block B of the EVM, the crystal frequency must be entered into the spaceprovided; click on the Device_EEPROM drop-down menu at the top of the software GUI. A menu itemlabeled Save Block B–XTAL Freq to EEPROM appears; this menu item must be selected. The crystal
SCAU020 – March 2007 10.9MHz–1175MHz Low Phase Noise Clock Evaluation Board 9Submit Documentation Feedback

www.ti.com
ChronosGUI
frequency should be entered here in this format: xx.xxx (specified in MHz).Step 3. Output Calculator and Apply PLL Settings.The second row of calculations is used to obtain the PLL settings necessary to achieve a particularoutput frequency provided a given input frequency to CDCE421. The input must be entered in thesecond row as well as the location provided at the input of the PLL block diagram. After the Calculatebutton is pressed, the adjacent drop-down menu populates with several choices for the given input.The desired output can then be chosen from this list. Choosing one output sets the divider settingswithin the PLL. Clicking Apply next to the drop-down menu results in writing the PLL settings to theSRAM. If LVPECL output is desired, click Output Type until the LVPECL option displays. This optionautomatically enables onboard LVPECL termination. If LVDS output is desired, use Output Type toselect the LVDS option.Step 4. PLL Bandwidth Select.If the user wants to adjust the PLL bandwidth, click the Loop Filter block, bringing a pop-up screen asshown in Figure 6 .
Figure 6. Chronos GUI—Loop Filter Configuration Pop-Up
For a clean reference input to the CDCE421 (for example, from an oscillator or crystal), the maximumbandwidth and phase margin setting must be used: 400kHz bandwidth and 80 degrees. The PhaseFrequency Detector (PFD) charge pump current must be set to its maximum, 224 µA. The PFD chargepump current can be set by clicking on the PDF Charge Pump block, presenting a drop-down menuwith the various charge pump current settings.For a dirty reference input to the CDCE421, the minimum bandwidth of 50kHz must be used.Additionally, to reduce the output jitter for a dirty input, the phase margin can also be reduced to nearits minimum (30 degrees), depending on the integration limits of the jitter that are important for a givenapplication. To reduce the output jitter further, the charge pump current can be reduced to its minimum(56 µA), depending on the integration limits of the jitter.Step 5. Write to CDCE421 EEPROM.To write any particular setting to the EEPROM (locking or nonlocking), the Device_EEPROMdrop-down menu (at the top of the screen) must be selected. This menu contains the items Writesettings to EEPROM (No locking) and Write settings to EEPROM (Locking). Choose the appropriateoption after setting the desired PLL configurations to write to the EEPROM in its appropriate mode.
10.9MHz–1175MHz Low Phase Noise Clock Evaluation Board10 SCAU020 – March 2007Submit Documentation Feedback