Texas Instruments LMX2572LPEVM User manual

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LMX2572LPEVM Evaluation Instructions
User's Guide
SNAU235–May 2018
LMX2572LPEVM Evaluation Instructions
The LMX2572LPEVM is designed to evaluate the performance of LMX2572LP. This board consists of a
LMX2572LP device.
The LMX2572LP is a low-power, high-performance wideband synthesizer that can generate any frequency
from 12.5 MHz to 2 GHz without using an internal VCO doubler. The PLL delivers excellent performance
while consuming just 70 mA from a single 3.3-V supply.
Contents
1 LMX2572LPEVM Evaluation Module...................................................................................... 3
2 Setup .......................................................................................................................... 3
3 Typical Measurement ....................................................................................................... 6
4 Schematic ................................................................................................................... 13
5 PCB Layout and Layer Stack-Up......................................................................................... 15
6 Bill of Materials ............................................................................................................. 18
7 Troubleshooting Guide .................................................................................................... 19
Appendix A Using Different Reference Clock................................................................................ 20
Appendix B Reference PRO.................................................................................................... 21
List of Figures
1 EVM Connection Diagram.................................................................................................. 3
2 Select Device in TICS Pro.................................................................................................. 5
3 Default Mode................................................................................................................. 5
4 MUXout_SW Switch......................................................................................................... 5
5 Loop Filter .................................................................................................................... 6
6 Default Output................................................................................................................ 7
7 Phase Adjustment Setting.................................................................................................. 7

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8 Phase Adjustment ........................................................................................................... 8
9 Calibration-Free Automatic Ramp Setting................................................................................ 9
10 Calibration-Free Automatic Ramp (CHDIV = 4) ......................................................................... 9
11 Automatic Ramp Setting .................................................................................................. 10
12 Automatic Ramp (CHDIV = 4)............................................................................................ 10
13 FSK SPI FAST Mode Setting............................................................................................. 11
14 FSK SPI FAST Mode...................................................................................................... 11
15 Readback Setting .......................................................................................................... 12
16 Register Readback......................................................................................................... 12
17 LMX2572LPEVM Schematic (Page 1) .................................................................................. 13
18 LMX2572LPEVM Schematic (Page 2) .................................................................................. 14
19 PCB Layer Stack-Up....................................................................................................... 15
20 Top Layer ................................................................................................................... 15
21 GND Layer .................................................................................................................. 16
22 Power Layer ................................................................................................................ 16
23 Bottom Layer................................................................................................................ 17
24 Troubleshooting Guide .................................................................................................... 19
25 Output Termination Schematic ........................................................................................... 22
26 Default Output Phase Nosie.............................................................................................. 23
27 Default Output Waveform ................................................................................................. 23
28 Firmware Requirement .................................................................................................... 23
29 Firmware Loader ........................................................................................................... 24
30 BSL Button.................................................................................................................. 24
31 Update Firmware........................................................................................................... 25
32 Firmware Update Complete............................................................................................... 25
33 USB Communications ..................................................................................................... 26
List of Tables
1 Loop Filter Configuration.................................................................................................... 6
2 Phase Adjustment Setting.................................................................................................. 7
3 Calibration-free Automatic Ramp Example............................................................................... 8
4 Automatic Ramp Example.................................................................................................. 9
5 FSK SPI FAST Mode Example........................................................................................... 10
6 Bill of Materials ............................................................................................................. 18
7 Reference Clock Input Configuration.................................................................................... 20
8 Reference PRO Output Frequency Selection .......................................................................... 21
9 Reference PRO Output Format Selection .............................................................................. 22
10 Output Termination Configuration........................................................................................ 22
Trademarks
All trademarks are the property of their respective owners.

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LMX2572LPEVM Evaluation Instructions
1 LMX2572LPEVM Evaluation Module
1.1 Evaluation Module Contents
In the box, there is:
• One LMX2572LPEVM board (SV601308-004)
• One Reference PRO board (SV601349)
• Two SMA Male-to-Male adaptors (132168)
• One USB cable
• One 10-pin ribbon cable
1.2 Evaluation Setup Requirement
The evaluation requires the following hardware and software:
• A DC power supply
• A spectrum analyzer or a signal analyzer
• A PC running Windows 7 or more recent version
• An oscilloscope (optional)
• A high quality signal generator (optional)
• Texas Instruments Clocks and Synthesizers TICS Pro software
• Texas Instruments PLLatinum Simulator Tool (optional)
1.3 Resources
Related evaluation and development resources are as follows:
•LMX2572LP data sheet
•TICS Pro software
•PLLatinum Simulator Tool (PLL Sim)
2 Setup
2.1 Connection Diagram
Figure 1. EVM Connection Diagram

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2.2 Power Supply
Apply 3.3 V to the VCC SMA connector. The acceptable supply voltage range is 3 V to 3.6 V. The
maximum current consumption in the most extreme configuration must not exceed 150 mA.
By default, the onboard DC/DC converter is not used.
2.3 Reference Clock
Use the SMA Male-to-male adopter to connect the OSCinP SMA connector with one of the outputs from
the Reference PRO. The OSCinM SMA connector is not connected to LMX2572LP, so this connector can
be left open.
The EVM is configured for single-ended input with the OSCin pin connected to the OSCinP SMA
connector and the OSCinM pin 50-Ωterminated onboard. If required, the EVM can be modified to operate
with a different clock source in a different configuration. See Appendix A for more details.
Terminate the unused output of the Reference PRO board with a 50-Ωresistor or SMA load. By default,
the output clock from the Reference PRO is a 100-MHz LVPECL clock. Appendix B has the details of the
Reference PRO.
2.4 RF Output
Connect either the RFoutAP or RFoutAM SMA connector to a signal analyzer. The unused connector
must be terminated with a 50-Ωresistor or SMA load. Output frequency is 1.5 GHz and the amplitude is
about +0.5 dBm.
By default, the TICS Pro evaluation software has RFoutB power down. These SMA connectors can be left
open.
2.5 Programming
Connect the ribbon cable from the Reference PRO to the LMX2572LPEVM.
Connect the USB cable from a PC to USB port in the Reference PRO. This provides power supply to the
Reference PRO board and communication with the TICS Pro. A firmware update may be required. See
Appendix B for more details.

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LMX2572LPEVM Evaluation Instructions
2.6 Evaluation Software
Download and install TICS Pro to a PC.
Run the software and follow these steps to start the program.
1. Go to "Select Device" →"PLL + VCO" →"LMX2572" →"LMX2572LP".
Figure 2. Select Device in TICS Pro
2. Go to "Default Configuration" →"Default Mode YYYY-MM-DD".
Figure 3. Default Mode
2.7 EVM Strap Options
2.7.1 MUXout_SW
There are two switches in MUXout_SW. Switch 1 is used for register readback, while Switch 2 is used to
provide a visual PLL lock status through the LED D1. By default, both switches are in the Make position.
To read back register in TICS Pro, set Switch 2 to the Break position.
Figure 4. MUXout_SW Switch

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LMX2572LPEVM Evaluation Instructions
3 Typical Measurement
3.1 Default Configuration
3.1.1 Loop Filter
The parameters for the loop filter are listed in Table 1.
Table 1. Loop Filter Configuration
PARAMETER VALUE
VCO frequency Designed for 6 GHz, but works
over the whole frequency range
VCO gain 66 MHz/V
Effective charge pump gain 2500 µA
Phase detector frequency 100 MHz
Loop bandwidth 115 kHz
Phase margin 48 degrees
C1_LF, C3_LF Open
C2_LF 15 nF
C4_LF 2.2 nF
R2_LF 330 Ω
R3_LF, R4_LF 0 Ω
Figure 5. Loop Filter
3.1.2 Typical Output
1. Follow Section 2 to set up the evaluation.
2. Click "Write All Registers" to write all the registers to LMX2572LP.
The default output is 1.5 GHz.

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Figure 6. Default Output
3.2 Additional Tests
3.2.1 Phase Adjustment
Use Equation 1 to adjust the phase of the RF output signal.
Phase shift in degree = 360° × (MASH_SEED / PLL_DEN) × (P / CHDIV)
where
• P = 2 when VCO_PHASE_SYNC_EN = 1, otherwise P = 1 (1)
Table 2 and Equation 2 show an example.
Table 2. Phase Adjustment Setting
PARAMETER EXAMPLE VALUE
MASH_SEED 800
PLL_DEN 1000
CHDIV 32
VCO_PHASE_SYNC_EN 0
Phase shift = 360° × (800 / 1000) × (1 / 32) = 9° (2)
The user can write 800 to MASH_SEED 40 times to get the 360° phase shift.
Figure 7. Phase Adjustment Setting

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Figure 8. Phase Adjustment
3.2.2 Calibration-Free Automatic Ramping
The LMX2572LP supports linear frequency ramp without the need of VCO calibration in the middle of the
ramp. The output waveform is a continuous frequency sweep between the start and the end frequencies.
However, the frequency ramp range is limited. When using ramp, these parameters must be set
accordingly:
• OUT_FORCE = 1
• LD_DLY = 0
• PLL_DEN = 232 – 1
Table 3. Calibration-free Automatic Ramp Example
PARAMETER EXAMPLE VALUE
Ramping start frequency 4795 MHz
Ramping stop frequency 4805 MHz
Phase detector frequency 50 MHz
Ramp up / down time 200 µs
RAMP_LIMIT_HIGH 4995 MHz
RAMP_LIMIT_LOW 4595 MHz
This is a triangular ramp example. Ramp up is defined by RAMP0 while ramp down is defined by RAMP1.
RAMP_THRESH, RAMP_DLY_CNT, and RAMP_SCALE_COUNT are set to "don't care" because there is
no plan to trigger VCO calibration. RAMP_MANUAL = 0 means Automatic Ramping mode.
Set RAMP_EN = 1 to start ramping. Set RAMP_EN = 0 to turn off ramping.

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Figure 9. Calibration-Free Automatic Ramp Setting
Figure 10. Calibration-Free Automatic Ramp (CHDIV = 4)
3.2.3 Automatic Ramping
This ramping mode supports wider ramp frequency, but there are glitches in the middle of the ramp
because of the VCO calibrations that are required to ensure the continuity of the ramp.
Table 4. Automatic Ramp Example
PARAMETER EXAMPLE VALUE
Ramping start frequency 4740 MHz
Ramping stop frequency 4860 MHz
Phase detector frequency 50 MHz
Ramp up / down time 1000 µs
RAMP_LIMIT_HIGH 5060 MHz
RAMP_LIMIT_LOW 4540 MHz
fOSCin 100 MHz
CAL_CLK_DIV 0
RAMP_THRESH 40 MHz
Pause time for VCO calibration 500 µs

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Figure 11. Automatic Ramp Setting
Figure 12. Automatic Ramp (CHDIV = 4)
3.2.4 FSK Modulation
The LMX2572LP supports direct digital FSK modulation. The FSK SPI mode supports discrete 2-, 4-, or 8-
level FSK modulation while the FSK SPI FAST and FSK I2S modes support arbitrary level FSK
modulation. Table 5 shows a FSK SPI FAST mode example.
Table 5. FSK SPI FAST Mode Example
PARAMETER EXAMPLE VALUE
Phase detector frequency 100 MHz
CHDIV 8
PLL_DEN 8000000
FSK_DEV_SCALE 1
Frequency deviation ±648 Hz; ±1944 Hz

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Write the correct values to the FSK_SPI_FAST_DEV register field. The output of LMX2572LP is a discrete
4-level FSK modulation signal.
Figure 13. FSK SPI FAST Mode Setting
Figure 14. FSK SPI FAST Mode

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3.2.5 Register Readback
To read back the written register values, follow these steps:
1. Set MUXout_SW Switch 2 to Break position. See Section 2.7.1 for details.
2. Set MUXOUT_LD_SEL to Readback in TICS Pro.
Figure 15. Readback Setting
3. Click on the Register Name that you want to read back.
4. Click the Read Register button to read back the register value.
Figure 16. Register Readback

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4 Schematic
Figure 17. LMX2572LPEVM Schematic (Page 1)

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Figure 18. LMX2572LPEVM Schematic (Page 2)

Top layer
RO4003 (Er = 3.38)
16 mil
GND layer
FR4 (Er = 4.6)
Power layer
FR4 (Er = 4.6)
Bottom layer
62 mil
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5 PCB Layout and Layer Stack-Up
5.1 PCB Layer Stack-Up
The top layer is 1-oz. copper.
Figure 19. PCB Layer Stack-Up
5.2 PCB Layout
Figure 20. Top Layer

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Figure 21. GND Layer
Figure 22. Power Layer

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Figure 23. Bottom Layer

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6 Bill of Materials
Table 6. Bill of Materials
DESIGNATOR QUANTITY DESCRIPTION PART NUMBER MANUFACTURER
C1, C3, C9, C14, C15, C17, C19, C30 8 CAP, CERM, 0.1 µF, 16 V, ±5%, X7R,
0603 0603YC104JAT2A AVX
C2, C4, C8, C16 4 CAP, CERM, 10 µF, 10 V, ±10%, X5R,
0805 C0805C106K8PACTU Kemet
C2_LF 1 CAP, CERM, 0.015 µF, 50 V, ±10%,
X7R, 0603 GRM188R71H153KA01D MuRata
C4_LF 1 CAP, CERM, 2200 pF, 50 V, ±5%,
C0G/NP0, 0603 GRM1885C1H222JA01D MuRata
C5, C7, C10, C12 4 CAP, CERM, 0.01 µF, 16 V, ±10%, X7R,
0402 520L103KT16T AT Ceramics
C18, C23, C26, C27, C28, C29 6 CAP, CERM, 1 µF, 16 V, ±10%, X7R,
0603 C1608X7R1C105K080AC TDK
C20, C21, C22 3 CAP, CERM, 10 µF, 10 V, ±20%, X5R,
0603 C1608X5R1A106M080AC TDK
C24 1 CAP, CERM, 0.01 µF, 50 V, ±5%, X7R,
0603 C0603C103J5RACTU MuRata
C25 1 CAP, CERM, 0.47 µF, 25 V, ±10%, X7R,
0603 GRM188R71E474KA12D Kemet
CE_TP, CSB_TP, GND_TP,
MUXout_TP, RampCLK_TP,
RampDIR_TP, SCK_TP, SDI_TP,
SYNC_TP, SysRefReq_TP, Vcc_TP,
VccRF_TP, Vtune_TP
13 Test Point, Compact, White, TH 5007 Keystone
Cin_0 1 CAP, CERM, 10 µF, 25 V, ±10%, X5R,
0805 GRM219R61E106KA12D MuRata
Cout0 1 CAP, CERM, 22 µF, 16 V, ±10%, X5R,
0805 C2012X5R1C226K125AC TDK
Css 1 CAP, CERM, 3300 pF, 50 V, ±5%,
C0G/NP0, 0603 GRM1885C1H332JA01D MuRata
D1 1 LED, Green, SMD LTST-C190GKT Lite-On
L1_TPS 1 Inductor, Shielded, Composite, 2.2 µH,
3.7 A, 0.02 Ω, SMD XFL4020-222MEB Coilcraft
MUXout_SW 1 Switch, SPST, Slide, Off-On, 2 Pos, 0.1
A, 20 V, SMD 219-2MST CTS Electrocomponents
OSCinM, OSCinP, SYNC, SysRef, Vcc 5 Connector, SMT, End launch SMA 50 Ω142-0701-851 Emerson Network
Power Connectivity
R1 1 RES, 330 Ω, 5%, 0.1 W, 0603 RC0603JR-07330RL Yageo America
R2 1 RES, 100 kΩ, 5%, 0.1 W, 0603 CRCW0603100KJNEA Vishay-Dale
R2_LF 1 RES, 330 Ω, 5%, 0.1 W, 0603 CRCW0603330RJNEA Vishay-Dale
R3_LF, R4_LF, R12, R15, R24, R26,
R31 7 RES, 0 Ω, 5%, 0.1 W, 0603 CRCW06030000Z0EA Vishay-Dale
R5, R7, R8, R9, R16, R19, R20, R22 8 RES, 12 kΩ, 5%, 0.1 W, 0603 CRCW060312K0JNEA Vishay-Dale
R25, R30 2 RES, 51 Ω, 5%, 0.1 W, 0603 CRCW060351R0JNEA Vishay-Dale
R34, R35, R36, R41, R42, R43, R44,
R45 8 RES, 0 Ω, 5%, 0.1 W, 0603 CRCW06030000Z0EA Vishay-Dale
Rfbb1 1 RES, 180 kΩ, 0.1%, 0.1 W, 0603 RT0603BRD07180KL Yageo America
Rfbt1 1 RES, 562 kΩ, 1%, 0.1 W, 0603 CRCW0603562KFKEA Vishay-Dale
RFoutAM, RFoutAP, RFoutBM, RFoutBP 4 JACK, SMA, 50 Ω, Gold, Edge Mount 142-0771-831 Johnson
U1 1 High Performance, Wideband PLLatinum
RF Synthesizer LMX2572LPRHAR Texas Instruments
uWire 1 Header (shrouded), 100 mil, 5x2, Gold
plated, SMD 52601-S10-8LF FCI

Device locked Congratulation!
Start
Yes
Verify hardware setup:
x Validate power supply is connected, turned on, and current limit is appropriate for the device.
x Validate OSCin signal is supplied and turned on, if required.
x Ensure programming cable is hooked up to the board.
x Ensure spectrum analyzer center frequency matches target frequency. Choose wide span so that the carrier can
be seen if it is off frequency.
x Ensure device is not powered down by the CE pin.
x Load all registers (Ctrl+L).
Device locked Congratulation!
No
Yes
Verify software setup:
x 5HYHUWWRGHIDXOWPRGHLQWKHVRIWZDUHXQGHU³'HIDXOW&RQILJXUDWLRQ´.
x Validate that no boxes are red. If so, mouse over and read the tool tips.
x Ensure that all the frequency boxes values are correct. Also understand that the VCO frequency could be
different than the output frequency as there are often dividers after the boxes.
x Load all registers (Ctrl+L).
x Try Readback at this point, if necessary.
Device locked Congratulation!
No
Yes
Verify communications:
x *RWR³86%&RPPXQLFDWLRQV´, ³,QWHUIDFH´, ensure that the USB2ANY button is turned green. &OLFN³,GHQWLI\´WR
have the program blink the green LED.
x Send simple one way communication to the device such as: POWERDOWN, RESET, or change the status of a
pin. Realize that if a RESET is done, do a Ctrl+L to refresh the registers afterwards. For POWERDOWN, you can
validate this looking at the current on the power supply.
Device locked Congratulation!
No
Yes
No
Contact TI support
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7 Troubleshooting Guide
If the EVM does not work as expected, use Figure 24 to identify potential root causes. Consider the
following:
• Do not make modifications to the EVM or change the default settings until AFTER it is verified to be
working.
• Register readback requires the correct hardware and software setup. See Section 3.2.5 for details.
• The POR current of the LMX2572LPEVM is approximately 30 mA.
• The power-down current of the LMX2572LPEVM is approximately 2.5 mA.
Figure 24. Troubleshooting Guide

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Using Different Reference Clock
Appendix A
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Using Different Reference Clock
These are the different options to provide a reference clock to LMX2572LPEVM. By default, the EVM is
configured for an external single-ended clock.
Table 7. Reference Clock Input Configuration
INPUT EXTERNAL CLOCK CRYSTAL OSCILLATOR
Single-
ended
Differential
(LVDS)