Texas Instruments LMX2572LPEVM User manual

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LMX2572LPEVM Evaluation Instructions
User's Guide
SNAU235–May 2018
LMX2572LPEVM Evaluation Instructions
The LMX2572LPEVM is designed to evaluate the performance of LMX2572LP. This board consists of a
LMX2572LP device.
The LMX2572LP is a low-power, high-performance wideband synthesizer that can generate any frequency
from 12.5 MHz to 2 GHz without using an internal VCO doubler. The PLL delivers excellent performance
while consuming just 70 mA from a single 3.3-V supply.
Contents
1 LMX2572LPEVM Evaluation Module...................................................................................... 3
2 Setup .......................................................................................................................... 3
3 Typical Measurement ....................................................................................................... 6
4 Schematic ................................................................................................................... 13
5 PCB Layout and Layer Stack-Up......................................................................................... 15
6 Bill of Materials ............................................................................................................. 18
7 Troubleshooting Guide .................................................................................................... 19
Appendix A Using Different Reference Clock................................................................................ 20
Appendix B Reference PRO.................................................................................................... 21
List of Figures
1 EVM Connection Diagram.................................................................................................. 3
2 Select Device in TICS Pro.................................................................................................. 5
3 Default Mode................................................................................................................. 5
4 MUXout_SW Switch......................................................................................................... 5
5 Loop Filter .................................................................................................................... 6
6 Default Output................................................................................................................ 7
7 Phase Adjustment Setting.................................................................................................. 7

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8 Phase Adjustment ........................................................................................................... 8
9 Calibration-Free Automatic Ramp Setting................................................................................ 9
10 Calibration-Free Automatic Ramp (CHDIV = 4) ......................................................................... 9
11 Automatic Ramp Setting .................................................................................................. 10
12 Automatic Ramp (CHDIV = 4)............................................................................................ 10
13 FSK SPI FAST Mode Setting............................................................................................. 11
14 FSK SPI FAST Mode...................................................................................................... 11
15 Readback Setting .......................................................................................................... 12
16 Register Readback......................................................................................................... 12
17 LMX2572LPEVM Schematic (Page 1) .................................................................................. 13
18 LMX2572LPEVM Schematic (Page 2) .................................................................................. 14
19 PCB Layer Stack-Up....................................................................................................... 15
20 Top Layer ................................................................................................................... 15
21 GND Layer .................................................................................................................. 16
22 Power Layer ................................................................................................................ 16
23 Bottom Layer................................................................................................................ 17
24 Troubleshooting Guide .................................................................................................... 19
25 Output Termination Schematic ........................................................................................... 22
26 Default Output Phase Nosie.............................................................................................. 23
27 Default Output Waveform ................................................................................................. 23
28 Firmware Requirement .................................................................................................... 23
29 Firmware Loader ........................................................................................................... 24
30 BSL Button.................................................................................................................. 24
31 Update Firmware........................................................................................................... 25
32 Firmware Update Complete............................................................................................... 25
33 USB Communications ..................................................................................................... 26
List of Tables
1 Loop Filter Configuration.................................................................................................... 6
2 Phase Adjustment Setting.................................................................................................. 7
3 Calibration-free Automatic Ramp Example............................................................................... 8
4 Automatic Ramp Example.................................................................................................. 9
5 FSK SPI FAST Mode Example........................................................................................... 10
6 Bill of Materials ............................................................................................................. 18
7 Reference Clock Input Configuration.................................................................................... 20
8 Reference PRO Output Frequency Selection .......................................................................... 21
9 Reference PRO Output Format Selection .............................................................................. 22
10 Output Termination Configuration........................................................................................ 22
Trademarks
All trademarks are the property of their respective owners.

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LMX2572LPEVM Evaluation Instructions
1 LMX2572LPEVM Evaluation Module
1.1 Evaluation Module Contents
In the box, there is:
• One LMX2572LPEVM board (SV601308-004)
• One Reference PRO board (SV601349)
• Two SMA Male-to-Male adaptors (132168)
• One USB cable
• One 10-pin ribbon cable
1.2 Evaluation Setup Requirement
The evaluation requires the following hardware and software:
• A DC power supply
• A spectrum analyzer or a signal analyzer
• A PC running Windows 7 or more recent version
• An oscilloscope (optional)
• A high quality signal generator (optional)
• Texas Instruments Clocks and Synthesizers TICS Pro software
• Texas Instruments PLLatinum Simulator Tool (optional)
1.3 Resources
Related evaluation and development resources are as follows:
•LMX2572LP data sheet
•TICS Pro software
•PLLatinum Simulator Tool (PLL Sim)
2 Setup
2.1 Connection Diagram
Figure 1. EVM Connection Diagram

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2.2 Power Supply
Apply 3.3 V to the VCC SMA connector. The acceptable supply voltage range is 3 V to 3.6 V. The
maximum current consumption in the most extreme configuration must not exceed 150 mA.
By default, the onboard DC/DC converter is not used.
2.3 Reference Clock
Use the SMA Male-to-male adopter to connect the OSCinP SMA connector with one of the outputs from
the Reference PRO. The OSCinM SMA connector is not connected to LMX2572LP, so this connector can
be left open.
The EVM is configured for single-ended input with the OSCin pin connected to the OSCinP SMA
connector and the OSCinM pin 50-Ωterminated onboard. If required, the EVM can be modified to operate
with a different clock source in a different configuration. See Appendix A for more details.
Terminate the unused output of the Reference PRO board with a 50-Ωresistor or SMA load. By default,
the output clock from the Reference PRO is a 100-MHz LVPECL clock. Appendix B has the details of the
Reference PRO.
2.4 RF Output
Connect either the RFoutAP or RFoutAM SMA connector to a signal analyzer. The unused connector
must be terminated with a 50-Ωresistor or SMA load. Output frequency is 1.5 GHz and the amplitude is
about +0.5 dBm.
By default, the TICS Pro evaluation software has RFoutB power down. These SMA connectors can be left
open.
2.5 Programming
Connect the ribbon cable from the Reference PRO to the LMX2572LPEVM.
Connect the USB cable from a PC to USB port in the Reference PRO. This provides power supply to the
Reference PRO board and communication with the TICS Pro. A firmware update may be required. See
Appendix B for more details.

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2.6 Evaluation Software
Download and install TICS Pro to a PC.
Run the software and follow these steps to start the program.
1. Go to "Select Device" →"PLL + VCO" →"LMX2572" →"LMX2572LP".
Figure 2. Select Device in TICS Pro
2. Go to "Default Configuration" →"Default Mode YYYY-MM-DD".
Figure 3. Default Mode
2.7 EVM Strap Options
2.7.1 MUXout_SW
There are two switches in MUXout_SW. Switch 1 is used for register readback, while Switch 2 is used to
provide a visual PLL lock status through the LED D1. By default, both switches are in the Make position.
To read back register in TICS Pro, set Switch 2 to the Break position.
Figure 4. MUXout_SW Switch

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3 Typical Measurement
3.1 Default Configuration
3.1.1 Loop Filter
The parameters for the loop filter are listed in Table 1.
Table 1. Loop Filter Configuration
PARAMETER VALUE
VCO frequency Designed for 6 GHz, but works
over the whole frequency range
VCO gain 66 MHz/V
Effective charge pump gain 2500 µA
Phase detector frequency 100 MHz
Loop bandwidth 115 kHz
Phase margin 48 degrees
C1_LF, C3_LF Open
C2_LF 15 nF
C4_LF 2.2 nF
R2_LF 330 Ω
R3_LF, R4_LF 0 Ω
Figure 5. Loop Filter
3.1.2 Typical Output
1. Follow Section 2 to set up the evaluation.
2. Click "Write All Registers" to write all the registers to LMX2572LP.
The default output is 1.5 GHz.

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Figure 6. Default Output
3.2 Additional Tests
3.2.1 Phase Adjustment
Use Equation 1 to adjust the phase of the RF output signal.
Phase shift in degree = 360° × (MASH_SEED / PLL_DEN) × (P / CHDIV)
where
• P = 2 when VCO_PHASE_SYNC_EN = 1, otherwise P = 1 (1)
Table 2 and Equation 2 show an example.
Table 2. Phase Adjustment Setting
PARAMETER EXAMPLE VALUE
MASH_SEED 800
PLL_DEN 1000
CHDIV 32
VCO_PHASE_SYNC_EN 0
Phase shift = 360° × (800 / 1000) × (1 / 32) = 9° (2)
The user can write 800 to MASH_SEED 40 times to get the 360° phase shift.
Figure 7. Phase Adjustment Setting

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Figure 8. Phase Adjustment
3.2.2 Calibration-Free Automatic Ramping
The LMX2572LP supports linear frequency ramp without the need of VCO calibration in the middle of the
ramp. The output waveform is a continuous frequency sweep between the start and the end frequencies.
However, the frequency ramp range is limited. When using ramp, these parameters must be set
accordingly:
• OUT_FORCE = 1
• LD_DLY = 0
• PLL_DEN = 232 – 1
Table 3. Calibration-free Automatic Ramp Example
PARAMETER EXAMPLE VALUE
Ramping start frequency 4795 MHz
Ramping stop frequency 4805 MHz
Phase detector frequency 50 MHz
Ramp up / down time 200 µs
RAMP_LIMIT_HIGH 4995 MHz
RAMP_LIMIT_LOW 4595 MHz
This is a triangular ramp example. Ramp up is defined by RAMP0 while ramp down is defined by RAMP1.
RAMP_THRESH, RAMP_DLY_CNT, and RAMP_SCALE_COUNT are set to "don't care" because there is
no plan to trigger VCO calibration. RAMP_MANUAL = 0 means Automatic Ramping mode.
Set RAMP_EN = 1 to start ramping. Set RAMP_EN = 0 to turn off ramping.

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Figure 9. Calibration-Free Automatic Ramp Setting
Figure 10. Calibration-Free Automatic Ramp (CHDIV = 4)
3.2.3 Automatic Ramping
This ramping mode supports wider ramp frequency, but there are glitches in the middle of the ramp
because of the VCO calibrations that are required to ensure the continuity of the ramp.
Table 4. Automatic Ramp Example
PARAMETER EXAMPLE VALUE
Ramping start frequency 4740 MHz
Ramping stop frequency 4860 MHz
Phase detector frequency 50 MHz
Ramp up / down time 1000 µs
RAMP_LIMIT_HIGH 5060 MHz
RAMP_LIMIT_LOW 4540 MHz
fOSCin 100 MHz
CAL_CLK_DIV 0
RAMP_THRESH 40 MHz
Pause time for VCO calibration 500 µs

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Figure 11. Automatic Ramp Setting
Figure 12. Automatic Ramp (CHDIV = 4)
3.2.4 FSK Modulation
The LMX2572LP supports direct digital FSK modulation. The FSK SPI mode supports discrete 2-, 4-, or 8-
level FSK modulation while the FSK SPI FAST and FSK I2S modes support arbitrary level FSK
modulation. Table 5 shows a FSK SPI FAST mode example.
Table 5. FSK SPI FAST Mode Example
PARAMETER EXAMPLE VALUE
Phase detector frequency 100 MHz
CHDIV 8
PLL_DEN 8000000
FSK_DEV_SCALE 1
Frequency deviation ±648 Hz; ±1944 Hz