Texas Instruments TMS320C6000 DSP Manual

TMS320C6000
Programmer’s Guide
Literature Number: SPRU198E
October 2000
Printed on Recycled Paper

IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED
TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.
Copyright 2000, Texas Instruments Incorporated

iii Contents
Preface
Read This First
About This Manual
ThismanualisareferenceforprogrammingTMS320C6000digitalsignalpro-
cessor (DSP) devices.
Before you use this book, you should install your code generation and debug-
ging tools.
This book is organized in five major parts:
-PartI:Introductionincludesabriefdescriptionofthe’C6000architecture
and code development flow. It also includes a tutorial that introduces you
tothetoolsyouwilluseineachphaseofdevelopmentandanoptimization
checklist to help you achieve optimal performance from your code.
-Part II: C Code includes C code examples and discusses optimization
methods for the code. This information can help you choose the most
appropriate optimization techniques for your code.
-PartIII:Assembly Codedescribesthestructureofassemblycode.Itpro-
videsexamplesanddiscussesoptimizationsforassemblycode.Italsoin-
cludes a chapter on interrupt subroutines.
-Part IV: ’C64x Programming Techniques describes programming con-
siderations for the ’C64x.
-Part V: Appendix provides a summary of feedback solutions.

Related Documentation From Texas Instruments
iv
Related Documentation From Texas Instruments
Thefollowing books describe the TMS320C6000 devices andrelatedsupport
tools. To obtain a copy of any of these TI documents, call the Texas Instru-
mentsLiteratureResponseCenterat(800)477–8924.Whenordering,please
identify the book by its title and literature number.
TMS320C6000AssemblyLanguageToolsUser’sGuide (literaturenumber
SPRU186) describes the assembly language tools (assembler, linker,
and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging
directives for the ’C6000 generation of devices.
TMS320C6000 Optimizing C Compiler User’s Guide (literature number
SPRU187)describesthe’C6000Ccompilerandtheassemblyoptimizer.
ThisCcompileracceptsANSIstandardCsourcecodeandproducesas-
semblylanguagesourcecode forthe’C6000generationofdevices. The
assembly optimizer helps you optimize your assembly code.
TMS320C6000 CPU and Instruction Set Reference Guide (literature
number SPRU189) describes the ’C6000 CPU architecture, instruction
set, pipeline, and interrupts for these digital signal processors.
TMS320C6000 Peripherals Reference Guide (literature number SPRU190)
describes common peripherals available on the TMS320C6201/6701
digital signal processors. This book includes information on the internal
data and program memories, the external memory interface (EMIF), the
host port interface (HPI), multichannel buffered serial ports (McBSPs),
direct memory access (DMA), enhanced DMA (EDMA), expansion bus,
clocking and phase-locked loop (PLL), and the power-down modes.
TMS320C64x Technical Overview (SPRU395) The TMS320C64x technical
overview gives an introduction to the ’C64x digital signal processor, and
discussestheapplicationareasthatareenhancedbythe’C64xVelociTI.
TMS320 DSP Designer’s Notebook: Volume 1 (literature number
SPRT125) presents solutions to common design problems using ’C2x,
’C3x, ’C4x, ’C5x, and other TI DSPs.

Trademarks
v Read This First
Trademarks
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
VelociTI is a trademark of Texas Instruments Incorporated.
Windows and Windows NT are registered trademarks of Microsoft
Corporation.

Contents
vii
Contents
1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduces some features of the ’C6000 microprocessor and discusses the basic process for
creating code and understanding feedback.
1.1 TMS320C6000 Architecture 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 TMS320C6000 Pipeline 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Code Development Flow To Increase Performance 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Understanding Feedback 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.1 Stage 1: Qualify the Loop for Software Pipelining 1-9. . . . . . . . . . . . . . . . . . . . . . . .
1.4.2 Stage 2: Collect Loop Resource and Dependency Graph Information 1-11. . . . . .
1.4.3 Stage 3: Software Pipeline the Loop 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Compiler Optimization Tutorial 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Uses example code to walk you through the code development flow for the TMS320C6000.
2.1 Introduction: Simple C Tuning 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Lesson 1: Loop Carry Path From Memory Pointers 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Lesson 2: Balancing Resources With Dual-Data Paths 2-12. . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Lesson 3: Packed Data Optimization of Memory Bandwidth 2-18. . . . . . . . . . . . . . . . . . . . .
2.5 Lesson 4: Program Level Optimization 2-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Lesson 5: Writing Linear Assembly 2-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Optimizing C/C++ Code 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ExplainshowtomaximizeCperformancebyusingcompileroptions,intrinsics,andcodetrans-
formations.
3.1 Writing C/C++ Code 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 Tips on Data Types 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 Analyzing C Code Performance 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Compiling C/C++ Code 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Compiler Options 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 Memory Dependencies 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3 Performing Program-Level Optimization (–pm Option) 3-12. . . . . . . . . . . . . . . . . . .
3.3 Profiling Your Code 3-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 Using the Standalone Simulator (load6x) to Profile 3-13. . . . . . . . . . . . . . . . . . . . . .
3.4 Refining C/C++ Code 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 Using Intrinsics 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Using Word Access for Short Data 3-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.3 Software Pipelining 3-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
viii
4 Linking Issues 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Explains linker messages and how to use RTS functions.
4.1 How to Use Linker Error Messages 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 How to Find The Problem 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2 Executable Flag 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 How to Save On-Chip Memory by Placing RTS Off-Chip 4-6. . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1 How to Compile 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2 Must #include Header Files 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3 RTS Data 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.4 How to Link 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.5 Example Compiler Invocation 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.6 Header File Details 4-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.7 Changing RTS Data to near 4-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Structure of Assembly Code 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the structure of the assembly code, including labels, conditions, instructions, func-
tional units, operands, and comments.
5.1 Labels 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Parallel Bars 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Conditions 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Instructions 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 Functional Units 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 Operands 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7 Comments 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Optimizing Assembly Code via Linear Assembly 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes methods that help you develop more efficient assembly language programs.
6.1 Assembly Code 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Assembly Optimizer Options and Directives 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.1 The –on Option 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.2 The –mt Option and the .no_mdep Directive 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.3 The .mdep Directive 6-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.4 The .mptr Directive 6-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.5 The .trip Directive 6-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Writing Parallel Code 6-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.1 Dot Product C Code 6-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.2 Translating C Code to Linear Assembly 6-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.3 Linear Assembly Resource Allocation 6-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.4 Drawing a Dependency Graph 6-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.5 Nonparallel Versus Parallel Assembly Code 6-14. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.6 Comparing Performance 6-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
ix Contents
6.4 Using Word Access for Short Data and Doubleword Access for
Floating-Point Data 6-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.1 Unrolled Dot Product C Code 6-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.2 Translating C Code to Linear Assembly 6-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.3 Drawing a Dependency Graph 6-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.4 Linear Assembly Resource Allocation 6-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.5 Final Assembly 6-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.6 Comparing Performance 6-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5 Software Pipelining 6-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.1 Modulo Iteration Interval Scheduling 6-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.2 Using the Assembly Optimizer to Create Optimized Loops 6-39. . . . . . . . . . . . . . .
6.5.3 Final Assembly 6-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.4 Comparing Performance 6-57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 Modulo Scheduling of Multicycle Loops 6-58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.1 Weighted Vector Sum C Code 6-58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.2 Translating C Code to Linear Assembly 6-58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.3 Determining the Minimum Iteration Interval 6-59. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.4 Drawing a Dependency Graph 6-61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.5 Linear Assembly Resource Allocation 6-62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.6 Modulo Iteration Interval Scheduling 6-62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.7 Using the Assembly Optimizer for the Weighted Vector Sum 6-73. . . . . . . . . . . . .
6.6.8 Final Assembly 6-74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7 Loop Carry Paths 6-77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.1 IIR Filter C Code 6-77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.2 Translating C Code to Linear Assembly (Inner Loop) 6-78. . . . . . . . . . . . . . . . . . . .
6.7.3 Drawing a Dependency Graph 6-79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.4 Determining the Minimum Iteration Interval 6-80. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.5 Linear Assembly Resource Allocation 6-82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.6 Modulo Iteration Interval Scheduling 6-83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.7 Using the Assembly Optimizer for the IIR Filter 6-84. . . . . . . . . . . . . . . . . . . . . . . . .
6.7.8 Final Assembly 6-85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8 If-Then-Else Statements in a Loop 6-86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8.1 If-Then-Else C Code 6-86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8.2 Translating C Code to Linear Assembly 6-87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8.3 Drawing a Dependency Graph 6-88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8.4 Determining the Minimum Iteration Interval 6-89. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8.5 Linear Assembly Resource Allocation 6-90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8.6 Final Assembly 6-91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8.7 Comparing Performance 6-92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
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6.9 Loop Unrolling 6-94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.1 Unrolled If-Then-Else C Code 6-94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.2 Translating C Code to Linear Assembly 6-95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.3 Drawing a Dependency Graph 6-96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.4 Determining the Minimum Iteration Interval 6-97. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.5 Linear Assembly Resource Allocation 6-97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.6 Final Assembly 6-99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.7 Comparing Performance 6-100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10 Live-Too-Long Issues 6-101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.1 C Code With Live-Too-Long Problem 6-101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.2 Translating C Code to Linear Assembly 6-102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.3 Drawing a Dependency Graph 6-102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.4 Determining the Minimum Iteration Interval 6-104. . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.5 Linear Assembly Resource Allocation 6-106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.6 Final Assembly With Move Instructions 6-108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11 Redundant Load Elimination 6-110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11.1 FIR Filter C Code 6-110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11.2 Translating C Code to Linear Assembly 6-112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11.3 Drawing a Dependency Graph 6-113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11.4 Determining the Minimum Iteration Interval 6-114. . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11.5 Linear Assembly Resource Allocation 6-114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11.6 Final Assembly 6-115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12 Memory Banks 6-118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.1 FIR Filter Inner Loop 6-120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.2 Unrolled FIR Filter C Code 6-122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.3 Translating C Code to Linear Assembly 6-123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.4 Drawing a Dependency Graph 6-124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.5 Linear Assembly for Unrolled FIR Inner Loop With .mptr Directive 6-125. . . . . . . .
6.12.6 Linear Assembly Resource Allocation 6-127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.7 Determining the Minimum Iteration Interval 6-128. . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.8 Final Assembly 6-128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.9 Comparing Performance 6-128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13 Software Pipelining the Outer Loop 6-131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.1 Unrolled FIR Filter C Code 6-131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.2 Making the Outer Loop Parallel With the Inner Loop Epilog and Prolog 6-132. . .
6.13.3 Final Assembly 6-132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.4 Comparing Performance 6-135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14 Outer Loop Conditionally Executed With Inner Loop 6-136. . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.1 Unrolled FIR Filter C Code 6-136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.2 Translating C Code to Linear Assembly (Inner Loop) 6-137. . . . . . . . . . . . . . . . . . .
6.14.3 Translating C Code to Linear Assembly (Outer Loop) 6-138. . . . . . . . . . . . . . . . . . .
6.14.4 Unrolled FIR Filter C Code 6-138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.5 Translating C Code to Linear Assembly (Inner Loop) 6-140. . . . . . . . . . . . . . . . . . .
6.14.6 Translating C Code to Linear Assembly (Inner Loop and Outer Loop) 6-142. . . .
6.14.7 Determining the Minimum Iteration Interval 6-146. . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.8 Final Assembly 6-146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.9 Comparing Performance 6-149. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
xi Contents
7 Interrupts 7-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes interrupts from a software programming point of view.
7.1 Overview of Interrupts 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Single Assignment vs. Multiple Assignment 7-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Interruptible Loops 7-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 Interruptible Code Generation 7-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.1 Level 0 - Specified Code is Guaranteed to Not Be Interrupted 7-6. . . . . . . . . . . . .
7.4.2 Level 1 – Specified Code Interruptible at All Times 7-7. . . . . . . . . . . . . . . . . . . . . . .
7.4.3 Level 2 – Specified Code Interruptible Within Threshold Cycles 7-7. . . . . . . . . . . .
7.4.4 Getting the Most Performance Out of Interruptible Code 7-8. . . . . . . . . . . . . . . . . .
7.5 Interrupt Subroutines 7-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.1 ISR with the C/C++ Compiler 7-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.2 ISR with Hand-Coded Assembly 7-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.3 Nested Interrupts 7-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 ’C64x Programming Considerations 8-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes programming considerations for the ’C64x.
8.1 Overview of ’C64x Architectural Enhancements 8-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.1 Improved Scheduling Flexibility 8-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.2 Greater Memory Bandwidth 8-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.3 Support for Packed Data Types 8-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.4 Non-aligned Memory Accesses 8-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.5 Additional Specialized Instructions 8-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Packed-Data Processing on the ’C64x 8-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.1 Introduction to Packed Data Processing Techniques 8-4. . . . . . . . . . . . . . . . . . . . .
8.2.2 Packed Data Types 8-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.3 Storing Multiple Elements in a Single Register 8-5. . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.4 Packing and Unpacking Data 8-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.5 Optimizing for Packed Data Processing 8-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.6 Vectorizing With Packed Data Processing 8-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.7 Combining Multiple Operations in a Single Instruction 8-28. . . . . . . . . . . . . . . . . . .
8.2.8 Non-Aligned Memory Accesses 8-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.9 Performing Conditional Operations with Packed Data 8-40. . . . . . . . . . . . . . . . . . .
8.3 Linear Assembly Considerations 8-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.1 Using BDEC and BPOS in Linear Assembly 8-45. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.2 Avoiding Cross Path Stalls 8-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 FeedbackSolutions A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1 Loop Disqualification Messages A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2 Pipeline Failure Messages A-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.3 Investigative Feedback A-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures
xii
Figures
3–1 Dependency Graph for Vector Sum #1 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 Software-Pipelined Loop 3-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 Labels in Assembly Code 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Parallel Bars in Assembly Code 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 Conditions in Assembly Code 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 Instructions in Assembly Code 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–5 TMS320C6x Functional Units 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–6 Units in the Assembly Code 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–7 Operands in the Assembly Code 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–8 Operands in Instructions 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–9 Comments in Assembly Code 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Dependency Graph of Fixed-Point Dot Product 6-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 Dependency Graph of Floating-Point Dot Product 6-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–3 Dependency Graph of Fixed-Point Dot Product with Parallel Assembly 6-15. . . . . . . . . . . . . .
6–4 Dependency Graph of Floating-Point Dot Product with Parallel Assembly 6-17. . . . . . . . . . . .
6–5 Dependency Graph of Fixed-Point Dot Product With LDW 6-22. . . . . . . . . . . . . . . . . . . . . . . . .
6–6 Dependency Graph of Floating-Point Dot Product With LDDW 6-23. . . . . . . . . . . . . . . . . . . . .
6–7 Dependency Graph of Fixed-Point Dot Product With LDW
(Showing Functional Units) 6-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–8 Dependency Graph of Floating-Point Dot Product With LDDW
(Showing Functional Units) 6-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–9 Dependency Graph of Fixed-Point Dot Product With LDW
(Showing Functional Units) 6-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–10 Dependency Graph of Floating-Point Dot Product With LDDW
(Showing Functional Units) 6-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–11 Dependency Graph of Weighted Vector Sum 6-61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–12 Dependency Graph of Weighted Vector Sum (Showing Resource Conflict) 6-65. . . . . . . . . .
6–13 Dependency Graph of Weighted Vector Sum (With Resource Conflict Resolved) 6-68. . . . .
6–14 Dependency Graph of Weighted Vector Sum (Scheduling ci +1) 6-70. . . . . . . . . . . . . . . . . . . .
6–15 Dependency Graph of IIR Filter 6-79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–16 Dependency Graph of IIR Filter (With Smaller Loop Carry) 6-81. . . . . . . . . . . . . . . . . . . . . . . .
6–17 Dependency Graph of If-Then-Else Code 6-88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–18 Dependency Graph of If-Then-Else Code (Unrolled) 6-96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–19 Dependency Graph of Live-Too-Long Code 6-103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–20 Dependency Graph of Live-Too-Long Code (Split-Join Path Resolved) 6-106. . . . . . . . . . . . .
6–21 Dependency Graph of FIR Filter (With Redundant Load Elimination) 6-113. . . . . . . . . . . . . . .
6–22 4-Bank Interleaved Memory 6-118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures
xiii Contents
6–23 4-Bank Interleaved Memory With Two Memory Blocks 6-119. . . . . . . . . . . . . . . . . . . . . . . . . . .
6–24 Dependency Graph of FIR Filter (With Even and Odd Elements of
Each Array on Same Loop Cycle) 6-121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–25 Dependency Graph of FIR Filter (With No Memory Hits) 6-124. . . . . . . . . . . . . . . . . . . . . . . . . .
8–1 Four Bytes Packed Into a Single General Purpose Register 8-5. . . . . . . . . . . . . . . . . . . . . . . .
8–2 Two Half–Words Packed Into a Single General Purpose Register 8-6. . . . . . . . . . . . . . . . . . . .
8–3 Graphical Representation of _packXX2 Intrinsics 8-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–4 Graphical Representation of _spack2 8-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–5 Graphical Representation of 8–bit Packs (_packX4 and _spacku4) 8-11. . . . . . . . . . . . . . . . .
8–6 Graphical Representation of 8–bit Unpacks (_unpkXu4) 8-12. . . . . . . . . . . . . . . . . . . . . . . . . . .
8–7 Graphical Representation of (_shlmb, _shrmb, and _swap4) 8-13. . . . . . . . . . . . . . . . . . . . . . .
8–8 Graphical Representation of a Simple Vector Operation 8-14. . . . . . . . . . . . . . . . . . . . . . . . . . .
8–9 Graphical Representation of Dot Product 8-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–10 Graphical Representation of a Single Iteration of Vector Complex Multiply 8-17. . . . . . . . . . .
8–11 Array Access in Vector Sum by LDDW 8-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–12 Array Access in Vector Sum by STDW 8-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–13 Vector Addition 8-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–14 Graphical Representation of a Single Iteration of Vector Multiply 8-22. . . . . . . . . . . . . . . . . . .
8–15 Packed 16x16 Multiplies Using _mpy2 8-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–16 Fine Tuning Vector Multiply (shift > 16) 8-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–17 Fine Tuning Vector Multiply (shift < 16) 8-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–18 Graphical Representation of the _dotp2 Intrinsic c = _dotp2(b, a) 8-30. . . . . . . . . . . . . . . . . . .
8–19 The _dotpn2 Intrinsic Performing Real Portion of Complex Multiply 8-34. . . . . . . . . . . . . . . . .
8–20 _packlh2 and _dotp2 Working Together 8-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–21 Graphical Illustration of _cmpXX2 Intrinsics 8-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–22 Graphical Illustration of _cmpXX4 Intrinsics 8-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–23 Graphical Illustration of _xpnd2 Intrinsic 8-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–24 Graphical Illustration of _xpnd4 Intrinsic 8-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–25 C64x Data Cross Paths 8-50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables
xiv
Tables
1–1 Code Development Steps 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 Status Update: Tutorial example lesson_c lesson1_c 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Status Update: Tutorial example lesson_c lesson1_c lesson2_c 2-17. . . . . . . . . . . . . . . . . . . .
2–3 Status Update: Tutorial example lesson_c lesson1_c lesson2_c lesson3_c 2-22. . . . . . . . . .
2–4 Status Update: Tutorial example lesson_c lesson1_c lesson2_c lesson3_c 2-24. . . . . . . . . .
3–1 Compiler Options to Avoid on Performance Critical Code 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 Compiler Options for Performance 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Compiler Options That Slightly Degrade Performance and Improve Code Size 3-5. . . . . . . .
3–4 Compiler Options for Control Code 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 Compiler Options for Information 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–6 TMS320C6000 C/C++ Compiler Intrinsics 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 Command Line Options for RTS Calls 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 How _FAR_RTS is Defined in Linkage.h With –mr 4-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 Selected TMS320C6x Directives 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Functional Units and Operations Performed 5-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Comparison of Nonparallel and Parallel Assembly Code for
Fixed-Point Dot Product 6-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 Comparison of Nonparallel and Parallel Assembly Code for
Floating-Point Dot Product 6-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–3 Comparison of Fixed-Point Dot Product Code With Use of LDW 6-28. . . . . . . . . . . . . . . . . . . .
6–4 Comparison of Floating-Point Dot Product Code With Use of LDDW 6-28. . . . . . . . . . . . . . . .
6–5 Modulo Iteration Interval Scheduling Table for Fixed-Point Dot Product
(Before Software Pipelining) 6-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–6 Modulo Iteration Interval Scheduling Table for Floating-Point Dot Product
(Before Software Pipelining) 6-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–7 Modulo Iteration Interval Table for Fixed-Point Dot Product
(After Software Pipelining) 6-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–8 Modulo Iteration Interval Table for Floating-Point Dot Product
(After Software Pipelining) 6-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–9 Software Pipeline Accumulation Staggered Results Due to Three-Cycle Delay 6-38. . . . . .
6–10 Comparison of Fixed-Point Dot Product Code Examples 6-57. . . . . . . . . . . . . . . . . . . . . . . . . .
6–11 Comparison of Floating-Point Dot Product Code Examples 6-57. . . . . . . . . . . . . . . . . . . . . . . .
6–12 Modulo Iteration Interval Table for Weighted Vector Sum (2-Cycle Loop) 6-64. . . . . . . . . . . .
6–13 Modulo Iteration Interval Table for Weighted Vector Sum With SHR Instructions 6-66. . . . . .
6–14 Modulo Iteration Interval Table for Weighted Vector Sum (2-Cycle Loop) 6-69. . . . . . . . . . . .
6–15 Modulo Iteration Interval Table for Weighted Vector Sum (2-Cycle Loop) 6-72. . . . . . . . . . . .
6–16 Resource Table for IIR Filter 6-80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–17 Modulo Iteration Interval Table for IIR (4-Cycle Loop) 6-83. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables
xv Contents
6–18 Resource Table for If-Then-Else Code 6-89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–19 Comparison of If-Then-Else Code Examples 6-93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–20 Resource Table for Unrolled If-Then-Else Code 6-97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–21 Comparison of If-Then-Else Code Examples 6-100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–22 Resource Table for Live-Too-Long Code 6-104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–23 Resource Table for FIR Filter Code 6-114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–24 Resource Table for FIR Filter Code 6-128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–25 Comparison of FIR Filter Code 6-128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–26 Comparison of FIR Filter Code 6-135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–27 Resource Table for FIR Filter Code 6-146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–28 Comparison of FIR Filter Code 6-149. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–1 Packed data types 8-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–2 Supported Operations on Packed Data Types 8-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–3 Instructions for Manipulating Packed Data Types 8-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–4 Unpacking Packed 16-bit Quantities to 32-bit Values 8-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–5 Intrinsics Which Combine Multiple Operations in one Instruction 8-28. . . . . . . . . . . . . . . . . . . .
8–6 Comparison Between Aligned and Non–Aligned Memory Accesses 8-37. . . . . . . . . . . . . . . . .

Examples
xvi
Examples
1–1 Compiler and/or Assembly Optimizer Feedback 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 Stage 1 Feedback 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–3 Stage 2 Feedback 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–4 Stage 3 Feedback 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 Vector Summation of Two Weighted Vectors 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 lesson_c.c 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 Feedback From lesson_c.asm 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 lesson_c.asm 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 lesson1_c.c 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 lesson1_c.asm 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 lesson1_c.asm 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–8 lesson2_c.c 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–9 lesson2_c.asm 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–10 lesson2_c.asm 2-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–11 lesson3_c.c 2-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–12 lesson3_c.asm 2-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–13 Profile Statistics 2-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–14 Using the iircas4 Function in C 2-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–15 Software Pipelining Feedback From the iircas4 C Code 2-27. . . . . . . . . . . . . . . . . . . . . . . . . . .
2–16 Rewriting the iircas4 ( ) Function in Linear Assembly 2-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–17 Software Pipeline Feedback from Linear Assembly 2-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 Basic Vector Sum 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 Use of the Restrict Type Qualifier With Pointers 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Use of the Restrict Type Qualifier With Arrays 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 Incorrect Use of the restrict Keyword 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 Including the clock( ) Function 3-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–6 Saturated Add Without Intrinsics 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–7 Saturated Add With Intrinsics 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–8 Vector Sum With restrict Keywords, MUST_ITERATE Pragma, Word Reads 3-24. . . . . . . . .
3–9 Vector Sum With Non–aligned Word Accesses to Memory 3-25. . . . . . . . . . . . . . . . . . . . . . . . .
3–10 Vector Sum With restrict Keywords, MUST_ITERATE pragma,
and Word Reads (Generic Version) 3-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–11 Dot Product Using Intrinsics 3-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–12 FIR Filter—Original Form 3-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–13 FIR Filter—Optimized Form 3-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–14 Basic Float Dot Product 3-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Examples
xvii Contents
3–15 Float Dot Product Using Intrinsics 3-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–16 Float Dot Product With Peak Performance 3-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–17 Int Dot Product with Nonaligned Doubleword Reads 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–18 Using the Compiler to Generate a Dot Product With Word Accesses 3-34. . . . . . . . . . . . . . . .
3–19 Using the _nassert() Intrinsic to Generate Word Accesses for Vector Sum 3-35. . . . . . . . . . .
3–20 Using _nassert() Intrinsic to Generate Word Accesses for FIR Filter 3-36. . . . . . . . . . . . . . . .
3–21 Compiler Output From Example 3–20 3-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–22 Compiler Output From Example 3–13 3-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–23 Compiler Output From Example 3–12 3-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–24 Automatic Use of Word Accesses Without the _nassert Intrinsic 3-38. . . . . . . . . . . . . . . . . . . .
3–25 Trip Counters 3-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–26 Vector Sum With Three Memory Operations 3-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–27 Word-Aligned Vector Sum 3-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–28 Vector Sum Using const Keywords, MUST_ITERATE pragma,
Word Reads, and Loop Unrolling 3-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–29 FIR_Type2—Original Form 3-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–30 FIR_Type2—Inner Loop Completely Unrolled 3-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–31 Vector Sum 3-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–32 Use of If Statements in Float Collision Detection (Original Code) 3-50. . . . . . . . . . . . . . . . . . .
3–33 Use of If Statements in Float Collision Detection (Modified Code) 3-51. . . . . . . . . . . . . . . . . . .
4–1 Referencing Far Global Objects Defined in Other Files 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Linear Assembly Block Copy 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 Block copy With .mdep 6-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–3 Linear Assembly Dot Product 6-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–4 Linear Assembly Dot Product With .mptr 6-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–5 Fixed-Point Dot Product C Code 6-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–6 Floating-Point Dot Product C Code 6-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–7 List of Assembly Instructions for Fixed-Point Dot Product 6-10. . . . . . . . . . . . . . . . . . . . . . . . . .
6–8 List of Assembly Instructions for Floating-Point Dot Product 6-10. . . . . . . . . . . . . . . . . . . . . . .
6–9 Nonparallel Assembly Code for Fixed-Point Dot Product 6-14. . . . . . . . . . . . . . . . . . . . . . . . . .
6–10 Parallel Assembly Code for Fixed-Point Dot Product 6-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–11 Nonparallel Assembly Code for Floating-Point Dot Product 6-16. . . . . . . . . . . . . . . . . . . . . . . .
6–12 Parallel Assembly Code for Floating-Point Dot Product 6-17. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–13 Fixed-Point Dot Product C Code (Unrolled) 6-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–14 Floating-Point Dot Product C Code (Unrolled) 6-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–15 Linear Assembly for Fixed-Point Dot Product Inner Loop with LDW 6-20. . . . . . . . . . . . . . . . .
6–16 Linear Assembly for Floating-Point Dot Product Inner Loop with LDDW 6-21. . . . . . . . . . . . .
6–17 Linear Assembly for Fixed-Point Dot Product Inner Loop With LDW
(With Allocated Resources) 6-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–18 Linear Assembly for Floating-Point Dot Product Inner Loop With LDDW
(With Allocated Resources) 6-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–19 Assembly Code for Fixed-Point Dot Product With LDW
(Before Software Pipelining) 6-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–20 Assembly Code for Floating-Point Dot Product With LDDW
(Before Software Pipelining) 6-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Examples
xviii
6–21 Linear Assembly for Fixed-Point Dot Product Inner Loop
(With Conditional SUB Instruction) 6-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–22 Linear Assembly for Floating-Point Dot Product Inner Loop
(With Conditional SUB Instruction) 6-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–23 Pseudo-Code for Single-Cycle Accumulator With ADDSP 6-37. . . . . . . . . . . . . . . . . . . . . . . . .
6–24 Linear Assembly for Full Fixed-Point Dot Product 6-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–25 Linear Assembly for Full Floating-Point Dot Product 6-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–26 Assembly Code for Fixed-Point Dot Product (Software Pipelined) 6-42. . . . . . . . . . . . . . . . . .
6–27 Assembly Code for Floating-Point Dot Product (Software Pipelined) 6-43. . . . . . . . . . . . . . . .
6–28 Assembly Code for Fixed-Point Dot Product
(Software Pipelined With No Extraneous Loads) 6-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–29 Assembly Code for Floating-Point Dot Product
(Software Pipelined With No Extraneous Loads) 6-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–30 Assembly Code for Fixed-Point Dot Product
(Software Pipelined With Removal of Prolog and Epilog) 6-52. . . . . . . . . . . . . . . . . . . . . . . . . .
6–31 Assembly Code for Floating-Point Dot Product
(Software Pipelined With Removal of Prolog and Epilog) 6-53. . . . . . . . . . . . . . . . . . . . . . . . . .
6–32 Assembly Code for Fixed-Point Dot Product
(Software Pipelined With Smallest Code Size) 6-55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–33 Assembly Code for Floating-Point Dot Product
(Software Pipelined With Smallest Code Size) 6-56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–34 Weighted Vector Sum C Code 6-58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–35 Linear Assembly for Weighted Vector Sum Inner Loop 6-58. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–36 Weighted Vector Sum C Code (Unrolled) 6-59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–37 Linear Assembly for Weighted Vector Sum Using LDW 6-60. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–38 Linear Assembly for Weighted Vector Sum With Resources Allocated 6-62. . . . . . . . . . . . . . .
6–39 Linear Assembly for Weighted Vector Sum 6-73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–40 Assembly Code for Weighted Vector Sum 6-75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–41 IIR Filter C Code 6-77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–42 Linear Assembly for IIR Inner Loop 6-78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–43 Linear Assembly for IIR Inner Loop With Reduced Loop Carry Path 6-82. . . . . . . . . . . . . . . . .
6–44 Linear Assembly for IIR Inner Loop (With Allocated Resources) 6-82. . . . . . . . . . . . . . . . . . . .
6–45 Linear Assembly for IIR Filter 6-84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–46 Assembly Code for IIR Filter 6-85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–47 If-Then-Else C Code 6-86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–48 Linear Assembly for If-Then-Else Inner Loop 6-87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–49 Linear Assembly for Full If-Then-Else Code 6-90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–50 Assembly Code for If-Then-Else 6-91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–51 Assembly Code for If-Then-Else With Loop Count Greater Than 3 6-92. . . . . . . . . . . . . . . . . .
6–52 If-Then-Else C Code (Unrolled) 6-94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–53 Linear Assembly for Unrolled If-Then-Else Inner Loop 6-95. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–54 Linear Assembly for Full Unrolled If-Then-Else Code 6-98. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–55 Assembly Code for Unrolled If-Then-Else 6-99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–56 Live-Too-Long C Code 6-101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–57 Linear Assembly for Live-Too-Long Inner Loop 6-102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Examples
xix Contents
6–58 Linear Assembly for Full Live-Too-Long Code 6-107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–59 Assembly Code for Live-Too-Long With Move Instructions 6-108. . . . . . . . . . . . . . . . . . . . . . .
6–60 FIR Filter C Code 6-110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–61 FIR Filter C Code With Redundant Load Elimination 6-111. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–62 Linear Assembly for FIR Inner Loop 6-112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–63 Linear Assembly for Full FIR Code 6-114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–64 Final Assembly Code for FIR Filter With Redundant Load Elimination 6-116. . . . . . . . . . . . . .
6–65 Final Assembly Code for Inner Loop of FIR Filter 6-120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–66 FIR Filter C Code (Unrolled) 6-122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–67 Linear Assembly for Unrolled FIR Inner Loop 6-123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–68 Linear Assembly for Full Unrolled FIR Filter 6-125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–69 Final Assembly Code for FIR Filter With Redundant Load Elimination
and No Memory Hits 6-129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–70 Unrolled FIR Filter C Code 6-131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–71 Final Assembly Code for FIR Filter With Redundant Load Elimination
and No Memory Hits With Outer Loop Software-Pipelined 6-133. . . . . . . . . . . . . . . . . . . . . . . .
6–72 Unrolled FIR Filter C Code 6-136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–73 Linear Assembly for Unrolled FIR Inner Loop 6-137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–74 Linear Assembly for FIR Outer Loop 6-138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–75 Unrolled FIR Filter C Code 6-139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–76 Linear Assembly for FIR With Outer Loop
Conditionally Executed With Inner Loop 6-141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–77 Linear Assembly for FIR With Outer Loop
Conditionally Executed With Inner Loop (With Functional Units) 6-143. . . . . . . . . . . . . . . . . . .
6–78 Final Assembly Code for FIR Filter 6-147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–1 Code With Multiple Assignment of A1 7-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–2 Code Using Single Assignment 7-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–3 Dot Product With MUST_ITERATE Pragma Guaranteeing Minimum Trip Count 7-8. . . . . . .
7–4 Dot Product With _nassert Guaranteeing Trip Count Range 7-9. . . . . . . . . . . . . . . . . . . . . . . .
7–5 Dot Product With MUST_ITERATE Pragma Guaranteeing Trip Count Range
and Factor of 2 7-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–6 Dot Product With MUST_ITERATE Pragma Guaranteeing Trip Count Range
and Factor of 4 7-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–7 Hand-Coded Assembly ISR 7-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–8 Hand-Coded Assembly ISR Allowing Nesting of Interrupts 7-14. . . . . . . . . . . . . . . . . . . . . . . . .
8–1 Vector Sum 8-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–2 Vector Multiply 8-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–3 Dot Product 8-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–4 Vector Complex Multiply 8-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–5 Vectorization: Using LDDW and STDW in Vector Sum 8-19. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–6 Vector Addition (Complete) 8-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–7 Using LDDW and STDW in Vector Multiply 8-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–8 Using _mpy2() and _pack2() to Perform the Vector Multiply 8-24. . . . . . . . . . . . . . . . . . . . . . . .
8–9 Vectorized Form of the Dot Product Kernel 8-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–10 Vectorized Form of the Dot Product Kernel 8-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Examples
xx
8–11 Final Assembly Code for Dot–Product Kernel’s Inner Loop 8-31. . . . . . . . . . . . . . . . . . . . . . . .
8–12 Vectorized form of the Vector Complex Multiply Kernel 8-33. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–13 Vectorized form of the Vector Complex Multiply 8-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–14 Non–aligned Memory Access With _mem4 and _memd8 8-38. . . . . . . . . . . . . . . . . . . . . . . . . .
8–15 Vector Sum Modified to use Non–Aligned Memory Accesses 8-38. . . . . . . . . . . . . . . . . . . . . .
8–16 Clear Below Threshold Kernel 8-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–17 Clear Below Threshold Kernel, Using _cmpgtu4 and _xpnd4 Intrinsics 8-44. . . . . . . . . . . . . .
8–18 Loop Trip Count in C 8-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–19 Loop Trip Count in Linear Assembly without BDEC 8-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–20 Loop Trip Count Using BDEC 8-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–21 Loop Tip Count Using BDEC With Extra Loop Iterations 8-47. . . . . . . . . . . . . . . . . . . . . . . . . . .
8–22 Using the .call Directive in Linear Assembly 8-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–23 Compiler Output Using ADDKPC 8-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–24 Avoiding Cross Path Stalls: Weighted Vector Sum Example 8-51. . . . . . . . . . . . . . . . . . . . . . .
8–25 Avoiding Cross Path Stalls: Partitioned Linear Assembly 8-52. . . . . . . . . . . . . . . . . . . . . . . . . .
8–26 Avoiding Cross Path Stalls: Vector Sum Loop Kernel 8-53. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–27 Avoiding Cross Path Stalls: Assembly Output Generated for Weighted Vector
Sum Loop Kernel 8-54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1
Introduction
Thischapter introduces some features ofthe ’C6000 microprocessor and dis-
cusses the basic process for creating code and understanding feedback. Any
referenceto’C6000pertainstothe’C62x(fixed-point),’C64x(fixed-point),and
the ’C67x (floating-point) devices. Though most of the examples shown are
fixed-point specific, all techniques are applicable to each device.
Topic Page
1.1 TMS320C6000 Architecture 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 TMS320C6000 Pipeline 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Code Development Flow to Increase Performance 1-3. . . . . . . . . . . . . . .
1.4 Understanding Feedback 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1