Texas Instruments TPIC74100EVM User manual

User’s Guide
TPIC74100EVM User's Guide
Table of Contents
1 Introduction.............................................................................................................................................................................2
2 Setup........................................................................................................................................................................................3
2.1 Input/Output Connector Description...................................................................................................................................3
2.2 Setup..................................................................................................................................................................................4
2.3 Operation........................................................................................................................................................................... 4
3 Board Layout...........................................................................................................................................................................6
4 Schematic................................................................................................................................................................................8
5 Revision History......................................................................................................................................................................9
List of Figures
Figure 2-1. Slew Rate Jumper Settings....................................................................................................................................... 3
Figure 2-2. Low Power Mode Jumper Settings............................................................................................................................4
Figure 2-3. Enable Jumper Settings............................................................................................................................................ 4
Figure 2-4. 5Vg Regulated Output Jumper Settings....................................................................................................................4
Figure 2-5. Low Pass Filter Inductor Bypass Jumper Settings.................................................................................................... 4
Figure 3-1. Top Assembly Layer.................................................................................................................................................. 6
Figure 3-2. Bottom Assembly Layer (viewed from bottom)..........................................................................................................6
Figure 3-3. Top Layer Routing..................................................................................................................................................... 7
Figure 3-4. Bottom Layer Routing (viewed from bottom).............................................................................................................7
Figure 4-1. TPIC74100EVM Schematic.......................................................................................................................................8
List of Tables
Table 1-1. Device and Package Configurations...........................................................................................................................2
Table 4-1. TPIC74100EVM Bill of Materials.................................................................................................................................9
Trademarks
PowerPAD™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
www.ti.com Table of Contents
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TPIC74100EVM User's Guide 1
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1 Introduction
The Texas Instruments TPIC74100EVM evaluation module (EVM) helps designers evaluate the operation and
performance of the TPIC74100 Switch Mode Power Supply – Buck Regulator. The EVM contains one DC/DC
converter (See Table 1).
Table 1-1. Device and Package Configurations
CONVERTER IC PACKAGE
U1 TPIC74100QPWPRQ1 PWP-20
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2 Setup
This section describes the jumpers and connectors on the EVM as well and how to properly connect, set up, and
use the TPIC74100EVM.
2.1 Input/Output Connector Description
J1 – VBAT is the power input terminal for the converter. The terminal provides power (Vbat).
J2 – GND is the ground terminal for the EVM.
J3 – 5Vg is the power output terminal for the 5Vg regulator output.
J4 – VOUT is the regulated output voltage for the converter.
J5 – GND is a ground terminal for the EVM.
JP1, JP2 – SCR1, SCR0 are jumpers used to set the slew rate of the switching transistor for the L1 terminal
switch pin. Jumpers allow the slew rate to be set to four set points.
SCR1
slow
SCR0
1
0
SCR1
medium -slow
SCR0
1
0
SCR1
medium-fast
SCR0
1
0
SCR1
fast
SCR0
1
0
Figure 2-1. Slew Rate Jumper Settings
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JP3 – LPM is the jumper used to enable Low Power Mode. The jumper allows LPM to be enabled or disabled.
The device will operate in Normal mode when LPM is disabled.
LPM
disabled
LPM
enabled
1
0
1
0
Figure 2-2. Low Power Mode Jumper Settings
JP4 – Enable is the jumper used to enable the converter. The converter is enabled when the Enable is high and
disabled when low. The jumper placement allows the converter to be enabled or disabled.
EN
disabled
EN
enabled
1
0
1
0
Figure 2-3. Enable Jumper Settings
JP5 – 5VgEN is the jumper used to enable switched 5V regulated output. The output is enabled when the
Enable is high and disabled when low. The jumper placement allows the converter to be enabled or disabled.
5Vg
disabled
5Vg
enabled
1
0
1
0
Figure 2-4. 5Vg Regulated Output Jumper Settings
JP6 – Bypass is the jumper used to bypass the low pass filter inductor on the power supply input to the device.
This allows the user to remove the filter from the circuit. The jumper placement allows the inductor to be active or
shorted.
BYPASS
active
BYPASS
shorted
Figure 2-5. Low Pass Filter Inductor Bypass Jumper Settings
2.2 Setup
The input voltage range for the converter is 1.5 volts to 40 volts. The input voltage must be at least 5 V during
start up.
2.3 Operation
For proper operation of the TPIC74100, JP1, JP2, JP3, JP4, JP5, and JP6 should be properly configured. The
recommended setting, using shorting blocks:
JP1 and JP2 to Fast
JP3 to Enabled
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JP4 to Enabled
JP5 to Enabled, if 5Vg is used
JP6 to Shorted
In this configuration, the device powers up when power is applied. JP1, JP2 SCR0, SCR1 select how switch pin
slew rate is set: slow, medium-slow, medium-fast, or fast. JP3 LPM selects how Low Power Mode is set: Enabled
or Disabled. JP4 EN turns the device on or off. JP5 5Vg turns the regulated 5-V output on or off. JP6 Bypass
disables the low-pass filter located on the input supply to the device.
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3 Board Layout
Figure 6, Figure 7, Figure 8, and Figure 9 show the board layout for the TPIC74100EVM PWB. The EVM offers
resistors, capacitors, and jumpers to program the switch pin slew rate and regulator turn-on Delay. Jumpers are
also provided to enable the device and to enable the low-power mode option.
The TPIC74100 offers high efficiency but does dissipate power. The PowerPAD™ package offers an exposed
thermal pad to enhance thermal performance. This must be soldered to the copper landing on the PCB for
optimal performance. The PCB provides 1-oz copper planes on the top and bottom to dissipate heat.
Figure 3-1. Top Assembly Layer
Figure 3-2. Bottom Assembly Layer (viewed from bottom)
Board Layout www.ti.com
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Figure 3-3. Top Layer Routing
Figure 3-4. Bottom Layer Routing (viewed from bottom)
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4 Schematic
GND
C2
C7
GND
D2
Aout 13
L1
5
Cboot2
25Vg_ENABLE 19
Rmod 15
GND 16
L2
7
PGND
6
Vdriver
4
Cboot1
3
SCR1
1
ENABLE 18
Vlogic 17
SCR0 20
5Vg
9
Ain
10
Vout
8
RESET 12
PAD
1
2
REST 14
TPIC74100PWP
CLP 11
2
1
L1
C1
GND
GND
GND
C3
GND
R1
GND
C4
GND
R3 R4
GND
C10
VOUT
1
JP1
D1
2 1
L2
R2 R5
GND
VDRIVER
AIN
VBAT
VDRIVER
AIN
VLOGIC
SCR1
SCR1
GND
1
JP2
VLOGIC
SCR0
SCR0
VLOGIC
C5
GND
VOUT
VOUT
GND
ENABLE
VDRIVER
ENABLE
5VG_ENABLE
GND
1
JP5
5VG_ENABLE
VDRIVER
C9
GND
JP6
5Vg
2 1
+C6
2 1
+C8
GND
REST AOUT RESET
GND
GND
GND
GND
GND
1
JP3
VLOGIC
LPM
LPM
1
JP4
Figure 4-1. TPIC74100EVM Schematic
Schematic www.ti.com
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Table 4-1. TPIC74100EVM Bill of Materials
COUNT REF
DES DESCRIPTION SIZE MFR PART NO.
2 C1, C2 Capacitor, ceramic, 4.7nF,
50V, 10% 0603 muRata GRM188R71H472KA01B
1 C3 Capacitor, ceramic, 470nF,
16V, 10% 0603 muRata GRM188R71C474KA88B
2 C4, C7 Capacitor, ceramic, 100nF,
16V, 10% 0603 muRata GRM188R71C104KA01J
1 C5 Capacitor, ceramic, 100nF,
50V, 10% 1206 muRata GCM319R71H104KA37B
1 C6 Capacitor, electrolytic, 470uF,
50V, 10% 10mm Panasonic EEU-FC1H471L
1 C8 Capacitor, tantalum, 47uF,
16V, 20% 6032 Kyocera AVX TPSD476K016T0100V
1 C9 Capacitor, ceramic, 1uF, 16V,
10% 0603 muRata GRM188R71C105KA12B
1 C10 Capacitor, ceramic, 10nF, 16V,
10% 0603 muRata GRM188R71C103KA01B
2 D1, D2 Diode, Schottky, 3A, 100V SMC IR 30BQ100
5 J1, J2, J3, J4, J5 Test point, 42-mil 0.042 Std Std
5JP1, JP2, JP3, JP4,
JP5
Header, 3-pin, 100-mil
spacing, (36-pin strip) 0.100 x 3 Sullins PTC36CAAN
1 JP6 Header, 2-pin, 100-mil
spacing, (36-pin strip) 0.100 x 2 Sullins PTC36CAAN
2 L1, L2 Inductor, SMT, 33-uH, 4.34,
54.9-mΩ 12.3mm x 12.3mm Coilcraft MSS1260T-333
1 R1 Resistor, chip, 12.1-kΩ,
1/16W, 1% 0603 Std Std
1 R2 Resistor, chip, 68.1-kΩ,
1/16W, 1% 0603 Std Std
2 R3, R4 Resistor, chip, 20-kΩ, 1/16W,
1% 0603 Std Std
1 R5 Resistor, chip, 33.2-kΩ,
1/16W, 1% 0603 Std Std
1 U1 IC, TPIC74100QPWPRQ1 TI TPIC74100QPWP
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (September 2008) to Revision A (October 2022) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................2
• Layout figures updated to match physical board Rev. E.....................................................................................6
• Updated BoM to match components of board Rev. E.........................................................................................8
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TPIC74100EVM User's Guide 9
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STANDARD TERMS FOR EVALUATION MODULES
1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
WARNING
Evaluation Kits are intended solely for use by technically qualified,
professional electronics experts who are familiar with the dangers
and application risks associated with handling electrical mechanical
components, systems, and subsystems.
User shall operate the Evaluation Kit within TI’s recommended
guidelines and any applicable legal or environmental requirements
as well as reasonable and customary safeguards. Failure to set up
and/or operate the Evaluation Kit within TI’s recommended
guidelines may result in personal injury or death or property
damage. Proper set up entails following TI’s instructions for
electrical ratings of interface circuits such as input, output and
electrical loads.
NOTE:
EXPOSURE TO ELECTROSTATIC DISCHARGE (ESD) MAY CAUSE DEGREDATION OR FAILURE OF THE EVALUATION
KIT; TI RECOMMENDS STORAGE OF THE EVALUATION KIT IN A PROTECTIVE ESD BAG.