Texas Instruments TPS546B24AEVM-2PH User manual

User’s Guide
TPS546B24A 2-Phase SWIFT™ Step-Down Converter
Evaluation Module User's Guide
ABSTRACT
The TPS546B24AEVM-2PH evaluation module (EVM) is a two-phase buck converter with two TPS546B24A
devices. The TPS546B24A device is a stackable synchronous buck with PMBus interface that can operate from
a nominal 2.95-V to 18-V supply. The device allows programming and monitoring through the interface.
Two TPS546B24A devices are configured as two-phase buck converter in factory default. Output current is
evenly distributed in the two devices; both the negative and positive output terminals are connected together.
Table of Contents
1 Description.............................................................................................................................................................................. 4
1.1 Before You Begin............................................................................................................................................................... 4
1.2 Typical Applications............................................................................................................................................................4
1.3 Features............................................................................................................................................................................. 5
2 Electrical Performance Specifications................................................................................................................................. 5
3 Schematic................................................................................................................................................................................6
4 Test Setup................................................................................................................................................................................9
4.1 Test and Configuration Software........................................................................................................................................ 9
4.2 Test Equipment.................................................................................................................................................................. 9
4.3 Tip and Barrel Measurement............................................................................................................................................10
4.4 List of Test Points, Jumpers, and Connectors..................................................................................................................10
4.5 Evaluating Single Phase Operation................................................................................................................................. 13
4.6 Evaluating Split Rail Input................................................................................................................................................ 13
4.7 Configuring EVM to Overdrive VDD5...............................................................................................................................13
5 EVM Configuration Using the Fusion GUI..........................................................................................................................14
5.1 Configuration Procedure.................................................................................................................................................. 14
6 Test Procedure......................................................................................................................................................................14
6.1 Line and Load Regulation and Efficiency Measurement Procedure................................................................................ 14
6.2 Efficiency Measurement Test Points................................................................................................................................ 15
6.3 Control Loop Gain and Phase Measurement Procedure................................................................................................. 16
7 Performance Data and Typical Characteristic Curves...................................................................................................... 17
7.1 Efficiency..........................................................................................................................................................................17
7.2 Load and Line Regulation (Measured Between TP22 and TP25)....................................................................................17
7.3 Transient Response......................................................................................................................................................... 18
7.4 Control Loop Bode Plot.................................................................................................................................................... 18
7.5 Output Ripple................................................................................................................................................................... 19
7.6 Power MOSFET Drain-Source Voltage............................................................................................................................20
7.7 Control On........................................................................................................................................................................21
7.8 Control Off........................................................................................................................................................................22
7.9 Control On with Pre-Biased Output..................................................................................................................................23
7.10 Current Sharing Between Two Phases.......................................................................................................................... 23
7.11 Thermal Image............................................................................................................................................................... 24
8 EVM Assembly Drawing and PCB Layout.......................................................................................................................... 25
9 Bill of Materials..................................................................................................................................................................... 28
10 Using the Fusion GUI......................................................................................................................................................... 31
10.1 Opening the Fusion GUI................................................................................................................................................ 31
10.2 General Settings............................................................................................................................................................ 32
10.3 Changing ON_OFF_CONFIG........................................................................................................................................ 33
10.4 Pop-up for Some Commands While Conversion is Enabled..........................................................................................34
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10.5 SMBALERT# Mask........................................................................................................................................................ 35
10.6 Device Info..................................................................................................................................................................... 36
10.7 Phase Commands..........................................................................................................................................................37
10.8 All Config........................................................................................................................................................................38
10.9 Pin Strapping..................................................................................................................................................................39
10.10 Monitor......................................................................................................................................................................... 40
10.11 Status........................................................................................................................................................................... 41
11 Revision History..................................................................................................................................................................41
List of Figures
Figure 3-1. TPS546B24AEVM-2PH Schematic Page 1.............................................................................................................. 6
Figure 3-2. TPS546B24AEVM-2PH Schematic Page 2 (U1_P1 Loop Controller)...................................................................... 7
Figure 3-3. TPS546B24AEVM-2PH Schematic Page 3 (U1_P2 Loop Follower)........................................................................ 8
Figure 4-1. Tip and Barrel Measurement...................................................................................................................................10
Figure 7-1. Efficiency, VOUT Measured Using TP13, TP16, TP26, and TP30............................................................................17
Figure 7-2. Efficiency, VOUT Measured Using TP22 and TP25..................................................................................................17
Figure 7-3. Load Regulation...................................................................................................................................................... 17
Figure 7-4. Line Regulation....................................................................................................................................................... 17
Figure 7-5. Transient Response................................................................................................................................................ 18
Figure 7-6. Bode Plot at 0.8-V Output at 12 VIN, 20-A Load......................................................................................................18
Figure 7-7. Output Ripple With 0-A Load...................................................................................................................................19
Figure 7-8. Output Ripple With 40-A Load.................................................................................................................................19
Figure 7-9. Low-Side MOSFET VDS ......................................................................................................................................... 20
Figure 7-10. High-Side MOSFET VDS .......................................................................................................................................20
Figure 7-11. Start-Up From Control, 0-A Load...........................................................................................................................21
Figure 7-12. Start-Up From Control, 40-A CC Load.................................................................................................................. 21
Figure 7-13. Shutdown From Control, 0-A Load........................................................................................................................22
Figure 7-14. Shutdown From Control, 20-A CC Load................................................................................................................22
Figure 7-15. Start-Up From Control With Pre-Biased Output.................................................................................................... 23
Figure 7-16. Inductor Current and Switch Node Waveform, 40-A Load.................................................................................... 23
Figure 7-17. Thermal Image...................................................................................................................................................... 24
Figure 8-1. TPS546B24AEVM-2PH 3D (Top View)................................................................................................................... 25
Figure 8-2. TPS546B24AEVM-2PH 3D (Bottom View)..............................................................................................................25
Figure 8-3. TPS546B24AEVM-2PH Top Side Component View (Top View)............................................................................. 25
Figure 8-4. TPS546B24AEVM-2PH Bottom Side Component View (Bottom View).................................................................. 25
Figure 8-5. TPS546B24AEVM-2PH Top Copper (Top View)..................................................................................................... 26
Figure 8-6. TPS546B24AEVM-2PH Internal Layer 1 (Top View)...............................................................................................26
Figure 8-7. TPS546B24AEVM-2PH Internal Layer 2 (Top View)...............................................................................................26
Figure 8-8. TPS546B24AEVM-2PH Internal Layer 3 (Top View)...............................................................................................26
Figure 8-9. TPS546B24AEVM-2PH Internal Layer 4 (Top View)...............................................................................................27
Figure 8-10. TPS546B24AEVM-2PH Internal Layer 5 (Top View).............................................................................................27
Figure 8-11. TPS546B24AEVM-2PH Internal Layer 6 (Top View)............................................................................................. 27
Figure 8-12. TPS546B24AEVM-2PH Internal Bottom Layer (Top View)................................................................................... 27
Figure 10-1. Select Device Scanning Mode.............................................................................................................................. 31
Figure 10-2. General Settings....................................................................................................................................................32
Figure 10-3. Configure – ON_OFF_CONFIG............................................................................................................................ 33
Figure 10-4. Pop-up When Trying to Change FREQUENCY_SWITCH With Conversion Enabled...........................................34
Figure 10-5. Configure – SMBALERT # Mask...........................................................................................................................35
Figure 10-6. Configure – Device Info.........................................................................................................................................36
Figure 10-7. Phase Commands.................................................................................................................................................37
Figure 10-8. Configure – All Config........................................................................................................................................... 38
Figure 10-9. Configure – Pin Strapping..................................................................................................................................... 39
Figure 10-10. Monitor Screen.................................................................................................................................................... 40
Figure 10-11. Status Screen...................................................................................................................................................... 41
List of Tables
Table 2-1. TPS546B24AEVM-2PH Electrical Performance Specifications..................................................................................5
Table 4-1. Test Point Functions..................................................................................................................................................10
Table 4-2. Jumpers.....................................................................................................................................................................11
Table 4-3. JP2_P1 and JP2_P2 Selections................................................................................................................................11
Table 4-4. JP7_P1 and JP7_P2 Selections................................................................................................................................11
Table 4-5. Connector Functions.................................................................................................................................................12
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Table 6-1. Test Points for Efficiency Measurements.................................................................................................................. 15
Table 6-2. Test Points for Better Efficiency Measurements........................................................................................................15
Table 6-3. List of Test Points for Loop Response Measurements..............................................................................................16
Table 9-1. TPS546B24AEVM-2PH Bill of Materials...................................................................................................................28
Trademarks
All trademarks are the property of their respective owners.
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1 Description
The TPS546B24AEVM-2PH is a two-phase buck design stacking two TPS546B24A devices. It designed
for a nominal 12-V bus and to produce a regulated 0.8-V output at up to 40 A of load current. The
TPS546B24AEVM-2PH is designed to demonstrate stacking operation of the TPS546B24A in a two-phase, low-
output voltage application while providing a number of test points to evaluate the performance of the devices.
The TPS546B24AEVM-2PH can be modified to single-phase buck converters by changing the components
assembled. See Section 4.3 for more information on single-phase configuration.
1.1 Before You Begin
The following warnings and cautions are noted for the safety of anyone using or working close to the
TPS546B24AEVM-2PH. Observe all safety precautions.
Warning The TPS546B24AEVM-2PH circuit module may become hot during operation due
to dissipation of heat. Avoid contact with the board. Follow all applicable safety
procedures applicable to your laboratory.
!
Caution Do not leave the EVM powered when unattended.
WARNING
The circuit module has signal traces, components, and component leads on the bottom of the board.
This may result in exposed voltages, hot surfaces, or sharp edges. Do not reach under the board
during operation.
CAUTION
The circuit module may be damaged by over temperature. To avoid damage, monitor the
temperature during evaluation and provide cooling, as needed, for your system environment.
CAUTION
Some power supplies can be damaged by application of external voltages. If using more than
one power supply, check the equipment requirements and use blocking diodes or other isolation
techniques, as needed, to prevent damage to the equipment.
CAUTION
The communication interface is not isolated on the EVM. Be sure no ground potential exists between
the computer and the EVM. Also be aware that the computer is referenced to the battery potential of
the EVM.
1.2 Typical Applications
The TPS546B24A device is designed for the following applications:
• High-density power solutions
• Wireless infrastructure
• Switcher
• Router network
• Server
• Storage
• Smart power systems
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1.3 Features
This EVM has the following features:
• Regulated 0.8-V output up to 40-ADC steady-state output current
• The output voltage is marginable and trimmable using the PMBus interface
– Programmable UVLO, soft-start, and enable via the PMBus interface
– Programmable overcurrent warning and fault limits and programmable response to faults through the
PMBus interface
– Programmable overvoltage and undervoltage warning and fault limits and programmable response to
faults through the PMBus interface
– Programmable turn-on and turn-off delays
• Convenient test points for probing critical waveforms
2 Electrical Performance Specifications
Table 2-1 lists the electrical performance specifications in room temperature (20 to 25°C). Characteristics are
given for an input voltage of VIN = 12 V, unless otherwise specified.
Table 2-1. TPS546B24AEVM-2PH Electrical Performance Specifications
Parameter Test Conditions MIN TYP MAX Unit
Input Characteristics
Input voltage range, VIN 5 12 18 V
Full load input current IOUT = 40 A 3.1 A
Full load input current VIN = 5 V, IOUT = 40 A 7.3 A
No load input current IOUT = 0 A, switching enabled 100 mA
Enable switching threshold Set by default resistor divider, JP2_P1 and JP2_P2 pins
3 and 4 shorted 5.26 V
Disable switching threshold Set by default resistor divider, JP2_P1 and JP2_P2 pins
3 and 4 shorted 4.75 V
Output Characteristics
Output voltage, VOUT 0.8 V
Output load current, IOUT 0 40 A
Output voltage regulation Line regulation: VIN = 5 V to 18 V 0.1%
Load regulation: IOUT = 0 A to 40 A 0.1%
Output voltage ripple IOUT = 40 A 9 mVpp
Output voltage undershoot IOUT = 10-A to 30-A step at 10 A/µs 100 mV
Output voltage overshoot IOUT = 30-A to 10-A step at 10 A/µs 100 mV
Output overcurrent fault threshold
Phase current limit setting of U1_P1 programmed by
MSEL2 26 A
Phase current limit setting of U1_P2 programmed by
MSEL2 26 A
Systems Characteristics
Switching frequency Programmed by MSEL1 550 kHz
Full load efficiency, VOUT (1) IOUT = 40 A 86.8%
Operating case temperature IOUT = 40 A, 10 minute soak 50 °C
Loop bandwidth IOUT = 20 A 60 kHz
Phase margin 56 °
PMBus Interface and Pin-Strapping
U1_P1 PMBus address Programmed by NVM and ADRSEL 36 Decimal
U1_P1 Voltage reference Default setting of VOUT_COMMAND programmed by
VSEL 800 mV
U1_P1 Soft-start time (TON_RISE) Default setting of TON_RISE programmed by MSEL2 3 ms
(1) The efficiency is measured using the test points listed in Table 6-2 to minimize the effect of DC drops caused by on-board copper
traces.
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3 Schematic
Figure 3-1 through Figure 3-3 illustrate the TPS546B24AEVM-2PH schematics.
SNS+
SMBALT
PM_CLK
PM_DAT
BC_CLK
BC_DAT
VIN
GND
SNS-
SW
VSH
SYNC
CNTL
S_VIN
EXT_5V
PG_S
P1
BSR104E1_Room.SchDoc
SNS+
SMBALT
PM_CLK
PM_DAT
BC_CLK
BC_DAT
VIN
GND
SNS-
SW
VSH
SYNC
CNTL
S_VIN
EXT_5V
PG_S
P2
BSR104E1_Room.SchDoc
1 2
3 4
5 6
7 8
9 10
J2
PMBus
GND
Green
2 1
LED1
1.00k
R28
CLK
CNTL
DATA SMBALRT
47uF
C42
DNP
47uF
C38
DNP
47uF
C43
DNP
47uF
C44
DNP
47uF
C40
DNP
47uF
C39
DNP
47uF
C41
DNP
47uF
C35 220uF
C47
220uF
C48
47uF
C45
DNP
47uF
C30
47uF
C36
47uF
C37
DNP
GND
VOUT
47uF
C58
DNP
47uF
C54
47uF
C59
DNP
47uF
C60
DNP
47uF
C56
DNP
47uF
C55
47uF
C57
DNP
47uF
C51 220uF
C63
220uF
C64
47uF
C61
DNP
47uF
C62
47uF
C52
47uF
C53
GND
VOUT
49.9
R36
49.9
R35
Remote Sense N
47uF
C50
47uF
C49
0R32
0
R33
0R37
DNP
0R39
DNP
VOUT
VSNS_P
VSNS_N
SW_P1
SW_P2
Remote Sense P
TP12
TP18
TP20
TP15
100uF
C34
100uF
C33
VSNS_P
VSNS_P
VSNS_N
VSNS_N
GND TP17
1
2
T4
IN
1
IN
2
IN[CP]
3
CP
4
EN
5
GND[CP]
6GND 7
FB 8
SET 9
OUT[FB] 10
OUT 11
OUT 12
DAP 13
U2
LP38798SD-ADJ
1µF
C22
10µF
C23
10nF
C24
47.5k
R29
15.0k
R30
560k
R31
GND
1
2
JP4
TP19
AVIN Aux_5V
GND
Auxilary 5V_0A8 to Overide VDD5
GND
CHA1 CHB1
TP10 TP9
TP7 TP8
TP6
TP13
TP16
TP26
TP30
1
2
SMB2 TP22
TP25
1
2
JP3
TP27
TP29
TP31
TP23
TP21
Test Points for BCX
External SYNC Input
Test Points for VSHARE
TP32
GND
TP24
GND
EXT_SYNC
PG_Stack
BC_CLK
BC_DAT
SYNC
VSH
1
2
T1
1
2
T2
47uF
C25
47uF
C26
DNP
47uF
C27
DNP
47uF
C28
DNP
47uF
C29
47uF
C46
DNP
47uF
C65
DNP
47uF
C66
DNP
47uF
C67
DNP
47uF
C68
47uF
C69
DNP
47uF
C70
DNP
47uF
C31
47uF
C32
47uF
C71
DNP
47uF
C72
DNP
GND
GND
VOUT
TP11
49.9
R34
49.9
R38
TP14
TP28
Remote Sense N1
Remote Sense P1
VOUT
SMBALT
CLK
DATA
CNTL
SMBALT
CLK
DATA
CNTL
SMBALT
CLK DATA
CNTL
T3
T5
1
3
56
4
2
7
910
8
12 11
J1
DNP
1
3
56
4
2
7
910
8
12 11
J3
DNP
VOUT
GND
GND
1
2
JP5
AVIN_LDO
1
2
JP6
DNP
AVIN
VBUS
1
D-
2
D+
3
ID
4
GND
5
67 8
11 10
9
J4
300nH
L2
300nH
L1
GND
1
2
JP8
DNP
VIN
Micro-USB Connection
VIN
TP33
DNP
30V
D2
30V
D1
HW1
BSR104E1_Hardware.SchDoc
Figure 3-1. TPS546B24AEVM-2PH Schematic Page 1
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22uF
C6_P1
1µF
C10_P1
DNP
22uF
C5_P1
10R3_P1
6800pF
C7_P1
6800pF
C8_P1
22uF
C3_P1
100uF
C2_P1
22uF
C4_P1
6800pF
C9_P1
0
R15_P1
0.1uF
C16_P1
DNP
4.7uF
C15_P1
7.50k
R14_P1
0.1uF
C20_P1
EN
AVIN
PVIN
PVIN
2.2µF
C18_P1
DNP
10.0k
R26_P1
PG
ADRSEL
VSEL
MSEL1
MSEL2
ADRSEL
SNS+
SMBALT
PM_CLK
PM_DAT
BC_CLK
BC_DAT
VIN
GND
SNS-
SW
VSH
GND
GND
VDD5
GND
BP1V5
BP1V5
VDD5
AGND
GND
AGND
30.1k
R9_P1
0R27_P1
0R25_P1
0
R23_P1
0
R16_P1
0R22_P1
SYNC
1000pF
C12_P1
1.0
R6_P1
GND
49.9
R5_P1
1
2
SMB1_P1
TP2_P1
TP4_P1
TP5_P1
45V
D1_P1
0.1uF
C13_P1
0
R4_P1
0
R1_P1
DNP
VDD5
CNTL 100pF
C17_P1
EN
GND
CNTL Jumper
1µF
C14_P1
DNP
1µF
C11_P1
S_VIN
NT1_P1
Net-Tie
VDD5
EXT_5V
1 2
3 4
5 6
JP2_P1
1 2
JP1_P1
TP1_P1
TP3_P1
PG_S
BP1V5
33pF
C21_P1
AGND
10.0k
R8_P1
DNP
AGND
AGND
0R17_P1
0R24_P1
DNP
GND
10.5k
R10_P1
DNP
MSEL2
10.5k
R11_P1
DNP
VSEL
10.5k
R20_P1
DNP
10.5k
R12_P1
DNP 53.6k
R13_P1
DNP
MSEL1
2.2µF
C19_P1
DRTN
1µF
C1_P1
GND
DRTN
10R2_P1 1
2
3
JP7_P1
TP34_P1
DNP
TP35_P1
DNP
14.7k
R19_P1
5.62k
R21_P1
0
R18_P1
DNP
PGD/RST 1
PMB_DATA
2
PMB_CLK
3
BP1V5
4
DRTN 5
SMB_ALRT
6
BOOT 7
SW 8
SW 9
SW 10
SW 11
SW 12
PGND 13
PGND 14
PGND 15
PGND 16
PGND 17
PGND 18
PGND 19
PGND 20
PVIN
21
PVIN
22
PVIN
23
PVIN
24
PVIN
25
AVIN
26
EN/UVLO
27
VDD5
28
MSEL2
29
VSEL
30
ADRSEL
31
MSEL1
32
VOSNS 33
GOSNS/FLWR 34
VSHARE 35
NC 36
AGND 37
SYNC 38
BCX_CLK 39
BCX_DAT 40
PAD 41
TPS546B24ARVFR
U1_P1
Figure 3-2. TPS546B24AEVM-2PH Schematic Page 2 (U1_P1 Loop Controller)
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22uF
C6_P2
1µF
C10_P2
DNP
22uF
C5_P2
10R3_P2
6800pF
C7_P2
6800pF
C8_P2
22uF
C3_P2
100uF
C2_P2
22uF
C4_P2
6800pF
C9_P2
0
R15_P2
0.1uF
C16_P2
DNP
4.7uF
C15_P2
7.50k
R14_P2
0.1uF
C20_P2
EN
AVIN
PVIN
PVIN
2.2µF
C18_P2
DNP
10.0k
R26_P2
PG
ADRSEL
VSEL
MSEL1
MSEL2
ADRSEL
SNS+
SMBALT
PM_CLK
PM_DAT
BC_CLK
BC_DAT
VIN
GND
SNS-
SW
VSH
GND
GND
VDD5
GND
BP1V5
BP1V5
VDD5
AGND
GND
AGND
30.1k
R9_P2
0
R27_P2
0
R25_P2
0
R23_P2
0
R16_P2
0R22_P2
SYNC
1000pF
C12_P2
1.0
R6_P2
GND
49.9
R5_P2
1
2
SMB1_P2
TP2_P2
TP4_P2
TP5_P2
45V
D1_P2
0.1uF
C13_P2
0
R4_P2
0
R1_P2
DNP
VDD5
CNTL 100pF
C17_P2
DNP
EN
GND
CNTL Jumper
1µF
C14_P2
DNP
1µF
C11_P2
S_VIN
NT1_P2
Net-Tie
VDD5
EXT_5V
1 2
3 4
5 6
JP2_P2
1 2
JP1_P2
TP1_P2
TP3_P2
PG_S
BP1V5
33pF
C21_P2
AGND
10.0k
R8_P2
AGND
AGND
0R17_P2
0R24_P2
DNP
GND
10.5k
R10_P2
DNP
MSEL2
10.5k
R11_P2
DNP
VSEL
10.5k
R20_P2
DNP
10.5k
R12_P2
DNP 53.6k
R13_P2
DNP
MSEL1
2.2µF
C19_P2
DRTN
1µF
C1_P2
GND
DRTN
10R2_P2 1
2
3
JP7_P2
TP34_P2
DNP
TP35_P2
DNP
14.7k
R19_P2
DNP 12.1k
R21_P2
DNP
0
R18_P2
PGD/RST 1
PMB_DATA
2
PMB_CLK
3
BP1V5
4
DRTN 5
SMB_ALRT
6
BOOT 7
SW 8
SW 9
SW 10
SW 11
SW 12
PGND 13
PGND 14
PGND 15
PGND 16
PGND 17
PGND 18
PGND 19
PGND 20
PVIN
21
PVIN
22
PVIN
23
PVIN
24
PVIN
25
AVIN
26
EN/UVLO
27
VDD5
28
MSEL2
29
VSEL
30
ADRSEL
31
MSEL1
32
VOSNS 33
GOSNS/FLWR 34
VSHARE 35
NC 36
AGND 37
SYNC 38
BCX_CLK 39
BCX_DAT 40
PAD 41
TPS546B24ARVFR
U1_P2
Figure 3-3. TPS546B24AEVM-2PH Schematic Page 3 (U1_P2 Loop Follower)
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4 Test Setup
4.1 Test and Configuration Software
To change any of the default configuration parameters on the EVM through PMBus, obtain the TI Fusion Digital
Power Designer software.
4.1.1 Description
The TI Fusion Digital Power Designer is the graphical user interface (GUI) used to configure and monitor the
Texas Instruments TPS546B24A power converter installed on this evaluation module. The application uses the
PMBus protocol to communicate with the controller over serial bus by way of a TI USB adapter described in
Section 4.2.6.
4.1.2 Features
Some of the tasks the user can perform with the GUI include:
• Turn on or off the power supply output, either through the hardware control line or the PMBus operation
command.
• Monitor real-time data that is continuously monitored and displayed by the GUI:
– Input voltage
– Output voltage
– Output current
– Die temperature
– Warnings and faults
• Configure common operating characteristics such as the following:
– VOUT trim and margin
– UVLO
– Soft-start time
– Warning and fault thresholds
– Fault response
– On/off modes
4.2 Test Equipment
4.2.1 Voltage Source
The input voltage source, VIN, should be a 0-V to 20-V variable DC source capable of supplying a minimum of 8
ADC to support 40-A load with 5-V input. Connect input VIN and GND to T1 and T2. If the output voltage of the
EVM is increased, the power supply may need to be capable of supplying more current.
4.2.2 Multimeters
TI recommends using two separate multimeters: one meter to measure VIN and the other to measure VOUT.
4.2.3 Output Load
A variable electronic load is recommended for the test setup. To test the full load current this EVM supports, the
load should be capable of sinking at least 40 A.
4.2.4 Oscilloscope
When using an oscilloscope to measure the switching node voltage or voltage ripple, measure using a Tip-and-
Barrel method as Figure 4-1 shows, or better.
4.2.5 Fan
During prolonged operation at high loads, it can be necessary to provide forced air cooling with a small fan
aimed at the EVM. Maintain the surface temperature of the devices on the EVM below their rated temperature.
4.2.6 USB-to-GPIO Interface Adapter
A communications adapter is required between the EVM and the host computer. This EVM is designed to use
TI's USB-to-GPIO adapter. Purchase this adapter at http://www.ti.com/tool/usb-to-gpio.
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4.2.7 Recommended Wire Gauge
• Input VIN and GND to T1 and T2 (GND) (12-V input) – The recommended wire size is AWG #12, with the
total length of wire less than two feet (1-foot input, 1-foot return).
• Output T3 and GND T5 (0.8-V output) – The minimum recommended wire size is AWG #10 with the total
length of wire less than two feet (1-foot output, 1-foot return). A thicker wire gauge can be required to
minimize the voltage drop the wires.
4.3 Tip and Barrel Measurement
Figure 4-1 illustrates the tip and barrel measurement for switching node waveform on TP2_P1 with TP4_P1 or
TP2_P2 with TP4_P2.
Metal Ground
Barrel
Probe
Tip
Figure 4-1. Tip and Barrel Measurement
4.4 List of Test Points, Jumpers, and Connectors
Table 4-1 lists the test point functions.
Table 4-1. Test Point Functions
Test
Point
Type Name Description
TP1_P1 T-H Loop PVIN_P1 PVIN pin voltage of U1_P1 device measurement point
TP1_P2 T-H Loop PVIN_P2 PVIN pin voltage of U1_P2 device measurement point
TP2_P1 T-H Loop SW_P1 Switching node of output rail phase 1 measurement point, reference to TP4_P1
TP2_P2 T-H Loop SW_P2 Switching node of output rail phase 2 measurement point, reference to TP4_P2
TP3_P1 T-H Loop GND_P1 GND pin voltage of U1_P1 device measurement point
TP3_P2 T-H Loop GND_P2 GND pin voltage of U1_P2 device measurement point
TP4_P1 T-H Loop GND_P1 GND reference for switch node measurement of U1_P1
TP4_P2 T-H Loop GND_P2 GND reference for switch node measurement of U1_P2
TP5_P1 T-H Loop PG_S_P1 PGOOD signal of phase 1
TP5_P2 T-H Loop PG_S_P2 PGOOD signal of phase 2
TP6 T-H Loop AUX_5V External 5-V measurement point for VDD5
TP7 T-H Loop DATA DATA signal on J2 header
TP8 T-H Loop SMBALRT SMBALERT signal on J2 header
TP9 T-H Loop CNTL CNTL signal on J2 header
TP10 T-H Loop CLK CLK signal on J2 header
TP11 T-H Loop GND GND reference
TP12 T-H Loop PVIN VIN + measurement point
TP13 T-H Loop VOUT_P1 U1_P1 output voltage measurement point for efficiency, reference to TP16
TP14 T-H Loop Remote SNS+ OUTPUT remote sense + voltage point
TP15 T-H Loop GND VIN- measurement point
TP16 T-H Loop GND_P1 U1_P1 output voltage referencing GND for efficiency measurement
TP17 T-H Loop CH_A OUTPUT for small signal loop gain measurements (B/A setup)
TP18 T-H Loop CH_B INPUT for small signal loop gain measurements (B/A setup)
TP19 T-H Loop Ext_AVIN AVIN measurement point
TP20 T-H Loop GND GND reference
TP21 T-H Loop VSHARE VSHARE measurement point. Sensitive signal
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Table 4-1. Test Point Functions (continued)
Test
Point
Type Name Description
TP22 T-H Loop VOUT VOUT + measurement point
TP23 T-H Loop GND GND reference
TP24 T-H Loop GND GND reference
TP25 T-H Loop GND VOUT – measurement point
TP26 T-H Loop VOUT_P2 U1_P2 output voltage measurement point for efficiency, reference to TP30
TP27 T-H Loop SYNC Synchronization connection between U1_P1 and U1_P2. External SYNC input
TP28 T-H Loop Remote SNS– OUTPUT remote sense – voltage point
TP29 T-H Loop BC_DAT Data for back-channel communications between stacked devices
TP30 T-H Loop GND_P2 U1_P2 output voltage referencing GND for efficiency measurement
TP31 T-H Loop BC_CLK Clock for back-channel communications between stacked devices
TP32 T-H Loop GND GND reference
TP33 T-H Loop VOSNS_P2 VOSNS measurement point for U1_P2
TP34_P1,
TP34_P2
T-H Loop MSEL2_P1,
MSEL2_P2
MSEL2 measurement point for U1_P1 and U1_P2
TP35_P1,
TP35_P2
T-H Loop VSEL_P1,
VSEL_P2
VSEL measurement point for U1_P1 and U1_P2
Table 4-2 lists the EVM jumpers.
Table 4-2. Jumpers
Jumper Type Name Description
JP1_P1,
JP1_P2 Header, 100 mil, 2 × 1 EXT_5.1V_P1, EXT_5.1V_P2 Short to connect VDD5 of U1_P1 or U1_P2 to the 5.1 V from U2
JP2_P1,
JP2_P2 Header, 100 mil, 3 × 2 CNTL_SEL1, CNTL_SEL2 U1_P1 and U1_P2 EN/UVLO pin selections
JP3 Header, 100 mil, 2 × 1 EN to GND Short to disable the auxiliary 5 V
JP4 Header, 100 mil, 2 × 1 AVIN-PVIN Short to connect to connect AVIN input to PVIN
JP5 Header, 100 mil, 2 × 1 AVIN-LDO Short to connect to connect AVIN input to U2 input
JP6 Header, 100 mil, 2 × 1 PMBus3.3V-AVIN Short to connect USB-to-GPIO 3.3 V to AVIN
JP7_P1,
JP7_P2 Header, 100 mil, 3 × 1 AVIN-U1_P1, AVIN-U1_P2 U1_P1 and U1_P2 AVIN input source selections
JP8 Header, 100 mil, 2 × 1 Micro_USB-PVIN Short to connect PVIN to Micro USB connector
Table 4-3 lists the options for the EN/UVLO pin selections on JP2_P1 and JP2_P2.
Table 4-3. JP2_P1 and JP2_P2 Selections
Shunt Position Selection
Pin 1 to 2 shorted PMBus adaptor control signal
Pin 3 to 4 shorted Resistor divider to PVIN
Pin 5 to 6 shorted EN/UVLO short to ground
Table 4-4 lists the options for the EN/UVLO pin selections on JP2_P1 and JP2_P2.
Table 4-4. JP7_P1 and JP7_P2 Selections
Shunt Position Selection
Pin 1 to 2 shorted AVIN pin connected to AVIN input through 10-Ω resistor. Use this selection when testing with a split rail input.
Pin 2 to 3 shorted AVIN pin connected to PVIN through 10-Ω resistor
Table 4-5 lists the EVM connector functions.
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Table 4-5. Connector Functions
Connector Type Name Description
J1 Header, 100 mil, 6 × 2 N/A Do not use
J2 Header, 100 mil, 5 × 2 PMBus connector PMBus socket for TI FUSION adaptor
J3 Header, 100 mil, 6 × 2 N/A Do not use
J4 Micro USB Micro USB Micro USB connector to power EVM from a 5 V USB
source
T1 Terminal block, 2 × 1 PVIN VIN+ connector
T2 Terminal block, 2 × 1 GND VIN– connector
T3 Terminal 90A Lug VOUT VOUT+ connector
T4 Terminal block, 2 × 1 Ext_AVIN External AVIN connector
T5 Terminal 90A Lug GND VOUT– connector
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4.5 Evaluating Single Phase Operation
The default configuration of the EVM is for 2-phase operation. For a single-phase operation, modify the EVM as
follows:
1. Short MSEL2 of U1_P1 to GND to program single-phase operation by populating R18_P1 with a 0-Ω
resistor.
2. If U1_P2 is left populated, disconnect VSHARE of the loop follower device from the loop controller by
depopulating R15_P1 (this is a 0-Ω resistor and can be used for MSEL2 pin of U1_P1 in the previous step).
3. If U1_P2 is left populated, disable U1_P2 by moving the JP2_P2 jumper to position 5-6 (GND).
Note
This will leave the AVIN (pin 26) of U1_P2 powered. If no-load leakage current or light-light efficiency
measurement is important, the U1_P2 AVIN pin should also be disconnected from the input supply.
Disconnect the loop follower U1_P2 AVIN from VIN by removing the jumper from JP7_P2.
4.6 Evaluating Split Rail Input
The default configuration of the EVM is for single rail input. Split rail input enables operation with 3.3-V PVIN. For
split rail operation, configure the jumpers on the EVM as follows:
1. Open JP4 to disconnect AVIN from PVIN.
2. Move the jumper JP7_P1 and JP7_P2 to position 1-2 to disconnect the AVIN pin from the PVIN pins.
3. Apply the AVIN input to T4. 4-V or greater AVIN is required to bring the VDD5 voltage high enough to enable
conversion.
4. If operation with 3.3-V PVIN is needed and the CNTL jumpers (JP2_P1 and JP2_P2) are in position 3-4, the
resistor divider at the EN/UVLO will need to be changed. Alternately, move the CNTL jumpers to position 1-2
and use the control signal to enable conversion or use the ON_OFF_CONFIG and OPERATION commands
to enable conversion.
4.7 Configuring EVM to Overdrive VDD5
The EVM has an external LDO (U2) that can be used to overdrive VDD5. The output of this LDO is set for 5.1 V
by default. This LDO is useful to minimize the power dissipation in the TPS546B24A IC when using a single rail
input. Overdriving VDD5 moves the loss from the internal LDO of the TPS546B24A to the external LDO (U2). To
use this LDO, configure the jumpers on the EVM as follows:
1. Short JP4 and JP5 to connect the input of the LDO to the input supply.
2. Open JP3 to enable the LDO.
3. Short JP1_P1 and JP1_P2 to connect the LDO output to the VDD5 pin.
4. Ensure the VDD5 output of the TPS546B24A is set below the external output voltage of the LDO.
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5 EVM Configuration Using the Fusion GUI
The TPS546B24A IC leaves the factory pre-configured. The factory default settings for the parameters can be
found in the data sheet. If configuring the EVM to settings other than the factory defaults, use the software
described in Section 4.1. It is necessary to have the input voltage applied to the EVM prior to launching the
software so that the TPS546B24A can respond to the GUI and the GUI can recognize the device. The default
configuration for the EVM to stop converting is set by the EN/UVLO resistor divider to a nominal input voltage of
4.75 V; therefore, if it is necessary to avoid any converter activity during configuration, an input voltage less than
4.75 V should be applied. TI recommends an input voltage of 3.3 V.
5.1 Configuration Procedure
1. Adjust the input supply to provide 3.3 VDC, current limited to 1 A.
2. Apply the input voltage to the EVM. See Section 4.2 for connections and test setup.
3. Launch the Fusion GUI software. See the screen shots in Section 10 for more information.
4. Configure the EVM operating parameters as desired.
By default, the pinstrap resistors configure U1_P1 as the loop controller and U1_P2 as the loop follower.
6 Test Procedure
6.1 Line and Load Regulation and Efficiency Measurement Procedure
1. Set up the EVM as Section 4.2 and Section 6.2 describe.
2. Set the electronic load to draw 0 ADC.
3. Increase VIN from 0 V to 12 V using voltage meter to measure input voltage.
4. Use the other voltage meter to measure output voltage VOUT.
5. Vary the load from 0 to 40 ADC. VOUT should remain in regulation as defined in Table 2-1.
6. Vary VIN from 5 V to 18 V. VOUT should remain in regulation as defined in Table 2-1.
7. Decrease the load to 0 A.
8. Decrease VIN to 0 V.
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6.2 Efficiency Measurement Test Points
To evaluate the efficiency of the power train (device and inductor), it is important to measure the voltages at
the correct location. This is necessary because otherwise the measurements will include losses that are not
related to the power train itself. Losses incurred by the voltage drop in the copper traces and in the input and
output connectors are not related to the efficiency of the power train, which should not be included in efficiency
measurements.
Input current can be measured at any point in the input wires, and output current can be measured anywhere in
the output wires of the output being measured.
Table 6-1 shows the measurement points for input voltage and output voltage. VIN and VOUT are measured
to calculate the efficiency. Using these measurement points will result in efficiency measurements that excluded
losses due to the wires and connectors.
Table 6-1. Test Points for Efficiency Measurements
Test Point Node Name Description Comment
TP12 PVIN Input voltage measurement point
for VIN+ The pair of test points is connected to the PVIN/PGND pins of U1_P1. The voltage drop
between input terminal to the device pins is included for efficiency measurement.
TP15 PGND Input voltage measurement point
for VIN– (GND)
TP22 VOUT Output voltage measurement
point for VOUT+ The pair of test points is connected near the output terminals. The voltage drop from the
output point of the inductor to the output terminals is included for efficiency measurement.
TP25 GND Output voltage measurement
point for VOUT– (GND)
For more accurate efficiency measurements of the power train, the voltage drop between the power train and the
terminals should also be removed from the measurement. Using the test points in Table 6-2 will reduce these
losses. To average the voltages at each test point so that only one meter is needed for PVIN and VOUT, add
some resistance between the each test point and the meter. For the measurements taken in this user's guide, a
1.5-kΩ resistor was added in series with each test point. Using these test points reduced the measured power
loss at 40 A load by approximately 0.15 W. This power is lost in the copper traces of the PCB.
Table 6-2. Test Points for Better Efficiency Measurements
Test Point Node Name Description Comment
TP1_P1 PVIN_P1 Input voltage measurement point
for VIN+ This pair of test points is connected to PVIN and PGND near the pins of U1_P1.
TP4_P1 GND_P1 Input voltage measurement point
for VIN– (PGND)
TP1_P2 PVIN_P2 Input voltage measurement point
for VIN+ This pair of test points is connected to PVIN and PGND near the pins of U1_P2.
TP4_P2 GND_P2 Input voltage measurement point
for VIN– (PGND)
TP13 VOUT_P1 Output voltage measurement
point for VOUT+ This pair of test points is connected to VOUT and GND near the output inductor for U1_P1.
TP16 GND_P1 Output voltage measurement
point for VOUT– (GND)
TP26 VOUT_P2 Output voltage measurement
point for VOUT+ This pair of test points is connected to VOUT and GND near the output inductor for U1_P2.
TP30 GND_P2 Output voltage measurement
point for VOUT– (GND)
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6.3 Control Loop Gain and Phase Measurement Procedure
The TPS546B24AEVM-2PH includes a 49.9-Ω series resistor in the feedback loop for VOUT. The resistor is
accessible at the test points TP17 and TP18 for loop response analysis. These test points should be used during
loop response measurements as the perturbation injecting points for the loop. See the description in Table 6-3.
Table 6-3. List of Test Points for Loop Response Measurements
Test Point Node Name Description Comment
TP18 CH_B Input to feedback divider of VOUT The amplitude of the perturbation at this node should be limited to less than 30 mV.
TP17 CH_A Resulting output of VOUT Bode can be measured by a network analyzer with a CH_B/CH_A configuration.
Measure the loop response with the following procedure:
1. Set up the EVM as described in Section 4.2.
2. For VOUT, connect the isolation transformer of the network analyzer from TP18 to TP17.
3. Connect the input signal measurement probe to TP18. Connect the output signal measurement probe to
TP17.
4. Connect the ground leads of both probe channels to TP20.
5. On the network analyzer, measure the Bode as TP18/TP17 (In/Out).
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7 Performance Data and Typical Characteristic Curves
Figure 7-1 through Figure 7-4 present typical performance curves for the TPS546B24AEVM-2PH. The input
voltage is 12 V and the oscilloscope measurements use 20-MHz bandwidth limiting, unless otherwise noted.
7.1 Efficiency
Output Current (A)
Efficiency (%)
0 5 10 15 20 25 30 35 40
40
50
60
70
80
90
100
VIN = 5 V
VIN = 12 V
VIN = 16 V
Figure 7-1. Efficiency, VOUT Measured Using TP13,
TP16, TP26, and TP30
Output Current (A)
Efficiency (%)
0 5 10 15 20 25 30 35 40
40
50
60
70
80
90
100
VIN = 5 V
VIN = 12 V
VIN = 16 V
Figure 7-2. Efficiency, VOUT Measured Using TP22
and TP25
7.2 Load and Line Regulation (Measured Between TP22 and TP25)
Output Current (A)
Output Voltage (V)
0 5 10 15 20 25 30 35 40
0.795
0.796
0.797
0.798
0.799
0.8
0.801
0.802
0.803
0.804
0.805
VIN = 5 V
VIN = 12 V
VIN = 16 V
Figure 7-3. Load Regulation
Input Voltage (V)
Output Voltage (V)
5 6 7 8 9 10 11 12 13 14 15 16
0.795
0.796
0.797
0.798
0.799
0.8
0.801
0.802
0.803
0.804
0.805
IOUT = 0 A
IOUT = 20 A
IOUT = 40 A
Figure 7-4. Line Regulation
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7.3 Transient Response
Figure 7-5 shows the transient response waveform with a 10-A to 30-A transient at 10 A/µs.
Figure 7-5. Transient Response
7.4 Control Loop Bode Plot
Figure 7-6 is the control loop bode plot.
Frequency (Hz)
Gain (dB)
1000 2000 5000 10000 100000 1000000
-60 -180
-40 -120
-20 -60
0 0
20 60
40 120
60 180
Gain
Phase
Figure 7-6. Bode Plot at 0.8-V Output at 12 VIN, 20-A Load
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7.5 Output Ripple
Figure 7-7 and Figure 7-8 show the output ripple waveforms at 0-A and 40-A load.
Figure 7-7. Output Ripple With 0-A Load
Figure 7-8. Output Ripple With 40-A Load
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7.6 Power MOSFET Drain-Source Voltage
Figure 7-9 and Figure 7-10 show the low-side and high-side MOSFET drain-source voltage (VDS) at 40-A load.
The voltage is measured with 1-GHz bandwidth and at the solder mask openings near the U1_P1 IC using a
1-GHz differential probe.
Figure 7-9. Low-Side MOSFET VDS
Figure 7-10. High-Side MOSFET VDS
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