Texas Instruments TPS54JA20EVM-023 User manual

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Using the TPS54JA20EVM-023 12-A, Buck Converter Evaluation Module
User's Guide
SLVUBO0A–March 2020–Revised May 2020
Using the TPS54JA20EVM-023 12-A, Buck Converter
Evaluation Module
This user’s guide contains information for the TPS54JA20EVM-023 evaluation module (EVM) as well as
for the TPS54JA20 DC/DC converter. Also included are the performance specifications, the schematic,
and the list of materials for the TPS54JA20EVM.
Contents
1 Introduction ................................................................................................................... 2
1.1 Background.......................................................................................................... 2
1.2 Performance Specification Summary ............................................................................ 3
1.3 Modifications......................................................................................................... 3
2 Test Setup and Results..................................................................................................... 5
2.1 Input/Output Connections.......................................................................................... 5
2.2 Start Up Procedure................................................................................................. 5
2.3 Efficiency............................................................................................................. 6
2.4 Load Regulation..................................................................................................... 8
2.5 Load Transients..................................................................................................... 9
2.6 Loop Characteristics .............................................................................................. 10
2.7 Output Voltage Ripple ............................................................................................ 11
2.8 Powering Up ....................................................................................................... 12
3 Schematic, List of Materials, and Layout................................................................................ 13
3.1 Schematic .......................................................................................................... 14
3.2 List of Materials.................................................................................................... 15
3.3 Layout............................................................................................................... 16
List of Figures
1 Safety Warnings ............................................................................................................. 2
2 TPS54JA20 Efficiency Plot: Vin Range................................................................................... 6
3 TPS54JA20 Efficiency Plot: Vcc Range .................................................................................. 6
4 TPS54JA20 Efficiency Plot: Skip Mode................................................................................... 7
5 TPS54JA20 Efficiency Plot: FCCM and Skip Mode..................................................................... 7
6 TPS54JA20 Load Regulation .............................................................................................. 8
7 TPS54JA20 Load Regulation .............................................................................................. 8
8 TPS54JA20 Load Transient Response................................................................................... 9
9 TPS54JA20 Load Transient Response................................................................................... 9
10 TPS54JA20 Bode Plot..................................................................................................... 10
11 TPS54JA20 Output Ripple, No Load .................................................................................... 11
12 TPS54JA20 Output Ripple, 12-A Load.................................................................................. 11
13 TPS54JA20 Output Ripple, Skip Mode, 10mA Load .................................................................. 11
14 TPS54JA20 Enable Start-Up, 12A Load................................................................................ 12
15 TPS54JA20 EN Shutdown, 12A Load................................................................................... 12
16 TPS54JA20EVM Top-Side Layout....................................................................................... 17
17 TPS54JA20EVM Internal Layer-1 Layout............................................................................... 17
18 TPS54JA20EVM Internal Layer-2 Layout............................................................................... 18

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19 TPS54JA20EVM Bottom-Side Layout................................................................................... 18
List of Tables
1 Input Voltage and Output Current Summary............................................................................. 2
2 TPS54JA20EVM Performance Specification Summary ................................................................ 3
3 TPS54JA20EVM Mode Pin Selection..................................................................................... 4
4 Enable Pin Selection ........................................................................................................ 4
5 TPS54JA20EVM EVM Connectors and Test Points.................................................................... 5
6 TPS54JA20EVM List of Materials........................................................................................ 15
Trademarks
D-CAP3 is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
1 Introduction
The TPS54JA20 is a D-CAP3™ synchronous buck converter designed for 12 A output current, and the
evaluation module is designed to demonstrate the small printed-circuit-board areas that may be achieved
when designing with the device. The high-side and low-side switching MOSFETs are integrated in the
device package along with their gate drive circuitry. Rated input voltage and output current ranges for the
evaluation module are given in Table 1.
1.1 Background
The EVM is setup to allow the user to evaluate the performance of the TPS54JA20 IC, and easily make
changes to multiple settings. The low drain-to-source on resistance of the MOSFETs allows the device to
achieve high efficiencies and keep the junction temperature low at high output currents. There is no need
for external compensation components since this device is designed with D-CAP3™ control topology. On
the EVM the switching frequency and the operation mode are externally selectable using a jumper to set
the resistor from the MODE pin to AGND. An external resistor divider allows for an adjustable output
voltage. Additionally, the device provides adjustable soft start, adjustable OC limit threshold, external
reference input, and an open-drain power good indicator. Lastly the TPS54JA20 device has a fixed
internal VIN under voltage lockout and externally adjustable UVLO using a resistor divider at the EN pin.
Table 1. Input Voltage and Output Current Summary
EVM INPUT VOLTAGE RANGE OUTPUT CURRENT
RANGE
TPS54JA20 VIN = 4 V to 16 V 0 A to 12 A
Figure 1. Safety Warnings

O INTREF
FB HS FB LS
INTREF
V V
R R
V
_ _

u
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1.2 Performance Specification Summary
A summary of the TPS54JA20EVM performance specifications is provided in Table 2. Specifications are
given for an input voltage of VIN = 12 V and an output voltage of 2.5 V, unless otherwise specified. The
TPS54JA20EVM is designed and tested for VIN = 4 V to 16 V. The ambient temperature is 25°C for all
measurements, unless otherwise noted.
Table 2. TPS54JA20EVM Performance Specification Summary
SPECIFICATION TEST CONDITIONS MIN TYP MAX Unit
VIN voltage range (without internal
Bias) 4 12 16 V
VIN voltage range (with external Bias) 2.7 12 16 V
Output voltage setpoint 2.5 V
Output current range VIN = 4 V to 16 V 0 12 12 A
Internal LDO Voltage 3.0 V
Line regulation VIN = 4 V to 16 V, IO= 12 A +/– 0.07%
Load regulation VIN = 12 V, IO= 0 A to 12 A +/– 0.12%
Load transient response
IO= 3 A to 9 A , 2
A/us Voltage change –50 mV
Recovery time 12 µs
IO= 9 A to 3 A , 2
A/us Voltage change 50 mV
Recovery time 12 µs
Loop bandwidth VIN = 12 V, IO= 12 A 75 kHz
Phase margin VIN = 12 V , IO= 12 A 58 degree
Output ripple voltage IO= 12 A 12 15 mVPP
Operating frequency 600 800 1000 kHz
1.3 Modifications
These evaluation modules are designed to provide access to the features of the TPS54JA20. Some
modifications can be made to this module.
1.3.1 Output Voltage Setpoint
To change the output voltage of the EVM, it is necessary to change the value of resistor R6 and R7. R9 is
fixed at 10k Ohm. Changing the total value of R6 plus R7 can change the output voltage above the 0.9V
reference voltage VINTREF. A two resistor configuration of R6+R7 is implemented to give the exact desired
output voltage setting. The value of R6 and R7 for a specific output voltage can be calculated using
Equation 1.
(1)
VINTREF= 0.9V
RFB_HS = R6+ R7
RFB_LS = R9= 10kΩ

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1.3.2 Frequency and Operation Mode Setting
To change the frequency and operation mode of the part, the MODE pin is used. J6 and the surrounding
circuitry allows for an easy change to the frequency and operation mode setting. All 6 options offered by
J6 are shown in Table 3
Table 3. TPS54JA20EVM Mode Pin Selection
Switching Frequency (FSW)Operation Mode Under
Light Load Mode Pin Connections
Connection Jumper Setting
600 kHz Skip Mode Short to VCC Short Pins 1 and 2
800 kHz Skip Mode 243kΩ+/- 10% to AGND Short Pins 3 and 4
1000 kHz Skip Mode 121kΩ+/- 10% to AGND Short Pins 5 and 6
1000 kHz Forced CCM 60.4kΩ+/- 10% to AGND Short Pins 7 and 8
800 kHz Forced CCM 30.1kΩ+/- 10% to AGND Short Pins 9 and 10
600 kHz Forced CCM Short to AGND Short Pins 11 and 12
1.3.3 Enable Pin Selection
The converter can be enabled and disabled by J5.
Default setting: EN pin connected to VIN.
Table 4. Enable Pin Selection
Set On Connection Enable Selection
Pins 2-3 Shorted EN pin connected to VIN pins through resistor divider
J3 Open EN pin is left floating
Pins 1-2 Shorted EN pin connected to PGND
1.3.4 Remote Sensing
The EVM is not set-up for remote sensing by default. To set up remote sensing follow these steps:
1. Replace R8 and R11 with 100Ωresistors
2. Connect your sense points to the Vsns+ and Vsns- test points
1.3.5 Adjustable UVLO
The undervoltage lockout (UVLO) can be adjusted externally using R2 and R9. See the TPS54JA20 Data
Sheet to get detailed instructions for setting the external UVLO.

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2 Test Setup and Results
This section describes how to properly connect, set up, and use the TPS54JA20EVM. This section also
includes test results typical for the evaluation module and covers efficiency, output voltage regulation, load
transient, loop response, output ripple, and start-up.
2.1 Input/Output Connections
The TPS54JA20EVM is provided with input/output connectors and test points as shown in Table 5. A
power supply capable of supplying greater than 15 A must be connected to J1 and J2 through a pair of
20-AWG wires or better. The load must be connected to J3 and J4 through a pair of 20-AWG wires or
better on each connector. The maximum load current capability is 12 A.
Wire lengths must be minimized to reduce losses in the wires. Test point VIN_SENSE+ provides a place
to monitor the input voltage with Test point VIN_SENSE- providing a convenient ground reference. Test
point VOUT+ is used to monitor the output voltage with VOUT- as the ground reference.
Table 5. TPS54JA20EVM EVM Connectors and Test Points
REFERENCE
DESIGNATOR FUNCTION
J1 VIN input voltage connector (see Table 1 for VIN range)
J2 PGND connection for input
J3 VOUT, 2.5V at 12A maximum
J4 PGND connection for output
J5 3-pin header for enable. ON -> Connects EN to VIN to enable the device. OFF- > Connects EN to GND
to disable device. Floating EN will prevent the part from operating.
J6 12 Pin header for Mode selection (see Table 3)
VIN_SENSE+,
VIN_SENSE- VIN voltage sensing test points
VOUT+, VOUT- VOUT voltage sensing test points
VCC, PGND VCC voltage forcing/sensing test points
PGOOD PGOOD output test point (pulled up to VCC pin through a 30kΩresistor)
EN EN test point
VSNS+, VSNS- Remote sensing test points
AGND AGND test point
BODE+, BODE- Loop measurement test points (BODE+ is at the same net as VOUT, but is closer to FB divider and IC)
SS/REFIN Can be used to monitor the reference voltage
SW Switch Node test point
2.2 Start Up Procedure
1. Make sure the EN jumper (J5) is in the ON position (shorting pin 2 and pin 3) to connect the EN pin to
the resistor divider from VIN.
2. (Optional) Apply appropriate external bias voltage on VCC and PGND test points. If no external bias,
please go directly to step 3. The external bias range is 3.3V to 5.3V.
3. Apply appropriate VIN voltage to the VIN and PGND terminals at J1 and J2.

Output Current (A)
Efficiency (%)
0 2 4 6 8 10 12
70
80
90
100
Vin = 12 V
Vout = 2.5 V
800 kHz
800 nH
FCCM
D020
INTVCC
3.3-V VCC
5-V VCC
Output Current (A)
Efficiency (%)
0 2 4 6 8 10 12
20
30
40
50
60
70
80
90
100
Vout = 2.5 V
800 kHz
800 nH
VCC = Int
FCCM
D019
Vin = 8 V
Vin = 12 V
Vin = 16 V
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2.3 Efficiency
The efficiency of this EVM peaks at a load current of about 6 A and then decreases as the load current
increases toward full load. The following images show the efficiency for the TPS54JA20EVM at an
ambient temperature of 25°C. Figure 2 shows the efficiency over a range of Vin values, Figure 3 shows
efficiency over a range of Vcc values, and Figure 4 shows how the light load efficiency is improved in
DCM. Figure 2 and Figure 4 compare the efficiency of FCCM and Skip modes.
Figure 2. TPS54JA20 Efficiency Plot: Vin Range
Figure 3. TPS54JA20 Efficiency Plot: Vcc Range

Output Current (A)
Efficiency (%)
0 2 4 6 8 10 12
20
30
40
50
60
70
80
90
100
Vin = 12 V
Vout = 2.5 V
800 kHz
VCC = Int
800 nH
D021
FCCM
Skip
Output Current (A)
Efficiency (%)
0 2 4 6 8 10 12
20
30
40
50
60
70
80
90
100
Vout = 2.5 V
800 kHz
800 nH
VCC = Int
Skip
D022
Vin = 8 V
Vin = 12 V
Vin = 16 V
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Figure 4. TPS54JA20 Efficiency Plot: Skip Mode
Figure 5. TPS54JA20 Efficiency Plot: FCCM and Skip Mode

Output Current (A)
Output Voltage (V)
0 1 2 3 4 5 6 7 8 9 10 11 12
2.484
2.487
2.49
2.493
2.496
2.499
2.502
2.505
2.508
2.511
2.514
2.517
800 kHz
800 nH
Skip
VCC = Int
D026
Vin = 8 V
Vin = 12 V
Vin = 16 V
Output Current (A)
Output Voltage (V)
0 1 2 3 4 5 6 7 8 9 10 11 12
2.484
2.487
2.49
2.493
2.496
2.499
2.502
2.505
2.508
2.511
2.514
2.517
800 kHz
800 nH
FCCM
VCC = Int
D024
Vin = 8 V
Vin = 12 V
Vin = 16 V
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2.4 Load Regulation
Figure 6 and Figure 7 show the load regulation for the TPS54JA20EVM.
Measurements are given for an ambient temperature of 25°C.
Figure 6. TPS54JA20 Load Regulation
Figure 7. TPS54JA20 Load Regulation

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2.5 Load Transients
Figure 8 and Figure 9 show how the TPS54JA20EVM response to load transients. The current step is
from 25% to 75% Load. The current step slew rate is 2 A/µs. Total peak-to-peak voltage variation is as
shown, including ripple and noise on the output.
Figure 8. TPS54JA20 Load Transient Response
Figure 9. TPS54JA20 Load Transient Response

Frequency (Hz)
Gain (dB)
Phase (Degrees)
1000 2000 3000 5000 7000 10000 20000 30000 50000 100000 200000300000 500000 1000000
-40 -200
-30 -150
-20 -100
-10 -50
0 0
10 50
20 100
30 150
40 200
50 250
60 300
70 350
80 400
Vin = 12 V
Vout = 2.5 V
800 kHz
VCC = Int
800 nH
Iout = 12 A
D018
Gain
Phase
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2.6 Loop Characteristics
Figure 10 shows the TPS54JA20EVM loop-response characteristics. Gain and phase plots are shown for
VIN voltage of 12 V. Load current for the measurement is 100%.
Figure 10. TPS54JA20 Bode Plot

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2.7 Output Voltage Ripple
Figure 11,Figure 12, and Figure 13 show the TPS54JA20EVM output voltage ripple. VIN = 12 V. The
ripple voltage is measured directly across the last ceramic output capacitor.
Figure 11. TPS54JA20 Output Ripple, No Load
Figure 12. TPS54JA20 Output Ripple, 12-A Load
Figure 13. TPS54JA20 Output Ripple, Skip Mode, 10mA Load

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2.8 Powering Up
Figure 14 shows the start-up waveforms for the TPS54JA20EVM. In Figure 14, the start-up sequence
begins as soon as the EN voltage is increased above the enable-threshold voltage, and the output voltage
ramps up to the externally set value of 2.5 V. The input voltage for these plots is 12 V.
Figure 14. TPS54JA20 Enable Start-Up, 12A Load
2.8.1 Powering Down
Figure 15 shows the TPS54JA20EVM shutdown. The input voltage for these plots is 12 V.
Figure 15. TPS54JA20 EN Shutdown, 12A Load

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3 Schematic, List of Materials, and Layout
This section provides a schematic, a description of the TPS54JA20EVM board layout, and layer
illustrations.

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3.1 Schematic
The following image illustrates the schematic for the TPS54JA20EVM.

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3.2 List of Materials
Table 6 presents the List of materials for the TPS54JA20EVM.
Table 6. TPS54JA20EVM List of Materials
DES QTY DESCRIPTION PART NUMBER MANUFACTURER
C2 1 CAP, AL, 330 uF, 25 V, +/- 20%, 0.15 ohm, SMD, 330uF EEE-FC1E331P Panasonic
C5, C6,
C21, C22 4 CAP, CERM, 22 uF, 25 V, +/- 20%, X6S, 1206_190 GRM31CC81E226ME 11L MuRata
C7, C8,
C32 3 CAP CER 1UF 25V X6S 0402 GRM155C81E105KE 11D Murata
C9 1 CAP, CERM, 0.1 uF, 50 V, +/- 10%, X7R, AEC-Q200
Grade 1, 0603 CGA3E2X7R1H104K 080AA TDK
C10 1 CAP, CERM, 2.2 uF, 10 V, +/- 10%, X7R, 0603 GRM188R71A225KE
15D MuRata
C11, C24 2 CAP, CERM, 0.1 uF, 6.3 V, +/- 10%, X7R, 0402 GRM155R70J104KA0
1D MuRata
C12, C13,
C14, C25,
C26, C27
6 CAP, CERM, 47 uF, 6.3 V, +/- 10%, X6S, 1206 GRM31CC80J476KE
18L MuRata
C19 1 CAP, CERM, 0.22 uF, 16 V, +/- 10%, X7R, 0603 C1608X7R1C224K08
0AC TDK
C20 1 CAP, CERM, 0.022 uF, 16 V, +/- 10%, X7R, 0603 C0603C223K4RACTU Kemet
L1 1 Inductor, Shielded, Composite, 800 nH, 25.8 A, 0.00208
ohm, SMD XAL7070-801MEB Coilcraft
R1, R17 2 RES, 0, 1%, 0.5 W, 1206 5108 Keystone
R2, R7,
R11 3 RES, 0, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 RMCF0603ZT0R00 Stackpole Electronics Inc
R3, R12 2 RES, 30.1 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 CRCW060330K1FKE
AVishay-Dale
R4 1 RES, 20.0 k, 0.1%, 0.1 W, 0603 RT0603BRD0720KL Yageo America
R5 1 RES, 4.99 k, 1%, 0.1 W, 0603 RC0603FR-074K99L Yageo
R6 1 RES, 17.8 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 CRCW060317K8FKE
AVishay-Dale
R8 1 RES, 10.0, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 CRCW060310R0FKE
AVishay-Dale
R9, R10 2 RES, 10.0 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 CRCW060310K0FKE
AVishay-Dale
R13 1 RES, 60.4 k, 1%, 0.1 W, 0603 RC0603FR-0760K4L Yageo
R14 1 RES, 121 k, 1%, 0.1 W, 0603 RC0603FR-07121KL Yageo
R15 1 RES, 243 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 CRCW0603243KFKE
AVishay-Dale
U1 1 4-V to 16-V Input, 12-A Single Synchronous Step-Down
Converter, RWW0021A (VQFN-HR-21) TPS54JA20RWWT Texas Instruments

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3.3 Layout
The board layout for the TPS54JA20EVM is shown in Figure 16 through Figure 19. The top-side layer of
the EVM is laid out in a manner typical of a user application. The top, bottom, and internal layers are 2-oz.
copper.
The top layer contains the main power traces for VIN, VOUT, and SW. Also on the top layer are connections
for the remaining pins of the TPS54JA20 and the majority of the signal traces. The top layer has a
dedicated ground plane for quiet analog ground that is connected to the main power ground plane at a
single point. The internal layer-1 is a large ground plane. The internal layer-2 contains an additional large
ground copper area as well as an additional VOUT copper fill. The bottom layer is another ground plane
with two additional traces for the output voltage feedback and various signals routed to test points and
headers. There are also additional VIN and VOUT planes on the bottom layer. The top-side ground traces
are connected to the bottom and internal ground planes with multiple via groupings placed around the
board.
The input decoupling capacitors and bootstrap capacitor are all located as close to the IC as possible.
Additionally, the voltage set point resistor divider components are kept close to the IC. The voltage divider
network ties to the output voltage at the point of regulation, the copper VOUT trace at the TP4 test point. An
additional input bulk capacitor is used to limit the noise entering the converter from the input supply.
Critical analog circuits that are noise sensitive are terminated to the quiet analog ground island on the top
layer.

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Figure 16. TPS54JA20EVM Top-Side Layout
Figure 17. TPS54JA20EVM Internal Layer-1 Layout

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Figure 18. TPS54JA20EVM Internal Layer-2 Layout
Figure 19. TPS54JA20EVM Bottom-Side Layout

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Revision History
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2020) to A Revision ....................................................................................................... Page
• Changed marketing status from select disclosure to catalog........................................................................ 1

STANDARD TERMS FOR EVALUATION MODULES
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documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
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clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
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or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2Limited Warranty and Related Remedies/Disclaimers:
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Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
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warranty period.
WARNING
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professional electronics experts who are familiar with the dangers
and application risks associated with handling electrical mechanical
components, systems, and subsystems.
User shall operate the Evaluation Kit within TI’s recommended
guidelines and any applicable legal or environmental requirements
as well as reasonable and customary safeguards. Failure to set up
and/or operate the Evaluation Kit within TI’s recommended
guidelines may result in personal injury or death or property
damage. Proper set up entails following TI’s instructions for
electrical ratings of interface circuits such as input, output and
electrical loads.
NOTE:
EXPOSURE TO ELECTROSTATIC DISCHARGE (ESD) MAY CAUSE DEGREDATION OR FAILURE OF THE EVALUATION
KIT; TI RECOMMENDS STORAGE OF THE EVALUATION KIT IN A PROTECTIVE ESD BAG.