Texas Instruments TPS55065EVM User manual

TPS55065EVM User's Guide
User's Guide
Literature Number: SLIU003
October 2009

2SLIU003–October 2009
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1 Introduction ........................................................................................................................ 5
2 Setup ................................................................................................................................. 5
2.1 Input/Output Connector Description .................................................................................. 5
2.2 Setup ...................................................................................................................... 6
2.3 Operation ................................................................................................................. 7
3 Board Layout ...................................................................................................................... 7
4 Schematic ......................................................................................................................... 10
3
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List of Figures
1 Slew Rate Jumper Settings................................................................................................ 5
2 Low Power Mode Jumper Settings ....................................................................................... 6
3 Enable Jumper Settings.................................................................................................... 6
4 5Vg Regulated Output Jumper Settings ................................................................................. 6
5 Low Pass Filter Inductor Bypass Jumper Settings ..................................................................... 6
6 Top Assembly Layer........................................................................................................ 8
7 Bottom Assembly Layer.................................................................................................... 8
8 Top Layer Routing .......................................................................................................... 9
9 Bottom Layer Routing ...................................................................................................... 9
10 TPS55065EVM Schematic............................................................................................... 10
List of Tables
1 Device and Package Configurations ..................................................................................... 5
2 TPS55065EVM Bill of Materials ......................................................................................... 11
4List of Figures SLIU003–October 2009
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SCR1
slow
SCR0
1
0
SCR1
medium -slow
SCR0
1
0
SCR1
medium-fast
SCR0
1
0
SCR1
fast
SCR0
1
0
User's Guide
SLIU003–October 2009
TPS55065EVM User's Guide
1 Introduction
The Texas Instruments TPS55065EVM evaluation module (EVM) helps designers evaluate the operation
and performance of the TPS55065 Switch Mode Power Supply – Buck Regulator. The EVM contains one
dc/dc converter (see Table 1).
Table 1. Device and Package Configurations
CONVERTER IC PACKAGE
U1 TPS55065QPWPRQ1 PWP-20
2 Setup
This section describes the jumpers and connectors on the EVM as well and how to properly connect, set
up, and use the TPS55065EVM.
2.1 Input/Output Connector Description
J1 – VBAT is the power input terminal for the converter. The terminal provides power (Vbat).
J2 – GND is the ground terminal for the EVM.
J3 – 5Vg is the power output terminal for the 5Vg regulator output.
J4 – VOUT is the regulated output voltage for the converter.
J5 – GND is a ground terminal for the EVM.
JP1, JP2 – SCR1, SCR0 are jumpers used to set the slew rate of the switching transistor for the L1
terminal switch pin. Jumpers allow the slew rate to be set to four set points.
Figure 1. Slew Rate Jumper Settings
5
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LPM
disabled
LPM
enabled
1
0
1
0
EN
disabled
EN
enabled
1
0
1
0
5Vg
disabled
5Vg
enabled
1
0
1
0
BYPASS
active
BYPASS
shorted
Setup www.ti.com
JP3 – LPM is the jumper used to enable Low Power Mode. The jumper allows LPM to be enabled or
disabled. The device will operate in Normal mode when LPM is disabled.
Figure 2. Low Power Mode Jumper Settings
JP4 – Enable is the jumper used to enable the converter. The converter is enabled when the Enable is
high and disabled when low. The jumper placement allows the converter to be enabled or disabled.
Figure 3. Enable Jumper Settings
JP5 – 5VgEN is the jumper used to enable switched 5V regulated output. The output is enabled when the
Enable is high and disabled when low. The jumper placement allows the converter to be enabled or
disabled.
Figure 4. 5Vg Regulated Output Jumper Settings
JP6 – Bypass is the jumper used to bypass the low pass filter inductor on the power supply input to the
device. This allows the user to remove the filter from the circuit. The jumper placement allows the inductor
to be active or shorted.
Figure 5. Low Pass Filter Inductor Bypass Jumper Settings
2.2 Setup
The input voltage range for the converter is 1.5 V to 40 V. The input voltage must be at least 5 V during
start up.
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2.3 Operation
For proper operation of the TPS55065, JP1, JP2, JP3, JP4, JP5, and JP6 should be properly configured.
The recommended setting, using shorting blocks:
JP1 and JP2 to Fast
JP3 to Enabled
JP4 to Enabled
JP5 to Enabled, if 5Vg is used
JP6 to Shorted
In this configuration, the device powers up when power is applied. JP1, JP2 SCR0, SCR1 select how
switch pin slew rate is set: slow, medium-slow, medium-fast, or fast. JP3 LPM selects how Low Power
Mode is set: Enabled or Disabled. JP4 EN turns the device on or off. JP5 5Vg turns the regulated 5-V
output on or off. JP6 Bypass disables the low-pass filter located on the input supply to the device.
3 Board Layout
Figure 6,Figure 7,Figure 8, and Figure 9 show the board layout for the TPS55065EVM PWB. The EVM
offers resistors, capacitors, and jumpers to program the switch pin slew rate and regulator turn-on Delay.
Jumpers are also provided to enable the device and to enable the low-power mode option.
The TPS55065 offers high efficiency but does dissipate power. The PowerPAD™ package offers an
exposed thermal pad to enhance thermal performance. This must be soldered to the copper landing on
the PCB for optimal performance. The PCB provides 1-oz copper planes on the top and bottom to
dissipate heat.
Figure 6. Top Assembly Layer
7
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Figure 7. Bottom Assembly Layer
Figure 8. Top Layer Routing
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Figure 9. Bottom Layer Routing
9
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GND
C2
C7
GND
D2
Aout 13
L1
5
Cboot2
25Vg_ENABLE 19
Rmod 15
GND 16
L2
7
PGND
6
Vdriver
4
Cboot1
3
SCR1
1
ENABLE 18
Vlogic 17
SCR0 20
5Vg
9
Ain
10
Vout
8
RESET 12
PAD
1
2
REST 14
TPS55065
CLP 11
2
1
L1
C1
GND
GND
GND
C3
GND
R1
GND
C4
GND
R3 R4
GND
C10
VOUT
1
JP1
D1
2 1
L2
R2 R5
GND
VDRIVER
AIN
VBAT
VDRIVER
AIN
VLOGIC
SCR1
SCR1
GND
1
JP2
VLOGIC
SCR0
SCR0
VLOGIC
C5
GND
VOUT
VOUT
GND
ENABLE
VDRIVER
ENABLE
5VG_ENABLE
GND
1
JP5
5VG_ENABLE
VDRIVER
C9
GND
JP6
5Vg
2 1
+C6
2 1
+C8
GND
REST AOUT RESET
GND
GND
GND
GND
GND
1
JP3
VLOGIC
LPM
LPM
1
JP4
Schematic www.ti.com
4 Schematic
Figure 10. TPS55065EVM Schematic
10 TPS55065EVM User's Guide SLIU003–October 2009
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