Texas Instruments TPS2543EVM User manual

User's Guide
SLVU660–February 2012
TPS2543EVM User's Guide
This user’s guide describes the evaluation module (EVM) for the TPS2543. TPS2543 is a USB charging
port power switch and controller for charging host ports and dedicated charging ports.
Contents
1 Description ................................................................................................................... 2
1.1 Features ............................................................................................................. 2
1.2 Applications ......................................................................................................... 2
1.3 Glossary of Terms ................................................................................................. 2
2 Schematic .................................................................................................................... 3
3 General Configuration and Description .................................................................................. 4
3.1 Physical Access .................................................................................................... 4
3.2 Test Setup .......................................................................................................... 5
4 EVM Assembly Drawings and Layout Guidelines ...................................................................... 6
4.1 PCB Drawings ...................................................................................................... 6
4.2 Layout Guidelines .................................................................................................. 9
5 Bill of Materials ............................................................................................................. 10
List of Figures
1 TPS2543EVM Schematic.................................................................................................. 3
2 Typical TPS2543EVM Test Setup ........................................................................................ 5
3 Top Side Placement........................................................................................................ 6
4 Top Side Routing ........................................................................................................... 6
5 Layer Two Routing.......................................................................................................... 7
6 Layer Three Routing........................................................................................................ 7
7 Figure 7. Bottom Side Routing............................................................................................ 8
8 Bottom Side Placement .................................................................................................... 8
List of Tables
1 Connector Functionality.................................................................................................... 4
2 Test Points................................................................................................................... 4
3 Jumpers ...................................................................................................................... 4
4 TPS2543 Mode Truth Table............................................................................................... 5
5 TPS2543EVM Bill of Materials........................................................................................... 10
1
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Description www.ti.com
1 Description
The TPS2543EVM allows reference circuit evaluation of the TI TPS2543 USB charging port power switch
and controller.
1.1 Features
•USB Charging Port Power Switch and Controller
•Meets Battery Charging Specification BC1.2 for DCP and CDP
•Meets Chinese Telecommunications Industry 2.0 Standard YD/T 1591-2009
•Compatible With USB 2.0 and 3.0 Power Switch Requirements
•Adjustable Current Limit, 230 mA–2800 mA Typical
•Fast Overcurrent Response –1.5 μs Typical
•73-mΩHigh-Side MOSFET
•2.6-GHz Bandwidth USB 2.0 Data Switch
•EVM supports USB 3.0 data passthrough
1.2 Applications
•USB Ports/Hubs
•Notebook PCs
1.3 Glossary of Terms
•Charging downstream port (CDP)
–A downstream port that complies with the USB 2.0 definition of a host or a hub, and additionally
defines a handshake on DP/DM to identify a BC 1.1 compliant host to a BC 1.1 compliant portable
device
–BC 1.1 allows a high-speed portable device to draw 900 mA and low-speed or full-speed device to
draw 1500 mA
–BC 1.2 intention is to allow all devices to draw 1500 mA
–BC 1.2 corrects BC 1.1 to ensure USB host provides 5 V at >1500 mA
•Standard downstream port (SDP)
–USB 2.0 defined port currently adopted by most USB ports
–Portable device is allowed to draw 100 mA initially and request additional current over USB
communications in 100-mA steps up to a maximum of 500 mA
–USB host required to provide at least 500 mA at 5 V
–Portable device must draw less than 2.5 mA when in USB Suspend due to the absence of USB
communication
•Dedicated charging port (DCP) as defined in BC 1.1
–BC 1.1 defines a dedicated charging port as a downstream port on a device that outputs power
through a USB connector, but is not capable of enumerating a downstream device.
–Wall adapter must source between 500 mA and 1500 mA.
–Portable device may attempt to draw 1800 mA in order to force the wall adapter into
constant-current mode.
–BC 1.2 intention is to allow DCP to current limit above 1800 mA
•YD/T 1591-2006, updated 2009
–PROC Telecommunications Standard
–Defines wall-adapter requirements
–Rated current between 500 mA–1500 mA with defined I-V curve
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1
2
GND
DM-OUT
GND
VOUT
USB HOST SIDE
AUX
INPUT
+
-
IN
DM-INDP-IN
2
VOUT-ON
5 +/- 0.1V
DP-OUT
NOT INSTALLED
NOTES:
Install ILIM_SEL shunt for ILIM = ILIM_LO = 0.63A
Remove ILIM_SEL shunt for ILIM =ILIM_HI = 2.97A
~FAULT ~STATUS
SSTX+
SSTX-
D-
D+
SSRX+
SSRX-
VBUS
GND
G_DRN
SSTX+
SSTX-
D-
D+
SSRX+
SSRX-
VBUS
GND
G_DRN
USB PD SIDE
USB 2.0 w/USB 3.0 PASS THRU
USB 2.0 w/USB 3.0 PASS THRU
SSP PASS THRU (90 +/- 7 OHM DIFFERENTIAL IMPEDANCE
3NOT INSTALLED on TPS2545EVM-064
3
3
TP5
JP1
TP2
TP3
R1
2k
TP7 TP8
JP2
D2
LN1371G
TP6
R6
100k
R3
80.6k
R7
100k
R8
100k
1 2 3
4
L1
370-Ohm
R4
2k
1
2
J1
R11
100k
R12
100k
R13
100k
R9
100k
R10
100k
TP1
D1
LN1271R
TP4
C1
10uF
C2
0.1uF
R5
100k
R2
16.9k
+
C3
150 uF
C4
0.1uF
1
GND
2
IO1
3IO2
4VCC
U2
TPD2E001DZDR
1IN
2DM_OUT
3DP_OUT
4ILIM_SEL
5
EN
6
CTL1
7
CTL2
8
CTL3
9
STATUS
10
DP_IN
11
DM_IN
12
OUT
13
FAULT
14
GND
15
ILIM_LO
16
ILIM_HI
17
PWPD
U1
TPS2543RTE
D3
LN1271R
R14
2k
TP9 TP10
1
2
3
4
5
6
7
8
9
10
11
J2
1
2
3
4
5
6
7
8
9
10
11
J3
1
2
3
4
5
6
7
8
9
10
JP3
S001
www.ti.com Schematic
2 Schematic
Figure 1. TPS2543EVM Schematic
spacer
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General Configuration and Description www.ti.com
3 General Configuration and Description
3.1 Physical Access
Table 1 lists the TPS2543EVM connector functionality, Table 2 describes the test point availability and
Table 3 describes the jumper functionality.
Table 1. Connector Functionality
Connector Label Description
J1 AUX Auxiliary high-current input connector
J2 USB INPUT USB input port
J3 POWER+DATA Charging port
D1 (RED) FAULT Fault LED
D2 (GREEN) VOUT-ON USB output powered
D3 (RED) STATUS STATUS pin LED
Table 2. Test Points
Test Point Color Label Description
TP1 WHT DP-OUT Data+ out
TP2 WHT DM-OUT Data–out
TP3 RED IN Power bus input
TP4 RED VOUT Power bus output
TP5 SM GND Power bus GND
TP6 SM GND Power bus GND
TP7 ORG DP-IN Data+ in
TP8 ORG DM-IN Data–in
TP9 WHT FAULT Fault pin
TP10 WHT STATUS Status pin
Table 3. Jumpers
Jumper Label Description
JP1 VIN Power bus input. Install shunt to allow charger source to power TPS2543 and downstream circuitry.
JP2 VOUT Power bus output. Install shunt to allow charger source to power downstream devices.
JP3 CTL3 CTL3. See MODE truth table.
CTL2 CTL2. See MODE truth table.
CTL1 CTL1. See MODE truth table.
EN TPS2543 enable select. Install shunt to disable TPS2543.
ILIM ILIM select. Install shunt to select ILIM_LO (0.6 A typical ILIM). Remove shunt to select ILIM_HI (2.8A typical ILIM).
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TPS2543EVM
J2 J3
D1
D3
PC (USB charging source)
PD
J1 D2
J3
www.ti.com General Configuration and Description
Table 4. TPS2543 Mode Truth Table
CTL1 CTL2 CTL3 ILIM_SEL Mode
0 0 0 X OUT discharge, power switch OFF
0 0 1 0 Dedicated charging port, auto-detect, without power-wake function
0 0 1 1 Dedicated charging port, auto-detect, with power wake function(1)
0 1 1 0 Dedicated charging port, auto-detect, with load detection disabled
0 1 1 1 Dedicated charging port, auto-detect, with load detection enabled(2)
1 0 0 X Dedicated charging port, BC 1.2 only, ILIM_HI or ILIM_LO is selected to set IOS
by ILIM_SEL.
1 0 1 X Dedicated charging port, Divider1 mode only, ILIM_HI or ILIM_LO is selected to
set IOS by ILIM_SEL.
X 1 0 X Standard downstream port, USB 2.0 mode, ILIM_HI or ILIM_LO is selected to
set IOS by ILIM_SEL.
1 1 0 1 Standard downstream port, USB 2.0 mode, ILIM_LO is selected to set IOS , no
discharge to or from 1111
1 1 1 1 Charging downstream port, BC 1.2, with load detection enabled(2)
(1) Current limit (IOS) is automatically changed, IOS is IOS_PW while no load, IOS is switched to the value set by ILIM_HI and STATUS is
active-low while with load
(2) ILIM_HI is selected to set IOS, ILIM_LO is selected to set load-detection current threshold (ILD)
3.2 Test Setup
Figure 2 shows a typical test setup for TPS2543EVM. Connect J2 to the PC either directly (insert J2 into
available/accessible PC USB port) or using any Type A Male to Type A Female USB v2.0 extension cable.
USB power and data are available at J3.
Figure 2. Typical TPS2543EVM Test Setup
5
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K001
K002
EVM Assembly Drawings and Layout Guidelines www.ti.com
4 EVM Assembly Drawings and Layout Guidelines
4.1 PCB Drawings
The following figures show component placement and layout of the EVM.
Figure 3. Top Side Placement
Figure 4. Top Side Routing
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K003
K004
www.ti.com EVM Assembly Drawings and Layout Guidelines
Figure 5. Layer Two Routing
Figure 6. Layer Three Routing
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K005
K006
EVM Assembly Drawings and Layout Guidelines www.ti.com
Figure 7. Figure 7. Bottom Side Routing
Figure 8. Bottom Side Placement
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www.ti.com EVM Assembly Drawings and Layout Guidelines
4.2 Layout Guidelines
•TPS2543 placement: Place the TPS2543 near the USB output connector and 150-µF OUT pin filter
capacitor. Connect the exposed pad to the GND pin and the system ground plane using an array of
vias.
•IN pin bypass capacitance: Place the 0.1-µF bypass capacitor near the IN pin and make the
connection using a low-inductance trace.
•DP-OUT/DM-OUT, DP-IN/DM-IN traces: Route these traces as controlled-impedance differential pairs
per the USB-2.0 specification. Minimize the use of vias in the high-speed data lines. Figure 7 provides
a good signal-routing example for the high-speed data traces. In this example, the data pairs are
routed as edge-coupled microstrips with nominal differential impedance of 90 Ω. The reference plane is
tied to GND and is shown in Figure 6. Ensure that the reference plane is void of cuts or splits above
the differential pairs to prevent impedance discontinuities.
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Bill of Materials www.ti.com
5 Bill of Materials
Table 5. TPS2543EVM Bill of Materials
REFDES Count Value Description Size Part Number Supplier
C1 1 10 µF Capacitor, ceramic, 10-V, X5R, 10% 0805 Std Std
C2, C4 2 0.1 µF Capacitor, ceramic, 50-V, X7R, 10% 0603 Std Std
C3 1 150 µF Capacitor, tantalum, low-ESR, 10-V, ±10% 7343 (D) TPSD157K010R0100 AVX
D1, D3 2 LN1271R Diode, LED, red, 10-mA, 0.4-mcd 0.114 ×0.049 inch (2.9 ×1.25 LN1271RTR Panasonic
mm)
D2 1 LN1371G Diode, LED, green, 10-mA, 2.6-mcd 0.114 ×0.049 inch (2.9 ×1.25 LN1371GTR Panasonic
mm)
J1 1 ED555/2DS Terminal block, 2-pin, 6-A, 3.5-mm 0.27 ×0.25 inch (6.86 ×6.35 ED555/2DS OST
mm)
J2 1 692 112 030 100 Connector, SMT, USB 3.0 plug with clip, type A 12 mm ×21 mm 692 112 030 100 Wurth
Elektronik
J3 1 692 122 030 100 Connector, SMT, USB 3.0 horizontal, type A 12 mm ×15 mm 692 122 030 100 Wurth
Elektronik
JP1, JP2 2 PEC02SAAN Header, male 2-pin, 100-mil spacing 0.100 inch (2.54 mm) ×2 PEC02SAAN Sullins
JP3 1 PEC05DAAN Header, male 2 ×5-pin, 100-mil spacing 0.100 inch (2.54 mm) ×5×2 PEC05DAAN Sullins
L1 1 370 ΩChoke, common-mode 0.050 ×0.080 inch (1.27 ×0805USB-372ML or Coilcraft or
2.03 mm) 744231371 Wurth
Elektronik
R1, R4, R14 3 2 kΩResistor, chip, 1/16-W, 1% 0603 Std Std
R2 1 16.9 kΩResistor, chip, 1/16-W, 1% 0603 Std Std
R3 1 80.6 kΩResistor, chip, 1/16-W, 1% 0603 Std Std
R5–R13 9 100 kΩResistor, chip, 1/16-W, 1% 0402 Std Std
TP1, TP2, TP9, 4 5012 Test point, white, through-hole 0.125 ×0.125 inch (3.18 ×5012 Keystone
TP10 3.18 mm)
TP3, TP4 2 5010 Test point, red, through-hole 0.125 ×0.125 inch (3.18 ×5010 Keystone
3.18 mm)
TP5, TP6 2 5016 Test point, SM 0.185 ×0.135 inch (3.81 ×5016 Keystone
3.43 mm)
TP7, TP8 2 5013 Test point, orange, through-hole 0.125 ×0.125 inch (3.18 ×5013 Keystone
3.18 mm)
U1 1 TPS2543RTE USB charging-port power switch controller with load QFN-16 TPS2540RTE TI
detect/status
U2 1 TPD2E001DZDR IC, low-capacitance 2-chan ±15-kV ESD-protection SOP TPD2E001DZDR TI
array
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