Texas Instruments UCC21551CQEVM-079 User manual

EVM User's Guide: UCC21551CQEVM-079
UCC21551CQEVM-079 Evaluation Module
Description
The UCC21551CQEVM-079 is a two copper layer
PCB containing multiple test points and jumpers
to fully evaluate the functionality of the UCC21551
gate driver. The EVM features PWM input control,
onboard adjustable power supply, sockets for discrete
FETs, external active clamp for low side protection,
bootstrapped high side power supply, negative gate
voltage capability, configurable deadtime switches,
EN/DIS jumpers, and socket for Wolfspeed XM3 SiC-
based half bridge power modules. The layout has
been optimized to minimize gate loop area for each
channel and placement of bypass capacitors allow for
clean and sharp signal reading with minimal noise
interference.
Features
• Variety of test points to help evaluate all of the gate
driver functions
• Onboard isolated adjustable bias supply
configured for 20 V
• Selectable dead time modes: overlap, interlock,
programmable
• Low side external active clamping circuit
• 16 V/-3V Zener negative voltage pulldown circuit
for SiC FETs
• Socket for Wolfspeed XM3 module
PCB Top Side
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1 Evaluation Module Overview
1.1 Introduction
The UCC21551CQEVM evaluation module is designed for evaluating TI’s UCC2155XX family of gate drivers.
The UCC2155XX is a 5.7-kVrms isolated dual-channel gate driver with 4-A source and 6-A sink peak current for
driving Si MOSFETs, IGBTs and WBG devices such as SiC and GaN transistors. This guide provides a complete
EVM schematic diagram, printed circuit board layout, bill of materials, test setup, and feature descriptions for
the UCC21551C. To evaluate other Iso-Drivers in the UCC2155XX family, TI recommends that the user read the
data sheet thoroughly before switching the part in the EVM covered by this user guide.
CAUTION
!
Caution Read the user's guide before use.
CAUTION
Caution Hot surface. Contact can cause
burns. Do not touch!
WARNING
Danger
Do not use EVM to test isolation
above VIOWM = 1414 VDC.
High voltage.
1.2 Kit Contents
• UCC21551CQEVM-079 two layer PCB
1.3 Specification
UCC21551CQEVM-079 primary function is to evaluate the UCC2155xx dual channel gate driver family. Multiple
test points enable monitoring of the different input and outputs of the gate driver for thorough performance
evaluation. The gate driver output can be configured to drive a capacitive loads for low voltage testing as well as
discrete MOSFETs in a halfbridge configuration.
1.4 Device Information
The UCC21551x-Q1 is an isolated dual channel gate driver family with programmable dead time and wide
temperature range. The device is designed with 4-A peak- source and 6-A peak-sink current to drive power
MOSFET, SiC, and IGBT transistors.
The UCC21551x-Q1 can be configured as two low- side drivers, two high-side drivers, or a half-bridge driver.
The input side is isolated from the two output drivers by a 5-kVRMS isolation barrier, with a minimum of 125-V/ns
common-mode transient immunity (CMTI).
Protection features include: resistor programmable dead time, disable feature to shut down both outputs
simultaneously, and integrated de-glitch filter that rejects input transients shorter than 5 ns. All supplies have
UVLO protection.
With all these advanced features, the UCC21551x- Q1 device enables high efficiency, high power density, and
robustness in a wide variety of power applications.
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1.5 General TI High Voltage Evaluation User Safety Guidelines
WARNING
Always follow TI’s set-up and application instructions, including use of all interface components within the
recommended electrical rated voltage and power limits. Always use electrical safety precautions to help ensure
your personal safety and the safety of those working around you. Contact TI’s Product Information Center http://
support/ti./com for further information.
Save all warnings and instructions for future reference.
Failure to follow warnings and instructions can result in personal injury, property damage, or death due
to electrical shock and/or burn hazards.
The term TI HV EVM refers to an electronic device typically provided as an open framed, unenclosed printed
circuit board assembly. It is intended strictly for use in development laboratory environments, solely for qualified
professional users having training, expertise, and knowledge of electrical safety risks in development and
application of high-voltage electrical circuits. Any other use and/or application are strictly prohibited by Texas
Instruments. If you are not suitably qualified, you must immediately stop from further use of the HV EVM.
•Work Area Safety:
– Maintain a clean and orderly work area .
– Qualified observers must be present anytime circuits are energized.
– Effective barriers and signage must be present in the area where the TI HV EVM and the interface
electronics are energized, indicating operation of accessible high voltages can be present, for the purpose
of protecting inadvertent access.
– All interface circuits, power supplies, evaluation modules, instruments, meters, scopes and other related
apparatus used in a development environment exceeding 50 VRMS/75 VDC must be electrically located
within a protected Emergency Power Off (EPO) protected power strip.
– Use a stable and non-conductive work surface.
– Use adequately insulated clamps and wires to attach measurement probes and instruments. No freehand
testing whenever possible.
•Electrical Safety:
As a precautionary measure, a good engineering practice is to assume that the entire EVM can have fully
accessible and active high voltages.
– De-energize the TI HV EVM and all the inputs, outputs, and electrical loads before performing any
electrical or other diagnostic measurements. Confirm that TI HV EVM power has been safely de-
energized.
– With the EVM confirmed de-energized, proceed with required electrical circuit configurations, wiring,
measurement equipment hook-ups and other application needs, while still assuming the EVM circuit and
measuring instruments are electrically live.
– When EVM readiness is complete, energize the EVM as intended.
WARNING
WARNING: While the EVM is energized, never touch the EVM or the electrical circuits as
the EVM or electrical circuits can be at high voltages capable of causing electrical shock
hazard.
•Personal Safety:
– Wear personal protective equipment, for example, latex gloves and/or safety glasses with side shields or
protect EVM in an adequate lucent plastic box with interlocks from accidental touch.
•Limitation for Safe Use:
– EVMs are not to be used as all or part of a production unit.
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The EVM is designed for professionals who have received the appropriate technical training, and is designed
to operate from an AC power supply or a high-voltage DC supply. Please read this user guide and the safety-
related documents that come with the EVM package before operating this EVM.
CAUTION
!
Do not leave the EVM powered when unattended.
WARNING
High Voltage! Electric shock is possible when connecting board to live wire. Board must be handled
with care by a professional.
For safety, use of isolated test equipment with overvoltage and overcurrent protection is highly
recommended.
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2 Hardware
2.1 Power Requirements
Table 2-1. UCC21551CQEVM-079 Electrical Specifications
Description Min Typ Max Units
VIN Enable for UCC21551 and UCC14240 3.3 5 5 V
VBIAS Primary side input voltage UCC14240 21 24 27 V
VDDB
VDDA
UCC21551C output bias supply voltage
See data sheet for UCC2155XX variants 13.5 25 V
Fs Switching frequency 0 500 KHz
DC Voltage on DC+ for half bridge application 0 800 V
Tj Operating junction temperature -40 150 °C
2.2 Header Information
Table 2-2. Headers Description
Header Marker Description
J5 Dead time setting
J7 Gate driver enable/disable
J20 Bias supply enable/disable
J22 Unused
J23 PWM mode toggle
2.3 Jumper Information
Table 2-3. Jumper Configurations
Header Jumper Settings Default
J5
VCC1-DT
DT-GND
Unconnected
DT-GND: enables gate driver interlock mode
J7 XEN-GND
XEN-VCC1
XEN-VCC1: connects VCC1 to UCC21551 EN pin,
enabling gate driver
J20 VCC1-ENA
ENA-GND VCC1-ENA: enables UCC14240 bias supply
J23 Connected
Unconnected Unconnected: disables single input PWM mode
2.4 Connectors Information
Table 2-4. Connectors Description
Connector Description
J18 VCC1 Input for UCC14240 3.3-5V
J21 VIN Input for UCC14240 21-27V
2.5 Interfaces Information
Table 2-5. Interfaces Description
Interface Description
J8 DC+
J9 Switch node
J12 DC-
J16A XM3 Wolfspeed Socket CHA Gate
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Table 2-5. Interfaces Description (continued)
Interface Description
J16B XM3 Wolfspeed Socket CHA VSSA
J17A XM3 Wolfspeed Socket CHB Gate
J17B XM3 Wolfspeed Socket CHB VSSB
Q1 Socket for discrete FET1
Q2 Socket for discrete FET2
2.6 Test Points
Table 2-6. Test Point Description
Test Point Test Point Board Marker Description
TP1 VBIAS/VCC1 EN for UCC14240
TP2 INA Input for channel A
TP3 INB Input for channel B
TP4 VDDA Output side channel A supply
TP5 GND Input side ground
TP6 GND Input side ground
TP7 GND Input side ground
TP8 VSSA Output side channel A ground
TP9 VSSB Output side channel B ground
TP11 XEN Test point to apply an external enable signal
TP12 PG Fault pin for detecting fault status for UCC14240
TP15 ENA Test point for measuring UCC14240 enable signal
TP16 VDDB Output side channel B supply
TP17 VIN Test point for primary supply for UCC14240 (21V-27V)
TP18 GND Input side ground
TP19 VGA Q1 FET gate
TP21 VGB Q2 FET gate
J1 VIN MMCX pad for primary supply for UCC14240 (21V-27V)
J2 VDDA MMCX pad for output side channel A supply
J3 OUTA MMCX pad for channel A output
J4 VGA MMCX pad for Q1 gate
J6 DT MMCX pad for Deadtime pin
J10 INA MMCX pad for input to channel A
J11 INB MMCX pad for input to channel B
J13 VDDB MMCX pad for output side channel B supply
J14 OUTB MMCX pad for channel B output
J15 VGB MMCX pad for Q2 gate
J19 VDDB MMCX pad for output low side supply
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3 Implementation Results
3.1 Evaluation Setup
This section describes the default EVM configurations and recommended test set up for the UCC21551-Q1
EVM.
Equipment
The following equipment is recommended for testing the EVM:
• One DC supply capable of 5 V/0.5A, for example: Keysight E3634A.
• One DC supply capable of 24 V/0.5A, for example: Keysight E3634A.
• One Arbitrary Function Generator, dual channel, for example: Tektronix AFG3102A
• One Oscilloscope, at least 3 channels, bandwidth 200 MHz or above, for example, Tektronix MDO3054 or
TDS3054C.
• Three passive oscilloscope probes, bandwidth 200 MHz or above. For example, TPP1000 like probe with a
ground spring.
• 4X BNC to Grabber Cables for input and supply connections.
• Banana plug connector.
Equipment Configurations
•DC Power Supply Settings
–DC Supply 1:
• Voltage setting: 5 V
• Current limit: 0.5A
–DC Supply 2:
• Voltage setting: 24 V
• Current limit: 0.5A
•Function Generator Settings
–Function: Pulse
–CH1: High: 5 V, Low: 0 V
–CH2: High: 5 V, Low: 0 V
•Oscilloscope Settings
–CH1-CH3:
• DC coupling
• Highest bandwidth setting available
• Termination 1M or automatic
• Probe scale: 10X or auto
Equipment Setup
•Jumper Connections
–J7: Shunt XEN to VCC
–J20: Shunt ON to EN
–J5: Shunt DT to GND
–SDT_DT1: All switches in the left most position
•Oscilloscope Connections
–CH1: VGA to VSSA
–CH2: VGB to VSSB
–CH3: VDDB to VSSB
•Function Generator
–CH1: INB to GND
–CH2: INA to GND
•Power Supply
–DC Supply 1: J18
–DC Supply 2: J21
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If testing the EVM with FETs, then populate Q1 and Q2 or the XM3 connector. If testing the EVM without FETs,
then place a banana plug connector between SW and DC-. See Figure 3-1 for a visual of the default test
connections.
Figure 3-1. Default Connections Without Load
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3.2 Performance Data and Results
Test Procedure
•Power Up
1. Before proceeding make sure the EVM and all equipment is setup as described in section Equipment
Configurations and Equipment Setup.
2. Turn on the 5 V and 24 V power supply. Probing VDDB(TP16)-VSSB(TP9) measures 20 V. Probing
VCC1(TP1)-GND(TP6) measures 5 V.
3. Turn on both channels of the function generator.
4. Use any probe of choice to verify that there is a 5 KHz, 5 V, pulse on INA and INB each with respect to
GND.
5. Probing VGA-VSSA and VGB-VSSB shows a PWM output signal from the gate driver going up to +16V
when HIGH and -3V when LOW as shown in Figure 3-2.
Figure 3-2. Power-up Test: Switching at 5 kHz
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Deadtime Configuration
The UCC21551 has 3 dead time modes that are selectable with the UCC21551CQEVM. Those modes are
Interlock, Programmable, and Overlap.
•Interlock Mode: Interlock mode sets a minimum delay of approximately 5 ns between gate driver outputs to
prevent the channels from overlapping. This mode is initiated when the dead time pin is grounded (Shunting
J5 to DT-GND). The dead time is defined as the delay between 90% of the falling edge of the first output and
10% of the rising edge of the second output. Timing is illustrated in Figure 3-3. See Figure 3-4for an example
of Interlock mode.
Figure 3-3. Timing Diagram
Figure 3-4. Interlock Mode
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•Programmable Mode: Programmable dead time mode is activated when the dead time pin is connected
to a resistor between 1.7K-100K Ohms to ground. To activate this mode on the EVM, leave jumper J5
unconnected. To adjust the deadtime, use the switches on SDT_DT1. By default, switch the switches to the
left. To program the dead time, move the switch to the right. The available resistors allow for various dead
time settings. Additional values can be created by toggling multiple switches at the same time, which has the
effect of paralleling the resistors. Figure 3-5 is an example output waveform with 5 kΩ resistance.
Figure 3-5. Programmable Mode: 5 kΩ RDT Resistor Selection
•Overlap Mode: Overlap mode disables the deadtime circuitry to allow the outputs to overlap. To select this
mode, shunt jumper J5 to VCC-DT. An example of overlap mode is depicted in Figure 3-6.
Figure 3-6. Overlap Mode
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Single Input PWM
Single input PWM allows the user to control channel A and B with a single PWM signal. On the EVM, this is
accomplished with a BJT inverter circuit that takes the incoming channel A signal inverts and forwards to the
input pin of channel B. To enable this mode, shunt jumper 23. Note that in this mode, there is an unavoidable
intrinsic dead time of 1us imposed by the BJT switching delay. This only occurs between the falling edge of
VGA and the rising edge of VGB. If the deadtime circuit of the UCC21551 is enabled, then the interlock and
programmable deadtime modes only affects the rising edge of VGA and the falling edge of VGB. This is because
the 1us deadtime caused by the BJT is happening in parallel with the gate driver deadtime instead of adding. In
Figure 3-7 and Figure 3-8, the driver is in interlock mode and both channels are switching at the same frequency.
As the frequency increases, the output pulses eventually become smaller than the 1us delay. Figure 3-8 is
depicting switching at 200 kHz, at which about half of INB’s signal is lost.
Figure 3-7. Switching at 5 kHz
Figure 3-8. Switching at 200 kHz
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Active Clamp
The Active clamp is a protection circuit added to channel B of the UCC21551CQEVM. This circuit helps keep the
gate low when the driver is not powered or if there is an unintended voltage rise coupling to VGB. If there is a
rise in the voltage on VGB greater than the voltage on OUTB, then the PNP BJT turns on and provides a path
for current to flow to ground instead of into the FET gate, which can turn the FET on. The active clamp clamps
voltage transients on VGB to approximately 1.2V. This is shown in Figure 3-9.
Figure 3-9. Active Clamp Clamping an Unintended Rise on VGB
Onboard Adjustable Bias Supply (UCC14240)
The UCC14240 is a 1.5W isolated adjustable bias supply configured to supply 20 V to the low side (channel B)
of the gate driver. The user can change this output voltage to accommodate different versions of UCC2155XX
drivers by changing resistor R28. For more information on how to adjust the output voltages, refer to the
UCC14240-Q1 Component Calculator and the application note UCC14240-Q1 Simplifies HEV, EV, Bias Supply
Design for Isolated Gate Drivers.
Negative Bias Supply Generation
The UCC21551CQEVM is equipped with a zener diode circuit on both gate driver output channels. This takes
the 20 V VDD supply and splits into +16/-3V. Applying a negative bias to the gate of MOSFET mitigates the
system from having unintentional turn on of the MOSFET caused by current flowing through the miller capacitor
during high dv/dt switching. The negative pulldown circuit needs multiple cycles to reach steady state. Not all
tests, such as a double pulse test, feature a negative voltage on the gate when performed.
High Voltage Double Pulse Test
This UCC21551CQEVM-079 was designed to work with voltages of up to 800 V. A low side double pulse test
was performed to test the high voltage capability of the EVM. This test consisted of a Wolfspeed XM3 evaluation
board which includes a SiC FET module and DC bus capacitor. The inductor is connected across the high side
FET so the body diode can free-wheel the inductor current while the low side FET switches.
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Figure 3-10. UCC21551CQEVM-079 Connected to SiC Wolfspeed XM3 Module
If the Wolfspeed XM3 evaluation board is not in use, then the user has the capability of connecting DC bus link
capacitors to the board by using connectors J8 (DC+) and J12 (DC-).
Figure 3-11 shows the waveforms taken of an 800 V double pulse test. The signals are described below:
• Red: ID, inductor current
• Blue: Vds, drain to source voltage of the low side FET switching
• Yellow: Vg, gate voltage of the low side FET
• Green: Vin, channel B input pulse signal
The peak current measured during this test measured 522 amps and the peak voltage across the low side fet
measured 977 volts.
Figure 3-11. Double Pulse Test Results at 800 V
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4 Hardware Design Files
4.1 Schematics
1INA
UCC21551CQDWKRQ1
2INB
VCCI
3
4GND
5EN
DT
6
7NC
8VCCI VSSB 9
OUTB 10
11
VDDB
VSSA 14
OUTA 15
16
VDDA
XU1
TP7
GND
10pF
0603
C4
100
R2 INA
TP5
GND 10pF
0603
C3
100
R1 INB
TP3
INB
10.4k
R4
10.4k
R3
50V
10pF
C10
1
2
3
J7
VCC1
GND
GND
EN
2.2nF
50V
C9
1
P
0.4k
R11
DN
1
2
3
J5
VCC1
GND
GND
DT
GNDGNDGND GND
63
1 8
2 7
54
SDT_DT1
DT_S
100k
R15
EN
DT
INB
INA
GND
1µF
25V
C1
100nF
50V
C2
VCC1
VCC1
GNDGND
GND
VCC1
VDDB
VSSB
VSSA
VDDA
100nF
50V
C6
100nF
50V
C13
VDDB
VSSB
VSSA
VDDA
10.2k
R20
VSSB
1µF
50V
C7
1µF
50V
C14
VDDA
1
2
J2
DNP
3 4 5
VDDA
1
2
J3
DNP
3 4 5
OUTA
1
2
J4
DNP
3 4 5
VGA
1
2
DNP
3 4 5
J13
VDDB
1
2
DNP
3 4 5
J14
OUTB
1
2
DNP
3 4 5
J15
VGB
VDDB
VDDA
VSSA
VSSB VSSB
OUTB
OUTA VGA
OUTB
OUTA
VSSA
VSSB
VGB
VSSA
1
2
DNP
3 4 5
J10
INA
1
2
DNP
3 4 5
J11
INB
1
2
J6
DNP
3 4 5
DT
INA INB
GND
GND
100
R10
I/O2 I/O1
I/O3
VGA
DC+
R5
0
DNP
INA
INB
24.9
R22
24.9
R23
24.9
R24
24.9
R7
24.9
0
R8
R9
1
3 2
Q1
DNP
1
STW42N65M5
3 2
Q2
DNP STW42N65M5
1
3
J16A
ESQ-102-33-L-D
2
4
J16B
ESQ-102-33-L-D
1
3
J17A
ESQ-102-33-L-D
2
4
J17B
ESQ-102-33-L-D
High side Low side
VGA VSSA VGB VSSB
3.9V
D1
SZMM3Z3V9ST1G
1µF
50V
C8
J8
DC+
DNP
J9
SW
DNP
4.99
R21
4.99
R13
VGB
40V
D3
40V
D4
BLM3L 11 SN500SZ1L
BLM3L 12 SN500SZ1L
DT resistor selection J12
DC-
DNP
VSSA
10.2k
R14
2.2nF
50V
DNPC16
OUTB
VGB
VSSB
Active pull down
SiC module sockets
INA and INB inputs, plus pwm input
optional INA/INB short
TP4
TP8
External Enable option
Bootstrap
20.0k
R17
4.99k
R18
TP11
XEN
3.9
R32
31
2Q4
2SC5585TL
GND
1nF
16V
C24
1.00k
R25
VCC1 J23
INB
TP2
3.9V
D7
SZMM3Z3V9ST1G
35V
10uF
C12
3
1
2
Q3
NSS40200LT1G
TP14
SW
DNP
2.0
R12
2.0
R19
24.9
R6
2 1
D6
GB02SLT12-214
5.00k
R33
1µF
50V
C18
100
R31
TP19
TP21
2.00k
R16
Figure 4-1. UCC21551C Schematic
VSSB
VDDB
GND
21V<VIN<27V
+15V
2.2nF
50V
3.3V<Vbias<5V
C23
3
2
1
J20
ENA
50V
0.1uF
C28
TP16
TP17
TP18
NOTE:
TP12
TP15
0.1%
10k
R30
VDDB
VSSB
VIN
GND
VCC1
GND
GND
VCC1
(1) C6 not installed: +15V/-5V configuration
(2) C6 installed: +20V/-5V configuration
ENA
/PG
GND
GND VSSB
VSSB
FBVDD
ENA
100k
VEE/VEEA Ground Tie
R26
VSSB
TP9
VSSB
FBVDD
2
1
J18
1
2
3.3V<VBIAS<5V
VIN
6
J21 21V<VIN<27V
VIN
7
VEE 26
VEE 27
VDD 28
29
VDD
RLIM 32
FBVEE 33
FBVDD 34
VEEA 35
5GNDP
1GNDP
PG
3
2GNDP
ENA
4
8GNDP
9GNDP
10 GNDP
GNDP
11
GNDP
12
13
14 GNDP
GNDP
15 GNDP
GNDP
16
GNDP
17
18 GNDP VEE 19
VEE 20
VEE 21
22
VEE
VEE 23
VEE 24
VEE 25
VEE 30
VEE 31
36
VEE
U1
UCC14240DWNQ1
1
2 3
4
5
J1
VIN
DNP
1
5 4 3 2
J19
VDDB
DNP
TP1
TP6
VDDB
1.00k
R27
35V
10uF
C21
2.2nF
50V
Cout1 and cout2
C26
X7R
330pF
C5
100nF
50V
C15
35V
10µF
C11
4.75
R29
GND
35V
10µF
C27
35V
10µF
C17
50V
100nF
C22
50V
100nF
C25
70.6k
R28
J22
Figure 4-2. UCC14240 Schematic
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4.2 PCB Layouts
Figure 4-3. PCB Top Layer
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Figure 4-4. PCB Bottom Layer
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4.3 Bill of Materials (BOM)
Table 4-1. Bill of Materials
Designator Qty Description Part Number Manufacturer
C1 1 CAP, CERM, 1 µF, 25 V,+/- 10%, X7R,
AEC-Q200 Grade 1, 0603 CGA3E1X7R1E105K080AC TDK
C2, C6, C13, C15,
C22, C25 6CAP, CERM, 0.1 uF, 50 V, +/- 5%, X7R, 0603 C0603C104J5RACTU Kemet
C3, C4, C10 3 CAP, CERM, 10 pF, 50 V, +/- 5%, C0G/
NP0, 0603 GRM1885C1H100JA01D MuRata
C5 1 CAP, CERM, 330 pF, 100 V, +/- 10%,
X7R, 0603 GRM188R72A331KA01D MuRata
C7, C8, C14, C18 4 CAP, CERM, 1 uF, 50 V, +/- 10%, X7R,
0805 C2012X7R1H105K085AC TDK
C9, C23, C26 3 CAP, CERM, 2200 pF, 50 V, +/- 10%,
X7R, 0603 C0603C222K5RACTU Kemet
C11, C17, C27 3 CAP, CERM, 10 µF, 35 V,+/- 10%, X5R,
0805 GMK212BBJ106KG-T Taiyo Yuden
C12, C21 2 CAP, CERM, 10 uF, 35 V, +/- 10%, X7R,
AEC-Q200 Grade 1, 1206_190 CGA5L1X7R1V106K160AC TDK
C24 1 1000 pF ±10% 16 V Ceramic Capacitor
X7R 0603 (1608 Metric) CC0603KRX7R7BB102 YAGEO
C28 1 CAP, CERM, 0.1 uF, 50 V, +/- 10%, X7R,
AEC-Q200 Grade 1, 0402 GCM155R71H104KE02D MuRata
D1, D7 2 Diode, Zener, 3.9 V, 300 mW, AEC-
Q101, SOD-323 SZMM3Z3V9ST1G ON Semiconductor
D3, D4 2 Diode, Schottky, 40 V, 1 A, MicroSMP MSS1P4-M3/89A Vishay-Siliconix
D6 1 Diode Silicon Carbide Schottky 1200 V 2
A (DC) Surface Mount DO-214AA GB02SLT12-214 GeneSiC Semiconductor
FID1, FID2, FID3 3 Fiducial mark. There is nothing to buy or
mount. N/A N/A
J5, J7 2 Header, 100mil, 3x1, Gold, TH TSW-103-07-G-S Samtec
J16, J17 2 4 Position Elevated Socket Connector
Through Hole ESQ-102-33-L-D Samtec
J18, J21 2 Terminal Block, 2x1, 3.81mm, 24-16
AWG, 10 A, 300VAC, TH 691214310002 Wurth Elektronik
J20 1 Header, 100mil, 3x1, Tin, TH PEC03SAAN Sullins Connector
Solutions
J22, J23 2 Header, 2.54mm, 2x1, TH 961102-6404-AR 3M
L1, L2 2 Ferrite Bead, 50 ohm @ 100 MHz, 12 A,
1206 BLM31SN500SZ1L MuRata
LBL1 1 Thermal Transfer Printable Labels,
0.650" W x 0.200" H - 10,000 per roll THT-14-423-10 Brady
Q3 1 Transistor, PNP, 40 V, 2 A, AEC-Q101,
SOT-23 NSS40200LT1G ON Semiconductor
Q4 1 Transistor, NPN, 12 V, 0.5 A, SOT-416 2SC5585TL Rohm
R1, R2, R10, R31 4 RES, 100, 0.5%, 0.1 W, 0805 RR1220P-101-D Susumu Co Ltd
R3, R4 2 RES, 10.4 k, 0.5%, 0.1 W, 0603 RT0603DRE0710K4L Yageo America
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Table 4-1. Bill of Materials (continued)
Designator Qty Description Part Number Manufacturer
R6, R7, R8, R22, R23,
R24 6RES, 24.9, 1%, 0.063 W, AEC-Q200 Grade 0, 0402 CRCW040224R9FKED Vishay-Dale
R9 1 RES, 0, 0%, 0.25 W, AEC-Q200 Grade
0, 0603 PMR03EZPJ000 Rohm
R12 1 RES, 2.0, 5%, 0.125 W, 0805 CRCW08052R00JNEA Vishay-Dale
R13, R21 2 RES, 4.99, 1%, 0.125 W, AEC-Q200
Grade 0, 0805 CRCW08054R99FKEA Vishay-Dale
R14, R20 2 RES, 10.2 k, 0.5%, 0.1 W, 0805 RR1220P-1022-D-M Susumu Co Ltd
R15 1 RES, 100 k, 1%, 0.125 W, 0805 CRG0805F100K TE Connectivity
R16 1 RES, 2.00 k, 0.01%, 0.1 W, 0603 Y16362K00000T9W Vishay Foil Resistors
R17 1 RES, 20.0 k, 0.5%, 0.1 W, 0805 RR1220P-203-D Susumu Co Ltd
R18 1 RES, 4.99 k, 1%, 0.1 W, 0603 CRCW06034K99FKEAC Vishay-Dale
R19 1 RES, 2.0, 5%, 0.125 W, AEC-Q200
Grade 0, 0805 CRCW08052R00JNEA Vishay-Dale
R25 1 RES, 1.00 k, 0.1%, 0.1 W, 0603 RT0603BRD071KL Yageo America
R26 1 RES, 100 k, 5%, 0.1 W, AEC-Q200
Grade 0, 0402 ERJ-2GEJ104X Panasonic
R27 1 RES, 1.00 k, 1%, 0.125 W, AEC-Q200
Grade 0, 0805 ERJ-6ENF1001V Panasonic
R28 1 RES, 70.6 k, 0.5%, 0.1 W, 0603 RT0603DRE0770K6L Yageo America
R29 1 RES, 4.75, 0.5%, 0.1 W, 0603 RT0603DRE074R75L Yageo America
R30 1
Res Thin Film 0603 10K Ohm 0.1%
1/10W ±10ppm/°C Molded SMD SMD
Punched Carrier T/R
ERA-3ARB103V Panasonic
R32 1 RES, 3.9, 5%, 0.25 W, AEC-Q200 Grade
0, 1206 CRCW12063R90JNEA Vishay-Dale
R33 1 RES, 5.00 k, 0.1%, 0.2 W, 0805 PNM0805E5001BST5 Vishay Thin Film
SDT_DT1 1 Switch, SPST, Slide, Off-On, 4 Pos, 0.1A,
20 V, SMD 219-4MST CTS Electrocomponents
TP1, TP4, TP16, TP17,
TP19, TP21 6 Test Point, Multipurpose, Red, TH 5010 Keystone Electronics
TP2, TP3, TP11 3 Test Point, Multipurpose, White, TH 5012 Keystone Electronics
TP5, TP6, TP7, TP8,
TP9, TP18 6 Test Point, Multipurpose, Black, TH 5011 Keystone Electronics
TP12, TP15 2 Test Point, Multipurpose, Yellow, TH 5014 Keystone Electronics
U1 1 2W, 24V-Vin, 25V-Vout, High-Efficiency,
>2. 5 kVRMS Isolated DC-DC Converter UCC14240DWNQ1 Texas Instruments
XU1 1 Automotive 4-A, 6-A, Reinforced Isolation
Dual-Channel Gate Driver UCC21551CQDWKRQ1 Texas Instruments
C16 0 CAP, CERM, 2200 pF, 50 V, +/- 10%,
X7R, 0603 C0603C222K5RACTU Kemet
H1, H2, H3, H4 0 Machine Screw, Round, #4-40 x 1/4,
Nylon, Philips panhead NY PMS 440 0025 PH B&F Fastener Supply
H5, H6, H7, H8 0 Standoff, Hex, 0.5"L #4-40 Nylon 1902C Keystone
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Table 4-1. Bill of Materials (continued)
Designator Qty Description Part Number Manufacturer
J1, J2, J3, J4, J6, J10,
J11, J13, J14, J15, J19 0 Connector, MMCX 50 ohm, TH MMCX-J-P-H-ST-TH1 Samtec
J8, J9, J12 0 Standard Banana Jack, Uninsulated, 15
A108-0740-001 Cinch Connectivity
Q1, Q2 0 MOSFET, N-CH, 650 V, 33 A, TO-247 STW42N65M5 STMicroelectronics
R5 0 RES, 0, 0%, 0.25 W, AEC-Q200 Grade
0, 0603 PMR03EZPJ000 Rohm
R11 0 RES, 10.4 k, 0.5%, 0.1 W, 0603 RT0603DRE0710K4L Yageo America
TP14 0 Fuse Holder, 5AG, TH 3566 Keystone
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