Texas Instruments TLV1544EVM User manual

TLV1544EVM Evaluation
Module for the TLV1544
10ĆBit ADC
1998 Mixed-Signal Products
User’s Guide

Printed in U.S.A.
08/98 SLAU014

TLV1544EVM Evaluation Module for
the TLV1544 10-Bit ADC
User’s Guide
Printed on Recycled Paper
Literature No. SLAU014
August 1998

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Copyright 1998, Texas Instruments Incorporated

Information About Cautions and Warnings
iii
Read This First
Preface
Read This First
About This Manual
This User’s Guide describes the characteristics, operation, and use of the
TLV1544EVM Evaluation Moduale for the TLV1544 10-Bit Analog-to-Digital
Converter (ADC).
How to Use This Manual
This document contains the following chapters:
- Chapter 1 Overview
- Chapter 2 Physical Description
- Chapter 3 Circuit Description
- Chapter 4 Operation
Information About Cautions and Warnings
This book may contain cautions and warnings.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you.

Related Documentation From Texas Instruments
iv
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.
Related Documentation From Texas Instruments
To obtain a copy of any of the following TI documents, call the Texas
Instruments Literature Response Center at (800) 477–8924 or the Product
Information Center (PIC) at (972) 644–5580. When ordering, please identify
the book by its title and literature number if possible.
Data Sheets:
- TLV1544CD Literature No. SLAS139
- SN74HC244IDW Literature No. D2684
- TPS7101QD Literature No. SLVS092
- TLV2432AID Literature No. SLOS168
- TLE2027ACD Literature No. SLOS192
- TL1431CD Literature No. SLVS062
- SN74AHCT1G04 Literature No. SCLS319
Application Reports:
- Interfacing the TLV1544 Analog-to-Digital Converter to the TMS320C50
DSP
, literature number SLAA025.
FCC Warning
Thisequipmentisintendedforuseinalaboratorytestenvironmentonly.Itgen-
erates,uses, andcan radiateradiofrequency energyand hasnotbeen tested
for compliance with the limits of computing devices pursuant to subpart J of
part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other en-
vironmentsmay causeinterference withradiocommunications, inwhich case
the user at his own expense will be required to take whatever measures may
be required to correct this interference.
Trademarks
TI is a trademark of Texas Instruments Incorporated.
SPI and QSPI are trademarks of Motorola, Inc.

If You Need Assistance
v
Read This First
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book.

vi

Running Title—Attribute Reference
vii
Chapter Title—Attribute Reference
Contents
1 Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Purpose 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 EVM Basic Function 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Power Requirements 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 I/O CLK Requirements 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 I/O Interface Connector Provisions 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Timing and Signal Requirements 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 TLV1544EVM Operational Procedure 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Physical Description 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 PCB Layout 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Component List 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Circuit Description 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Schematic Diagram 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Circuit Function 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Inputs 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 A0 – Voltage Variable Analog Input (Potentiometer) 3-3. . . . . . . . . . . . . . . . . . . . . .
3.2.3 A1 – External Input With Voltage Follower Buffer 3-3. . . . . . . . . . . . . . . . . . . . . . . .
3.2.4 Unbuffered Analog Inputs 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.5 Power 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.6 Voltage Reference Generation 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.7 Test Connector 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.8 Jumper Arrangement 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Operation 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 TLV1544 Overview 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 Description 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2 Timing Diagrams 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.3 TLV1544 Signal State for Microprocessor and DSP 4-5. . . . . . . . . . . . . . . . . . . . . .
4.1.4 TLV1544 Terminal Functions 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Microprocessor Serial Interface 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 DSP Interface 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 TLV1544 to TMS320C50 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Grounding Considerations A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1 Printed Circuit Board Grounding Considerations A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Running Title—Attribute Reference
viii
Figures
2–1 PCB Layout 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 PCB Layout 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 PCB Layout 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 PCB Layout 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 PCB Layout 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 EVM Schematic Diagram 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 Generation of AVdd/2 with Buffer for Channel A1 Input Biasing with JP6 Removed 3-4. . . .
4–1 Functional Block Diagram 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 Microprocessor Interface Timing (Normal Sample Mode, INV CLK = High) 4-3. . . . . . . . . . . .
4–3 Microprocessor Interface Timing (Normal Sample Mode, INV CLK = Low) 4-3. . . . . . . . . . . .
4–4 DSP Interface Timing (16-Clock Transfer, Normal Sample Mode, INV CLK = High) 4-4. . . .
4–5 DSP Interface Timing (16-Clock Transfer, Normal Sample Mode, INV CLK = Low) 4-5. . . .
4–6 Schematic Diagram 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
1–1 Maximum I/O CLK Frequency 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 Component List 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 Test Connector J7 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 TLV1544 Serial Interface Modes 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 Terminal Functions 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1
Overview
Overview
ThischaptergivesageneraloverviewoftheTLV1544EVMEvaluationModule
(EVM),anddescribessomeofthefactorsthatmustbeconsideredinusingthe
module.
Topic Page
1.1 Purpose 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 EVM Basic Function 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Power Requirements 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 I/O CLK Requirements 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 I/O Interface Connector Provisions 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Timing and Signal Requirements 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 TLV1544EVM Operational Procedure 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1

Purpose
1-2
Overview
1.1 Purpose
The TLV1544EVM Evaluation Module (EVM) provides a platform for
evaluating the TLV1544 10-Bit Analog-to-Digital Converter (ADC) under
various signal, reference, and supply conditions.
1.2 EVM Basic Function
Thereare fouranaloginputs tothe TLV1544EVM, threeofthese areavailable
forexternalinputsthroughBNCconnectors.Theinternalanaloginputconsists
of an operational amplifier with a potentiometer for observing simple dc
measurements.
Thereference voltagecan beselectedby usingthe on-boardjumpersand the
switch, SW1. The reference input can be the supply voltage, an onboard gen-
erated absolute reference or an externally generated reference voltage.
An SN74HC244 buffers the digital I/O signals to the output header and test
connector.

Power Requirements
1-3
Overview
1.3 Power Requirements
The EVM operates properly over a balanced input voltage range of ±10 volts
maximumto±7voltsminimum.Thepowersupplyandexternallyappliedrefer-
encevoltageshouldbesuppliedtotheEVMthroughshieldedtwisted-pairwire
for best performance. This type of power cabling minimizes any stray or tran-
sient pickup from the higher frequency digital circuitry.
Voltage Limits
Exceeding the ±10-volt maximum can damage EVM components.
Undervoltagemaycauseimproperoperationof the bipolar op amp
channel A1, depending on the application. The positive supply can
be lowered to 6 volts and the EVM will maintain the 5-V supply.
1.4 I/O CLK Requirements
The I/O CLK can go up to 10 MHz for most of the voltage range when fast I/O
is possible. The maximum I/O CLK is limited to 2.8 MHz for a supply voltage
range from 2.7 V. Table 1–1 lists the maximum I/O CLK frequencies for all dif-
ferent supply voltage ranges. This also depends on input source impedance.
For example, I/O CLK speed faster than 2.39 MHz is achievable if the input
source impedance is less than 1 kΩ.
Table 1–1.Maximum I/O CLK Frequency
VCC Maximum Input
Resistance (Max) Source Impedance I/O CLK
27V
5K
1 kΩ2.39 MHz
2
.
7
V
5
K
100 Ω2.81 MHz
45V
1K
1 kΩ7.18 MHz
4
.
5
V
1
K
100 Ω10 MHz

I/O Interface Connector Provisions
1-4
Overview
1.5 I/O Interface Connector Provisions
The connector interface is versatile allowing different connection
arrangements depending on the user selected interface. A 12-position single
inline male connector, J5, is hard wired to the input/output signals of the
TLV1544throughtheSN74HC244.J6isadualrow,24positionheader,soany
dual row 100 mil center connector can be used up to 24 pins. J5 and J6 are
separated by a jumper row that allows J6 to be user configured for the
appropriate external interface. The schematic shows the signal arrangement
for J5. Either J5 or J6 can easily be used with the corresponding male ribbon
cable plug.
The two rows of plated-through holes, designated as JPA shorting jumpers,
allow the on board signals to connect externally in a variety of user defined
selections. Using these jumpers, the TLV1544EVM I/O signals can be conve-
nientlyconnected toan existinghardware(DSP EVMs,microprocessor EVM,
micro-controller EVMs, etc.) by appropriate jumper placement.
When using J6, the clock lines should have a ground line on either side in the
ribbon cable to minimize cross-talk. If possible every other conductor in the
ribbon cable should be grounded.
1.6 Timing and Signal Requirements
The signal timing necessary is shown in Chapter 4, Figures 4–2 through 4–5
for the various processor options.

TLV1544EVM Operational Procedure
1-5
Overview
1.7 TLV1544EVM Operational Procedure
SomesignalsetuporsoftwareisrequiredfortheTLV1544EVM.TheTLV1544
data sheet provides the timing requirements and the application report (litera-
ture number SLAA025) supplies an example of software using the
TMS320C50 DSP. Once the input requirements are completed, the operating
procedures for the TLV1544EVM are as follows.
- Connect ±7 to ±10 V and ground to the V+, V–, and GND terminals of J1.
These terminals are marked on the bottom side of the EVM. Ensure that
JP6 is shorted to establish zero volts as the operating point for the bipolar
operational amplifier.
SW1 can select 5-V VCC or 2.7-V VCC. The 2.7 volt operation should be
used only with a host interface that provides 3-V nominal or less input
signals to the EVM.
- FormostDSPoperation, JP5 isopenand formostmicroprocessor opera-
tion, JP5 is shorted. The INV CLK terminal condition is controlled by this
jumper and therefore, the clocking edge that is used for data input.
- The analog input that is connected to the TLV1544 is determined by soft-
wareandanyinputcanbeselectedfortesting.Thefourchannelsarecon-
figured as follows:
Analog Input
A0 Potentiometer with operational amplifier buffer
A1 ±10 V supply voltage follower
A2 Uses external input unbuffered
A3 Uses external input unbuffered
Normally, through the software, the full scale, mid scale, and zero scale
couldbe checkedfirst. ThenA0can beselected andcheckedwith thepo-
tentiometer adjustment.
- Connect the appropriate voltage reference as follows. Place a short on
JP2, position 2 toward TP11 designation, to connect REF– terminal to
ground.
JP1 Designation Reference Voltage
1 On board absolute reference (4.086 V at 5 V VCC
or 2.5 V at 2.7 V VCC)
3 VCC
When SW1 is changed the onboard absolute reference is automatically
changed to the proper value for the VCC selected.
- The I/O signals can be monitored at J7.
- The additional analog inputs can be used for application of external sig-
nals.Selectthedesired analog inputforboard checkout.Ensurethat JP3,
JP4, and JP6 are shorted with a jumper connection.

1-6
Overview

2-1
Physical Description
Physical Description
ThischapterdescribesthephysicalcharacteristicsandPCBlayoutoftheEVM
and lists the components used on the module.
Topic Page
2.1 PCB Layout 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Components List 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 2

PCB Layout
2-2
Physical Description
2.1 PCB Layout
TheEVMis constructedon a4-layer,3-inch x5.25-inch, 0.062-inchthick PCB
using FR-4 material. Figures 2–1 through 2–5 show the individual layers.
Figure 2–1.PCB Layout

PCB Layout
2-3
Physical Description
Figure 2–2.PCB Layout

PCB Layout
2-4
Physical Description
Figure 2–3.PCB Layout