Texas Instruments LMK0482 Series User manual

DAC
Recovered
³GLUW\´FORFNRU
clean clock
0XOWLSOH³FOHDQ´
clocks at different
frequencies
DCLKout0 &
DCLKout2
DCLKout12
DCLKout4,
SDCLKout5
FPGA
CLKin0
Crystal or
VCXO
Backup
Reference
Clock CLKin1
OSCout
DAC
SDCLKout1 &
SDCLKout3
ADC
LMX2581
PLL+VCO
Serializer/
Deserializer
LMK0482xB SDCLKout13
SDCLKout9 &
SDCLKout11
DCLKout8 &
DCLKout10
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LMK04821 , LMK04826 , LMK04828
SNAS605AR –MARCH 2013–REVISED DECEMBER 2015
LMK0482x Ultra Low-Noise JESD204B Compliant
Clock Jitter Cleaner with Dual Loop PLLs
1 Features 2 Applications
1• JEDEC JESD204B Support • Wireless Infrastructure
• Ultra-Low RMS Jitter • Data Converter Clocking
• Networking, SONET/SDH, DSLAM
– 88 fs RMS Jitter (12 kHz to 20 MHz) • Medical / Video / Military / Aerospace
– 91 fs RMS Jitter (100 Hz to 20 MHz) • Test and Measurement
– –162.5 dBc/Hz Noise Floor at 245.76 MHz
• Up to 14 Differential Device Clocks from PLL2 3 Description
– Up to 7 SYSREF Clocks The LMK0482x family is the industry's highest
– Maximum Clock Output Frequency 3.1 GHz performance clock conditioner with JEDEC
– LVPECL, LVDS, HSDS, LCPECL JESD204B support.
Programmable Outputs from PLL2 The 14 clock outputs from PLL2 can be configured to
• Up to 1 Buffered VCXO/Crystal Output from PLL1 drive seven JESD204B converters or other logic
devices using device and SYSREF clocks. SYSREF
– LVPECL, LVDS, 2xLVCMOS Programmable can be provided using both DC and AC coupling. Not
• Dual Loop PLLatinum™ PLL Architecture limited to JESD204B applications, each of the 14
• PLL1 outputs can be individually configured as high
– Up to 3 Redundant Input Clocks performance outputs for traditional clocking systems.
– Automatic and Manual Switch-Over Modes The high performance combined with features like the
ability to trade off between power or performance,
– Hitless Switching and LOS dual VCOs, dynamic digital delay, holdover, and
– Integrated Low-Noise Crystal Oscillator Circuit glitchless analog delay make the LMK0482x family
– Holdover mode when Input Clocks are Lost ideal for providing flexible high performance clocking
• PLL2 trees.
– Normalized [1 Hz] PLL Noise Floor of Device Information(1)
-227 dBc/Hz PART VCO0 VCO1 FREQUENCY
– Phase Detector Rate up to 155 MHz NUMBER FREQUENCY
– OSCin Frequency-Doubler 2920 to 3080 MHz
LMK04821 1930 to 2075 MHz VCO1 Div = ÷2 to ÷8
– Two Integrated Low-Noise VCOs (÷2 = 1460 to 1540 MHz)
• 50% Duty Cycle Output Divides, 1 to 32 LMK04826B 1840 to 1970 MHz 2440 to 2505 MHz
(even and odd) LMK04828B 2370 to 2630 MHz 2920 to 3080 MHz
• Precision Digital Delay, Dynamically Adjustable (1) For all available packages, see the orderable addendum at
• 25 ps Step Analog Delay the end of the datasheet.
• Multi-mode: Dual PLL, single PLL, and Clock Simplified Schematic
Distribution
• Industrial Temperature Range: –40 to 85°C
• Supports 105°C PCB Temperature (Measured at
Thermal Pad)
• 3.15-V to 3.45-V Operation
• Package: 64-Pin QFN (9.0 mm x 9.0 mm x 0.8
mm)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMK04821 , LMK04826 , LMK04828
SNAS605AR –MARCH 2013–REVISED DECEMBER 2015 www.ti.com
Table of Contents
9.3 Feature Description................................................. 36
1 Features.................................................................. 19.4 Device Functional Modes........................................ 46
2 Applications ........................................................... 19.5 Programming........................................................... 49
3 Description............................................................. 19.6 Register Maps ........................................................ 50
4 Revision History..................................................... 29.7 Device Register Descriptions.................................. 54
5 Device Comparison Table..................................... 610 Applications and Implementation...................... 95
5.1 Device Configuration Information.............................. 610.1 Application Information.......................................... 95
6 Pin Configuration and Functions......................... 710.2 Typical Applications .............................................. 95
7 Specifications......................................................... 910.3 Do's and Don'ts................................................... 101
7.1 Absolute Maximum Ratings ...................................... 911 Power Supply Recommendations ................... 102
7.2 ESD Ratings.............................................................. 911.1 Current Consumption / Power Dissipation
7.3 Recommended Operating Conditions....................... 9Calculations............................................................ 102
7.4 Thermal Information.................................................. 912 Layout................................................................. 103
7.5 Electrical Characteristics......................................... 10 12.1 Layout Guidelines ............................................... 103
7.6 SPI Interface Timing ............................................... 23 12.2 Layout Example .................................................. 104
7.7 Typical Characteristics – Clock Output AC 13 Device and Documentation Support............... 105
Characteristics ......................................................... 24 13.1 Device Support .................................................. 105
8 Parameter Measurement Information ................ 26 13.2 Related Links ...................................................... 105
8.1 Charge Pump Current Specification Definitions...... 26 13.3 Trademarks......................................................... 105
8.2 Differential Voltage Measurement Terminology ..... 27 13.4 Electrostatic Discharge Caution.......................... 105
9 Detailed Description............................................ 28 13.5 Glossary.............................................................. 105
9.1 Overview................................................................. 28 14 Mechanical, Packaging, and Orderable
9.2 Functional Block Diagram....................................... 32 Information......................................................... 105
4 Revision History
Changes from Revision AQ (August 2014) to Revision AR Page
• Added Support for 105°C thermal pad temperature .............................................................................................................. 1
• Changed from I/O to I for pin 6 in Pin Functions table .......................................................................................................... 7
• Deleted programmable status pin in Description column for pin 6 in Pin Functions table..................................................... 7
• Changed from No connection to Do not connect for pins 7, 8, 9 in Pin Functions table ...................................................... 7
• Changed to Reference Clck Input Port 1 for PLL 1 for Pins 34, 35 in Pin Functions ........................................................... 8
• Added Reference Clock Input Port 2 for PLL1 for pins 40, 41 in Pin Functions ................................................................... 8
• Added ESD Ratings................................................................................................................................................................ 9
• Added PCB temperature in Recommended Operating Conditions........................................................................................ 9
• Added Digital Input Timing in Electrical Characteristics ...................................................................................................... 22
• Changed Detailed block diagrams for LMK04821 and LMK04826/8 .................................................................................. 32
• Added 6 to DCLKout0 sequence and 7 to SDCLKout1 sequence in Figure 12................................................................... 34
• Added 6 to DCLKout0 sequence and 7 to SDCLKout1 sequence in Figure 13................................................................... 35
• Added For each SDCLKoutY being used in SYNC/SYSREF............................................................................................... 36
• Deleted "SDCLKoutY_PD as required per output. " in Table 1............................................................................................ 36
• Added footnote starting SDCLKoutY_PD = 0 as... in Table 1 ............................................................................................. 36
• Added SDCLKout1_PD = 0, SDCLKout3_PD = 0 in Setup of SYSREF Example............................................................... 37
• Changed DLD_HOLD_CNT to HOLDOVER_DLD_CNT in Holdover Mode - Automatic Exit of Holdover ......................... 45
• Changed Recommended Programming Sequence ............................................................................................................. 49
• Added 0x171/0x172 to Register Map .................................................................................................................................. 53
• Added LMK04821 register setting ....................................................................................................................................... 55
• Revised Register 0x143 table............................................................................................................................................... 67
• Added fixed register setting for 0x171.................................................................................................................................. 68
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Revision History (continued)
• Added fixed register setting for 0x172 ................................................................................................................................. 68
• Added LMK04821 register setting ....................................................................................................................................... 91
• Added LMK04821 register setting ....................................................................................................................................... 92
• Changed RB_PLL1_LD description ..................................................................................................................................... 92
• Changed RB_PLL2_LD description ..................................................................................................................................... 92
Changes from Revision AP (June 2013) to Revision AQ Page
• Changed data sheet flow and layout to conform with new TI standards. Added, updated, or renamed the following
sections: Device Information Table, Application and Implementation; Power Supply Recommendations; Layout;
Device and Documentation Support; Mechanical, Packaging, and Ordering Information .................................................... 1
• Added values for LMK04821 under "Features" section. ........................................................................................................ 1
• Changed LMK04820 family to LMK0482x family .................................................................................................................. 1
• Added values for LMK04821 in Device Configuration Information......................................................................................... 6
• Added holdover DAC to pin 36 description in Pin Functions ................................................................................................ 8
• Changed Thermal Information header from LMK0482xB to LMK0482x ............................................................................... 9
• Changed CLKinX_BUF_TYPE to CLKinX_TYPE in Electrical Characteristics.................................................................... 10
• Added values for LMK04821 under Internal VCO Specifications in Electrical Characteristics............................................ 13
• Added values for LMK04821 under Noise Floor in Electrical Characteristics...................................................................... 14
• Added values for LMK04821 under CLKout Closed Loop Phase Noise Specifications a Commercial Quality VCXO
in Electrical Characteristics .................................................................................................................................................. 15
• Added 245.76 MHz as frequency for LMK04826B phase noise data L(f)CLKout for VCO0 ................................................... 16
• Added 245.76 MHz as frequency for LMK04826B phase noise data L(f)CLKout for VCO1 ................................................... 16
• Added 245.76 MHz as frequency for LMK04828B phase noise data L(f)CLKout for VCO0 ................................................... 16
• Added 245.76 MHz as frequency for LMK04828B phase noise data L(f)CLKout for VCO1 ................................................... 16
• Added values for LMK04821 under CLKout Closed Loop Jitter Specifications a Commercial Quality VCXO .................... 17
• Added SDCLKoutY_HS = 0 for tsJESD204B in Electrical Characteristics ................................................................................ 19
• Added Propagation Delay from CLKin0 to SDCLKoutY in Electrical Characteristics........................................................... 19
• Added footnote that LMK04821 has no DCLKoutX or SDCLKoutY outputs on at power up, only OSCout. ...................... 19
• Changed VOH TEST CONDITIONS to = 3 or 4 and VOL TEST CONDITIONS to 3, 4, or 6 under DIGITAL OUTPUTS
(CLKin_SELX, Status_LDX, and RESET/GPO) subheading in Electrical Characteristics................................................... 21
• Changed Digital Inputs (SCK, SDIO, CS*) IIH VIH = VCC min line from 5 µA to –5 µA........................................................ 22
• Added 4 wire mode read back has same timing as SDIO pin,R/W bit = 0 is for SPI write,R/W bit = 1 is for SPI
read,W1 and W0 shall be written as 0. ............................................................................................................................... 23
• Added LMK04821 phase noise graphs under Clock Output AC Characteristics................................................................. 24
• Added link to AN-912 Application Report............................................................................................................................. 27
• Changed from Glitchless Half Shift to Glitchless Half Step.................................................................................................. 30
• Added LMK04821 detailed block diagram............................................................................................................................ 32
• Changed block from SDCLKoutY_POL to DCLKoutX_POL in Figure 12............................................................................ 34
• Added SYSREF_CLKin0_MUX block to Figure 13 image. .................................................................................................. 35
• Changed Figure 13 to show that FB_MUX SYSREF input comes from SYSREF Divider, not SYSREF_MUX.................. 35
• Changed term pulsor to pulser throughout .......................................................................................................................... 36
• Changed DCLKout0_1_DIV to DCLKout0_DIV; DCLKout2_3_DIV to DCLKout2_DIV; DCLKout4_5_DIV to
DCLKout4_DIV .................................................................................................................................................................... 37
• Added DCLKout4_DIV = 20 ................................................................................................................................................. 37
• Added DCLKout0_DDLY_PD = 0, DCLKout2_DDLY_PD = 0, DCLKout4_DDLY_PD = 0.................................................. 37
• Changed text to read, Set device clock and SYSREF divider digital delays: DCLKout0_DDLY_CNTH,
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DCLKout0_DDLY_CNTL, DCLKout2_DDLY_CNTH, DCLKout2_DDLY_CNTL, DCLKout4_DDLY_CNTH,
DCLKout4_DDLY_CNTL, SYSREF_DDLY. ........................................................................................................................ 37
• Added = 1 in SYSREF Request .......................................................................................................................................... 38
• Changed step numbers in dynamic delay and references to steps to be correct, step 8 was duplicated .......................... 41
• Added note LMK04821 includes VCO1 divider on VCO1 output......................................................................................... 46
• Added note LMK04821 includes VCO1 divider on VCO1 output......................................................................................... 47
• Added R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read. ......................................................................................... 49
• Added If using LMK04821, program register 0x174 in Recommended Programming Sequence ...................................... 49
• Added SYSREF_CLKin0_MUX and VCO1_DIV to register map......................................................................................... 51
• Added CLKin_OVERRIDE bit to register map ..................................................................................................................... 52
• Changed from half shift to half step...................................................................................................................................... 57
• Changed definition of SDCLKoutY_DDLY value of 0 from Reserved to Bypass................................................................. 57
• Changed from Sets the polarity of SYSREF clocks to Sets the polarity of clock on SDCLKoutY when device clock
output is selected with SDCLKoutY_MUX............................................................................................................................ 60
• Changed Sets the polarity of the device clocks to Sets the polarity of the device clocks from the DCLKoutX outputs ...... 60
• Added LMK04821 DCLKoutX_FMT power on reset values as powerdown......................................................................... 60
• Changed from SYSREF to SYSREF Divider in Source column of Register 0x13F ............................................................ 64
• Changed reserved to Off for CLKin1_OUT_MUX ............................................................................................................... 69
• Changed reserved to Off for CLKin0_OUT_MUX. .............................................................................................................. 69
• Added CLKin_OVERRIDE bit .............................................................................................................................................. 76
• Added LMK04821 register 0x174 for VCO1_DIV................................................................................................................. 91
• Deleted LMK04828 from Core line .................................................................................................................................... 102
• Added VCO1 Icc including VCO1 Divider for LMK04821................................................................................................... 102
• Changed VCO1 Icc and power dissipated for LMK04828B/26B from 6 mA to 13.5 mA and 19.8 mW to 44.55 mW....... 102
Changes from Revision AO (March 2013) to Revision AP Page
• Changed datasheet title from LMK04828 to LMK0482xB...................................................................................................... 1
• Changed LMK04828 family to LMK04820 family................................................................................................................... 1
• Changed image from LMK04828B to LMK0482xB ................................................................................................................ 1
• Added LMK04826 to Device Configuration Information table ................................................................................................ 6
• Changed - increased LMK04828B VCO0 max frequency from 2600 MHz to 2630 MHz...................................................... 6
• Changed - expanded LMK04828B VCO1 frequency range from 2945 - 3005 MHz to 2920 MHz - 3080 MHz..................... 6
• Changed Thermal Information header from LMK04828B to LMK0482xB.............................................................................. 9
• Added LMK04826 VCO Range Specification....................................................................................................................... 13
• Changed - increased LMK04828B VCO0 max frequency from 2600 MHz to 2630 MHz.................................................... 13
• Changed - expanded LMK04828B VCO1 frequency range from 2945 - 3005 MHz to 2920 MHz - 3080 MHz................... 13
• Added LMK04826 KVCO specification ................................................................................................................................... 13
• Added clarification of LMK04828 specification vs LMK04826 specification for KVCO........................................................... 13
• Added LMK04826 noise floor data....................................................................................................................................... 14
• Changed - clarified phase noise data section header.......................................................................................................... 15
• Added LMK04826 phase noise data.................................................................................................................................... 16
• Added LMK04826 jitter data................................................................................................................................................. 17
• Added LMK04826 fCLKout-startup spec ...................................................................................................................................... 19
• Added clarification of LMK04828 specification vs. LMK04826 specification for fCLKout-startup................................................. 19
• Added LMK04826B Phase Noise Performance Graph for VCO0........................................................................................ 24
• Added LMK04826B Phase Noise Performance Graph for VCO1........................................................................................ 24
• Added Added PLL2 loop filter bandwidth and phase margin info to plot ............................................................................. 25
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• Changed LMK04828 to LMK0482xB in VCXO/Crystal Buffered Output ............................................................................. 28
• Changed LMK04828 to LMK0482xB in Status Pins ............................................................................................................ 31
• Changed image from LMK04828 to LMK0482xB................................................................................................................. 46
• Changed - corrected value of PLL2_P selection to be 0 to correspond with register programming definition.................... 46
• Changed image from LMK04828 to LMK0482xB................................................................................................................. 47
• Changed image from LMK04828 to LMK0482xB................................................................................................................. 48
• Added LMK04826 register setting........................................................................................................................................ 55
• Added LMK04826 register setting........................................................................................................................................ 91
• Added LMK04826 register setting........................................................................................................................................ 92
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5 Device Comparison Table
5.1 Device Configuration Information
PLL2
REF- OSCout (BUFFERED PROGRAMMABLE
ERENCE
PART NUMBER OSCin Clock) LVDS/ VCO0 FREQUENCY VCO1 FREQUENCY
LVDS/LVPECL/HSDS
LVPECL/ LVCMOS (1)
INPUTS(1) OUTPUTS
VCO1_DIV = ÷2
1460 to 1540 MHz
VCO1_DIV = ÷3
974 to 1026 MHz
VCO1_DIV = ÷4
730 to 770 MHz
VCO1_DIV = ÷5
LMK04821 Up to 3 Up to 1 14 1930 to 2075 MHz 584 to 616 MHz
VCO1_DIV = ÷6
487 to 513 MHz
VCO1_DIV = ÷7
418 to 440 MHz
VCO1_DIV = ÷8
365 to 385 MHz
LMK04826B Up to 3 Up to 1 14 1840 to 1970 MHz 2440 to 2505 MHz
LMK04828B Up to 3 Up to 1 14 2370 to 2630 MHz 2920 to 3080 MHz
(1) OSCout may also be third clock input, CLKin2.
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SDCLKout1
SCK
SDIO
CS*
NC
NC
NC
Vcc1_VCO
LDObyp1
LDObyp2
Status_LD1
Vcc9_CP2
Vcc7_OSCout
Vcc12_CG0
CPout2
Vcc10_PLL2
DCLKout4*
DCLKout4
OSCin
OSCin*
CPout1
Vcc8_OSCin
CLKin0
CLKin0*
SDCLKout3*
SDCLKout3
Vcc2_CG1
DCLKout2
DCLKout2*
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
SDCLKout1*
Vcc11_CG3 DCLKout10
SYNC/SYSREF_REQ
Vcc6_PLL1
CLKin1/Fin/FBCLKin
CLKin1*/Fin*/FBCLKin*
CLKin_SEL1
DCLKout0
DCLKout0*
SDCLKout11* DCLKout10* SDCLKout11
SDCLKout5
SDCLKout5*
OSCout*/CLKin2*
OSCout/CLKin2
SDCLKout13 DCLKout12* SDCLKout13* DCLKout12
SDCLKout7*
SDCLKout7
DCLKout6*
DCLKout6
SDCLKout9 DCLKout8* SDCLKout9* DCLKout8
Vcc4_CG2
Status_LD2
RESET/GPO
CLKin_SEL0
Vcc3_SYSREF
LLP-64
Top down view
DAP
Vcc5_DIG
Clock Group 1
Clock Group 0
Clock Group 2
Clock Group 3
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6 Pin Configuration and Functions
NKD Package
64-Pin WQFN
Top View
Pin Functions
PIN I/O TYPE DESCRIPTION(1)
NO. NAME
DCLKout0,
1, 2 O Programmable Device clock output 0.
DCLKout0*
SDCLKout1,
3, 4 O Programmable SYSREF / Device clock output 1
SDCLKout1*
5 RESET/GPO I CMOS Device reset input or GPO
6 SYNC/SYSREF_REQ I CMOS Synchronization input or SYSREF_REQ for requesting continuous SYSREF.
7, 8, 9 NC Do not connect. These pins must be left floating.
10 Vcc1_VCO PWR Power supply for VCO LDO.
11 LDObyp1 ANLG LDO Bypass, bypassed to ground with 10-µF capacitor.
12 LDObyp2 ANLG LDO Bypass, bypassed to ground with a 0.1-µF capacitor.
SDCLKout3,
13, 14 O Programmable SYSREF / Device Clock output 3.
SDCLKout3*
DCLKout2,
15, 16 O Programmable Device clock output 2.
DCLKout2*
17 Vcc2_CG1 PWR Power supply for clock outputs 2 and 3.
18 CS* I CMOS Chip Select
19 SCK I CMOS SPI Clock
(1) See Pin Connection Recommendations for recommended connections.
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Pin Functions (continued)
PIN I/O TYPE DESCRIPTION(1)
NO. NAME
20 SDIO I/O CMOS SPI Data
21 Vcc3_SYSREF PWR Power supply for SYSREF divider and SYNC.
SDCLKout5,
22, 23 O Programmable SYSREF / Device clock output 5.
SDCKLout5*
DCLKout4,
24, 25 O Programmable Device clock output 4.
DCLKout4*
26 Vcc4_CG2 PWR Power supply for clock outputs 4, 5, 6 and 7.
DCLKout6,
27, 28 O Programmable Device clock output 6.
DCLKout6*
SDCLKout7,
29, 30 O Programmable SYSREF / Device clock output 7.
SDCLKout7*
31 Status_LD1 I/O Programmable Programmable status pin.
32 CPout1 O ANLG Charge pump 1 output.
33 Vcc5_DIG PWR Power supply for the digital circuitry.
CLKin1, CLKin1* I ANLG Reference Clock Input Port 1 for PLL1.
FBCLKin,
34, 35 I ANLG Feedback input for external clock feedback input (0–delay mode).
FBCLKin*
Fin, Fin* I ANLG External VCO Input (External VCO mode).
36 Vcc6_PLL1 PWR Power supply for PLL1, charge pump 1, holdover DAC
37, 38 CLKin0, CLKin0* I ANLG Reference Clock Input Port 0 for PLL1.
39 Vcc7_OSCout PWR Power supply for OSCout port.
OSCout, OSCout* Buffered output of OSCin port.
40, 41 I/O Programmable
CLKin2, CLKin2* Reference Clock Input Port 2 for PLL1.
42 Vcc8_OSCin PWR Power supply for OSCin
43, 44 OSCin, OSCin* I ANLG Feedback to PLL1, Reference input to PLL2. AC coupled.
45 Vcc9_CP2 PWR Power supply for PLL2 Charge Pump.
46 CPout2 O ANLG Charge pump 2 output.
47 Vcc10_PLL2 PWR Power supply for PLL2.
48 Status_LD2 I/O Programmable Programmable status pin.
SDCLKout9,
49, 50 O Programmable SYSREF / Device clock 9
SDCLKout9*
DCLKout8,
51, 52 O Programmable Device clock output 8.
DCLKout8*
53 Vcc11_CG3 PWR Power supply for clock outputs 8, 9, 10, and 11.
DCLKout10,
54, 55 O Programmable Device clock output 10.
DCLKout10*
SDCLKout11,
56, 57 O Programmable SYSREF / Device clock output 11.
SDCLKout11*
58 CLKin_SEL0 I/O Programmable Programmable status pin.
59 CLKin_SEL1 I/O Programmable Programmable status pin.
SDCLKout13,
60, 61 O Programmable SYSREF / Device clock output 13.
SDCLKout13*
DCLKout12,
62, 63 O Programmable Device clock output 12.
DCLKout12*
64 Vcc12_CG0 PWR Power supply for clock outputs 0, 1, 12, and 13.
DAP DAP GND DIE ATTACH PAD, connect to GND.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage (2) –0.3 3.6 V
(VCC +
VIN Input voltage –0.3 V
0.3)
TLLead temperature (solder 4 seconds) 260 °C
TJJunction temperature 150 °C
Differential input current (CLKinX/X*,
IIN ± 5 mA
OSCin/OSCin*, FBCLKin/FBCLKin*, Fin/Fin*)
MSL Moisture sensitivity level 3
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Never to exceed 3.6 V.
7.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
Machine Model (MM) ±150
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22- ±250
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±250 V may actually have higher performance.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT
TJJunction Temperature 125 °C
TAAmbient Temperature –40 25 85 °C
TPCB PCB Temperature (measured at thermal pad) 105 °C
VCC Supply Voltage 3.15 3.3 3.45 V
7.4 Thermal Information LMK0482x
THERMAL METRIC(1) NKD (WQFN) UNIT
64 PINS
RθJA Junction-to-ambient thermal resistance(2) 24.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance(3) 6.1 °C/W
RθJB Junction-to-board thermal resistance(4) 3.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
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Thermal Information (continued)
LMK0482x
THERMAL METRIC(1) NKD (WQFN) UNIT
64 PINS
ψJT Junction-to-top characterization parameter(5) 0.1 °C/W
ψJB Junction-to-board characterization parameter(6) 3.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance(7) 0.7 °C/W
(5) The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ΨJB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
7.5 Electrical Characteristics
(3.15 V < VCC < 3.45 V, –40 °C < TA< 85 °C and TPCB ≤105 °C. Typical values at VCC = 3.3 V, TA= 25 °C, at the
Recommended Operating Conditions and are not assured.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT CONSUMPTION
ICC_PD Power Down Supply Current 1 3 mA
14 HSDS 8 mA clocks enabled
ICC_CLKS Supply Current(1) 565 665 mA
PLL1 and PLL2 locked.
CLKin0/0*, CLKin1/1*, and CLKin2/2* INPUT CLOCK SPECIFICATIONS
fCLKin Clock Input Frequency 0.001 750 MHz
SLEWCLKin Clock Input Slew Rate (2) 20% to 80% 0.15 0.5 V/ns
VIDCLKin Clock Input 0.125 1.55 |V|
Differential Input Voltage (3) AC coupled
VSSCLKin 0.25 3.1 Vpp
Figure 8 AC coupled to CLKinX;
CLKinX* AC coupled to Ground 0.25 2.4 Vpp
CLKinX_TYPE = 0 (Bipolar)
Clock Input
VCLKin Single-ended Input Voltage AC coupled to CLKinX;
CLKinX* AC coupled to Ground 0.35 2.4 Vpp
CLKinX_TYPE = 1 (MOS)
Each pin AC coupled, CLKin0/1/2 0 |mV|
CLKinX_TYPE = 0 (Bipolar)
DC offset voltage between
CLKinX/CLKinX* (CLKinX* - CLKinX) Each pin AC coupled, CLKin0/1
|VCLKinX-offset| 55 |mV|
CLKinX_TYPE = 1 (MOS)
DC offset voltage between Each pin AC coupled 20 |mV|
CLKin2/CLKin2* (CLKin2* - CLKin2) CLKinX_TYPE = 1 (MOS)
VCLKin- VIH High input voltage DC coupled to CLKinX; 2.0 VCC V
CLKinX* AC coupled to Ground
VCLKin- VIL Low input voltage 0.0 0.4 V
CLKinX_TYPE = 1 (MOS)
FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS
Clock Input Frequency for AC coupled
fFBCLKin 0.001 750 MHz
0-delay with external feedback. CLKinX_TYPE = 0 (Bipolar)
Clock Input Frequency for AC coupled (4)
fFin 0.001 3100 MHz
external VCO or distribution mode. CLKinX_TYPE = 0 (Bipolar)
(1) See the applications section of Power Supply Recommendations for Icc for specific part configuration and how to calculate Icc for a
specific design.
(2) In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all
input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input
slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended
clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to
their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to
achieve optimal phase noise performance at the device outputs.
(3) See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.
(4) Assured by characterization. ATE tested at 2949.12 MHz.
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Electrical Characteristics (continued)
(3.15 V < VCC < 3.45 V, –40 °C < TA< 85 °C and TPCB ≤105 °C. Typical values at VCC = 3.3 V, TA= 25 °C, at the
Recommended Operating Conditions and are not assured.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Single Ended AC coupled
VFBCLKin/Fin 0.25 2.0 Vpp
Clock Input Voltage CLKinX_TYPE = 0 (Bipolar)
AC coupled; 20% to 80%;
SLEWFBCLKin/Fin Slew Rate on CLKin (2) 0.15 0.5 V/ns
(CLKinX_TYPE = 0)
PLL1 SPECIFICATIONS
fPD1 PLL1 Phase Detector Frequency 40 MHz
VCPout1 = VCC/2, PLL1_CP_GAIN = 0 50
VCPout1 = VCC/2, PLL1_CP_GAIN = 1 150
VCPout1 = VCC/2, PLL1_CP_GAIN = 2 250
PLL1 Charge
ICPout1SOURCE µA
Pump Source Current (5) … …
VCPout1 = VCC/2, PLL1_CP_GAIN = 14 1450
VCPout1 = VCC/2, PLL1_CP_GAIN = 15 1550
VCPout1=VCC/2, PLL1_CP_GAIN = 0 –50
VCPout1=VCC/2, PLL1_CP_GAIN = 1 –150
VCPout1=VCC/2, PLL1_CP_GAIN = 2 –250
PLL1 Charge
ICPout1SINK µA
Pump Sink Current (5) … …
VCPout1=VCC/2, PLL1_CP_GAIN = 14 –1450
VCPout1=VCC/2, PLL1_CP_GAIN = 15 –1550
Charge Pump
ICPout1%MIS VCPout1 = VCC/2, T = 25 °C 1% 10%
Sink / Source Mismatch
Magnitude of Charge Pump Current 0.5 V < VCPout1 < VCC - 0.5 V
ICPout1VTUNE 4%
Variation vs. Charge Pump Voltage TA= 25 °C
Charge Pump Current vs.
ICPout1%TEMP 4%
Temperature Variation
Charge Pump TRI-STATE Leakage
ICPout1 TRI 0.5 V < VCPout < VCC - 0.5 V 5 nA
Current
PLL 1/f Noise at 10 kHz offset. PLL1_CP_GAIN = 350 µA –117
PN10kHz Normalized to 1 GHz Output dBc/Hz
PLL1_CP_GAIN = 1550 µA –118
Frequency PLL1_CP_GAIN = 350 µA –221.5
PN1Hz Normalized Phase Noise Contribution dBc/Hz
PLL1_CP_GAIN = 1550 µA –223
PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS
fOSCin PLL2 Reference Input (6) 500 MHz
PLL2 Reference Clock minimum slew
SLEWOSCin 20% to 80% 0.15 0.5 V/ns
rate on OSCin (2)
AC coupled; Single-ended
VOSCin Input Voltage for OSCin or OSCin* 0.2 2.4 Vpp
(Unused pin AC coupled to GND)
VIDOSCin 0.2 1.55 |V|
Differential voltage swing AC coupled
Figure 8
VSSOSCin 0.4 3.1 Vpp
DC offset voltage between
|VOSCin-offset| Each pin AC coupled 20 |mV|
OSCin/OSCin* (OSCinX* - OSCinX) EN_PLL2_REF_2X = 1(8);
fdoubler_max Doubler input frequency (7) 155 MHz
OSCin Duty Cycle 40% to 60%
(5) This parameter is programmable
(6) FOSCin maximum frequency assured by characterization. Production tested at 122.88 MHz.
(7) Assured by characterization. ATE tested at 122.88 MHz.
(8) The EN_PLL2_REF_2X bit enables/disables a frequency doubler mode for the PLL2 OSCin path.
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Electrical Characteristics (continued)
(3.15 V < VCC < 3.45 V, –40 °C < TA< 85 °C and TPCB ≤105 °C. Typical values at VCC = 3.3 V, TA= 25 °C, at the
Recommended Operating Conditions and are not assured.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CRYSTAL OSCILLATOR MODE SPECIFICATIONS
Fundamental mode crystal
FXTAL Crystal Frequency Range ESR = 200 Ω(10 to 30 MHz) 10 40 MHz
ESR = 125 Ω(30 to 40 MHz)
CIN Input Capacitance of OSCin port –40 to 85 °C 1 pF
PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS
fPD2 Phase Detector Frequency (7) 155 MHz
VCPout2=VCC/2, PLL2_CP_GAIN = 0 100
VCPout2=VCC/2, PLL2_CP_GAIN = 1 400
PLL2 Charge Pump Source Current
ICPoutSOURCE µA
(5) VCPout2=VCC/2, PLL2_CP_GAIN = 2 1600
VCPout2=VCC/2, PLL2_CP_GAIN = 3 3200
VCPout2=VCC/2, PLL2_CP_GAIN = 0 –100
VCPout2=VCC/2, PLL2_CP_GAIN = 1 –400
ICPoutSINK PLL2 Charge Pump Sink Current (5) µA
VCPout2=VCC/2, PLL2_CP_GAIN = 2 –1600
VCPout2=VCC/2, PLL2_CP_GAIN = 3 –3200
ICPout2%MIS Charge Pump Sink/Source Mismatch VCPout2=VCC/2, TA= 25 °C 1% 10%
Magnitude of Charge Pump Current 0.5 V < VCPout2 < VCC - 0.5 V
ICPout2VTUNE 4%
vs. Charge Pump Voltage Variation TA= 25 °C
Charge Pump Current vs.
ICPout2%TEMP 4%
Temperature Variation
ICPout2TRI Charge Pump Leakage 0.5 V < VCPout2 < VCC - 0.5 V 10 nA
PLL 1/f Noise at 10 kHz offset (9). PLL2_CP_GAIN = 400 µA –118
PN10kHz Normalized to dBc/Hz
PLL2_CP_GAIN = 3200 µA –121
1 GHz Output Frequency PLL2_CP_GAIN = 400 µA –222.5
Normalized Phase Noise Contribution
PN1Hz dBc/Hz
(10) PLL2_CP_GAIN = 3200 µA –227
(9) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker
noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10
kHz) - 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise,
L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean
crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference
oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f)
and LPLL_flat(f).
(10) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as:
PN1HZ=LPLL_flat(f) - 20log(N) - 10log(fPDX). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz
bandwidth and fPDX is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f).
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Electrical Characteristics (continued)
(3.15 V < VCC < 3.45 V, –40 °C < TA< 85 °C and TPCB ≤105 °C. Typical values at VCC = 3.3 V, TA= 25 °C, at the
Recommended Operating Conditions and are not assured.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL VCO SPECIFICATIONS
VCO0 1930 2075
LMK04821 VCO Tuning Range MHz
VCO1(11) 2920 3080
VCO0 1840 1970
fVCO LMK04826 VCO Tuning Range MHz
VCO1 2440 2505
VCO0 2370 2630
LMK04828 VCO Tuning Range MHz
VCO1 2920 3080
LMK04821 VCO0 12 to 20
LMK04821 Fine Tuning Sensitivity MHz/V
LMK04821 VCO1 15 to 24
LMK04826 VCO0 11 to 19
KVCO LMK04826 Fine Tuning Sensitivity MHz/V
LMK04826 VCO1 8 to 11
LMK04828 VCO0 at 2457.6 MHz 17 to 27
LMK04828 Fine Tuning Sensitivity MHz/V
LMK04828 VCO1 at 2949.12 MHz 17 to 23
Allowable Temperature Drift for After programming for lock, no changes
|ΔTCL| Continuous Lock to output configuration are permitted to 125 °C
(12) assure continuous lock
(11) The VCO1 divider, VCO1_DIV in register 0x174, can be programmed to ÷2 to ÷8 resulting in a lower effective VCO frequency range as
shown in Device Configuration Information.
(12) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was
at the time that the 0x168 register was last programmed with PLL2_FCAL_DIS = 0, and still have the part stay in lock. The action of
programming the 0x168 register, even to the same value, activates a frequency calibration routine. This implies the part will work over
the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be
necessary to reload the appropriate register to ensure it stays in lock. Regardless of what temperature the part was initially programmed
at, the temperature can never drift outside the frequency range of –40 °C to 85 °C without violating specifications.
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Electrical Characteristics (continued)
(3.15 V < VCC < 3.45 V, –40 °C < TA< 85 °C and TPCB ≤105 °C. Typical values at VCC = 3.3 V, TA= 25 °C, at the
Recommended Operating Conditions and are not assured.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NOISE FLOOR
LVDS –158.2
HSDS 6 mA –160
HSDS 8 mA –161
LMK04821, VCO0, Noise Floor
L(f)CLKout 245.76 MHz HSDS 10 mA –161.4 dBc/Hz
20 MHz Offset(13) LVPECL16 /w 240 Ω–161.6
LVPECL20 /w 240 Ω–162
LVPECL 161.7
LVDS –157.1
HSDS 6 mA –158.3
HSDS 8 mA –159
LMK04821, VCO1, Noise Floor
L(f)CLKout 245.76 MHz HSDS 10 mA –159.2 dBc/Hz
20 MHz Offset(13) LVPECL16 /w 240 Ω–158.8
LVPECL20 /w 240 Ω–158.9
LVPECL –158.8
LVDS –158.1
HSDS 6 mA –159.7
HSDS 8 mA –160.8
LMK04826, VCO0, Noise Floor
L(f)CLKout 245.76 MHz HSDS 10 mA –161.3 dBc/Hz
20 MHz Offset (14) LVPECL16 /w 240 Ω–161.8
LVPECL20 /w 240 Ω–162.0
LCPECL –161.7
LVDS –157.5
HSDS 6 mA –158.9
HSDS 8 mA –159.8
LMK04826, VCO1, Noise Floor
L(f)CLKout 245.76 MHz HSDS 10 mA –160.3 dBc/Hz
20 MHz Offset (14) LVPECL16 /w 240 Ω–160.8
LVPECL20 /w 240 Ω–160.7
LCPECL –160.7
(13) Data collected using a Prodyn BIB-100G balun. Loop filter is C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10
pF, R4 = 200 Ω, PLL1_CP = 450 µA, PLL2_CP = 3.2 mA.. VCO0 PLL2 loop filter bandwidth = 288 kHz, phase margin = 72 degrees.
VCO1 Loop filter loop bandwidth = 221 kHz, phase margin = 70 degrees. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0.
(14) Data collected using a Prodyn BIB-100G balun. Loop filter for PLL2 is C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, C3 = 10 pF, R3 = 200 Ω,
C4 = 10 pF, R4 = 200 Ω, PLL1_CP = 450 µA, PLL2_CP = 3.2 mA.. VCO0 loop filter bandwidth = 303 kHz, phase margin = 73 degrees.
VCO1 Loop filter loop bandwidth = 151 kHz, phase margin = 64 degrees. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0.
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Electrical Characteristics (continued)
(3.15 V < VCC < 3.45 V, –40 °C < TA< 85 °C and TPCB ≤105 °C. Typical values at VCC = 3.3 V, TA= 25 °C, at the
Recommended Operating Conditions and are not assured.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NOISE FLOOR (continued)
LVDS –156.3
HSDS 6 mA –158.4
HSDS 8 mA –159.3
LMK04828, VCO0, Noise Floor
L(f)CLKout 245.76 MHz HSDS 10 mA –158.9 dBc/Hz
20 MHz Offset (15) LVPECL16 /w 240 Ω–161.6
LVPECL20 /w 240 Ω–162.5
LCPECL –162.1
LVDS –155.7
HSDS 6 mA –157.5
HSDS 8 mA –158.1
LMK04828, VCO1, Noise Floor
L(f)CLKout 245.76 MHz HSDS 10 mA –157.7 dBc/Hz
20 MHz Offset (15) LVPECL16 /w 240 Ω–160.3
LVPECL20 /w 240 Ω–161.1
LCPECL –160.8
CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO(16)
Offset = 1 kHz –126.9
Offset = 10 kHz –133.5
LMK04821 Offset = 100 kHz –135.4
VCO0
L(f)CLKout Offset = 1 MHz –149.8 dBc/Hz
SSB Phase Noise (13) LVDS –158.1
245.76 MHz Offset = 10 MHz HSDS 8 mA –161.1
LVPECL16 /w 240 Ω–161.7
Offset = 1 kHz –126.8
Offset = 10 kHz –133.4
LMK04821 Offset = 100 kHz –135.4
VCO1
L(f)CLKout Offset = 1 MHz –151.8 dBc/Hz
SSB Phase Noise (13) LVDS –157.2
245.76 MHz Offset = 10 MHz HSDS 8 mA –159.1
LVPECL16 /w 240 Ω–158.9
(15) Data collected using ADT2-1T+ balun. Loop filter is C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 =
200 Ω, PLL1_CP = 450 µA, PLL2_CP = 3.2 mA.. VCO0 loop filter bandwidth = 344 kHz, phase margin = 73 degrees. VCO1 Loop filter
loop bandwidth = 233 kHz, phase margin = 70 degrees. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0.
(16) VCXO used is a 122.88 MHz Crystek CVHD-950-122.880.
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Electrical Characteristics (continued)
(3.15 V < VCC < 3.45 V, –40 °C < TA< 85 °C and TPCB ≤105 °C. Typical values at VCC = 3.3 V, TA= 25 °C, at the
Recommended Operating Conditions and are not assured.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued)
Offset = 10 kHz –134.8
Offset = 100 kHz –135.4
LVDS –148.2
LMK04826B Offset = 1 MHz
VCO0 HSDS 8 mA
L(f)CLKout –148.6 dBc/Hz
SSB Phase Noise (14) LVPECL16 /w 240 Ω
245.76 MHz LVDS –157.8
Offset = 10 MHz HSDS 8 mA –160.4
LVPECL16 /w 240 Ω–161.5
Offset = 10 kHz –134.3
Offset = 100 kHz –133.7
LVDS –152.5
LMK04826B Offset = 1 MHz
VCO1 HSDS 8 mA
L(f)CLKout –153.6 dBc/Hz
SSB Phase Noise (14) LVPECL16 /w 240 Ω
245.76 MHz LVDS –157.3
Offset = 10 MHz HSDS 8 mA –159.6
LVPECL16 /w 240 Ω–160.5
Offset = 1 kHz –124.3
Offset = 10 kHz –134.7
LMK04828 Offset = 100 kHz –136.5
VCO0
L(f)CLKout Offset = 1 MHz –148.4 dBc/Hz
SSB Phase Noise (15) LVDS –156.4
245.76 MHz Offset = 10 MHz HSDS 8 mA –159.1
LVPECL16 /w 240 Ω–160.8
Offset = 1 kHz –124.2
Offset = 10 kHz –134.4
LMK04828 Offset = 100 kHz –135.2
VCO1
L(f)CLKout Offset = 1 MHz –151.5 dBc/Hz
SSB Phase Noise (15) LVDS –159.9
245.76 MHz Offset = 10 MHz HSDS 8 mA –155.8
LVPECL16 /w 240 Ω–158.1
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Electrical Characteristics (continued)
(3.15 V < VCC < 3.45 V, –40 °C < TA< 85 °C and TPCB ≤105 °C. Typical values at VCC = 3.3 V, TA= 25 °C, at the
Recommended Operating Conditions and are not assured.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO(16)
LVDS, BW = 12 kHz to 20 MHz 99
HSDS 8 mA, BW = 12 kHz to 20 MHz 94
LVPECL16 /w 240 Ω,
LMK04821, VCO0 96
BW = 12 kHz to 20 MHz
fCLKout = 245.76 MHz fs rms
LVPECL20 /w 240 Ω,
Integrated RMS Jitter (13) 94
BW = 12 kHz to 20 MHz
LCPECL /w 240 Ω,93
BW = 12 kHz to 20 MHz
JCLKout LVDS, BW = 12 kHz to 20 MHz 96
HSDS 8 mA, BW = 12 kHz to 20 MHz 90
LVPECL16 /w 240 Ω,
LMK04821, VCO1 92
BW = 12 kHz to 20 MHz
fCLKout = 245.76 MHz fs rms
LVPECL20 /w 240 Ω,
Integrated RMS Jitter (13) 91
BW = 12 kHz to 20 MHz
LCPECL /w 240 Ω,91
BW = 12 kHz to 20 MHz
CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued)(16)
LVDS, BW = 100 Hz to 20 MHz 106
LVDS, BW = 12 kHz to 20 MHz 104
HSDS 8 mA, BW = 100 Hz to 20 MHz 99
HSDS 8 mA, BW = 12 kHz to 20 MHz 97
LVPECL16 /w 240 Ω,
LMK04826B, VCO0 99
BW = 100 Hz to 20 MHz
fCLKout = 245.76 MHz fs rms
Integrated RMS Jitter (14) LVPECL16 /w 240 Ω,96
BW = 12 kHz to 20 MHz
LCPECL /w 240 Ω,100
BW = 100 Hz to 20 MHz
LCPECL /w 240 Ω,97
BW = 12 kHz to 20 MHz
JCLKout LVDS, BW = 100 Hz to 20 MHz 99
LVDS, BW = 12 kHz to 20 MHz 97
HSDS 8 mA, BW = 100 Hz to 20 MHz 92
HSDS 8 mA, BW = 12 kHz to 20 MHz 90
LVPECL16 /w 240 Ω,
LMK04826, VCO1 91
BW = 100 Hz to 20 MHz
fCLKout = 245.76 MHz fs rms
Integrated RMS Jitter (14) LVPECL20 /w 240 Ω,89
BW = 12 kHz to 20 MHz
LCPECL /w 240 Ω,92
BW = 100 Hz to 20 MHz
LCPECL /w 240 Ω,89
BW = 12 kHz to 20 MHz
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Electrical Characteristics (continued)
(3.15 V < VCC < 3.45 V, –40 °C < TA< 85 °C and TPCB ≤105 °C. Typical values at VCC = 3.3 V, TA= 25 °C, at the
Recommended Operating Conditions and are not assured.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued)(16)
LVDS, BW = 100 Hz to 20 MHz 112
LVDS, BW = 12 kHz to 20 MHz 109
HSDS 8 mA, BW = 100 Hz to 20 MHz 102
HSDS 8 mA, BW = 12 kHz to 20 MHz 99
LVPECL16 /w 240 Ω,
LMK04828, VCO0 98
BW = 100 Hz to 20 MHz
fCLKout = 245.76 MHz fs rms
Integrated RMS Jitter (15) LVPECL20 /w 240 Ω,95
BW = 12 kHz to 20 MHz
LCPECL /w 240 Ω,96
BW = 100 Hz to 20 MHz
LCPECL /w 240 Ω,93
BW = 12 kHz to 20 MHz
JCLKout LVDS, BW = 100 Hz to 20 MHz 108
LVDS, BW = 12 kHz to 20 MHz 105
HSDS 8 mA, BW = 100 Hz to 20 MHz 98
HSDS 8 mA, BW = 12 kHz to 20 MHz 94
LVPECL16 /w 240 Ω,
LMK04828, VCO1 93
BW = 100 Hz to 20 MHz
fCLKout = 245.76 MHz fs rms
Integrated RMS Jitter (15) LVPECL20 /w 240 Ω,90
BW = 12 kHz to 20 MHz
LCPECL /w 240 Ω,91
BW = 100 Hz to 20 MHz
LCPECL /w 240 Ω,88
BW = 12 kHz to 20 MHz
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Electrical Characteristics (continued)
(3.15 V < VCC < 3.45 V, –40 °C < TA< 85 °C and TPCB ≤105 °C. Typical values at VCC = 3.3 V, TA= 25 °C, at the
Recommended Operating Conditions and are not assured.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DEFAULT POWER on RESET CLOCK OUTPUT FREQUENCY
LMK04826 235
Default output clock frequency at
fCLKout-startup MHz
device power on (17)(18) LMK04828 315
fOSCout OSCout Frequency (7) 500 MHz
CLOCK SKEW and DELAY
DCLKoutX to SDCLKoutY Same pair, Same format (20)
FCLK = 245.76 MHz, RL= 100 Ω25
SDCLKoutY_MUX = 0 (Device Clock)
AC coupled (19)
|TSKEW| |ps|
Maximum DCLKoutX or SDCLKoutY
to DCLKoutX or SDCLKoutY Any pair, Same format (20) 50
FCLK = 245.76 MHz, RL= 100 ΩSDCLKoutY_MUX = 0 (Device Clock)
AC coupled SDCLKoutY_MUX = 1 (SYSREF)
SYSREF_DIV = 30
SYSREF_DDLY = 8 (global)
SYSREF to Device Clock setup time SDCLKoutY_DDLY = 1 (2 cycles, local)
base reference. DCLKoutX_MUX = 1 (Div+DCC+HS)
tsJESD204B See SYSREF to Device Clock –80 ps
DCLKoutX_DIV = 30
Alignment to adjust SYSREF to DCLKoutX_DDLY_CNTH = 7
Device Clock setup time as required. DCLKoutX_DDLY_CNTL = 6
DCLKoutX_HS = 0
SDCLKoutY_HS = 0
CLKin0_OUT_MUX = 0 (SYSREF Mux)
SYSREF_CLKin0_MUX = 1 (CLKin0)
SDCLKout1_PD = 0
tPDCLKin0_ Propagation Delay from CLKin0 to SDCLKout1_DDLY = 0 (Bypass) 0.65 ns
SDCLKout1 SDCLKout1 SDCLKout1_MUX = 1 (SR)
EN_SYNC = 1
LVPECL16 /w 240 Ω
fADLYmax Maximum analog delay frequency DCLKoutX_MUX = 4 1536 MHz
LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, and OSCout)
VOD Differential Output Voltage 395 |mV|
Change in Magnitude of VOD for
ΔVOD –60 60 mV
T = 25 °C, DC measurement
complementary output states AC coupled to receiver input
VOS Output Offset Voltage 1.125 1.25 1.375 V
RL= 100 Ωdifferential termination
Change in VOS for complementary
ΔVOS 35 |mV|
output states
Output Rise Time 20% to 80%, RL= 100 Ω, 245.76 MHz
TR/ TF180 ps
Output Fall Time 80% to 20%, RL= 100 Ω
ISA Output short circuit current - single Single-ended output shorted to GND –24 24 mA
ISB ended T = 25 °C
Output short circuit current -
ISAB Complimentary outputs tied together –12 12 mA
differential
(17) OSCout will oscillate at start-up at the frequency of the VCXO attached to OSCin port.
(18) LMK04821 has no DCLKoutX or SDCLKoutY outputs which oscillate at power on. Only OSCout oscillates at power on.
(19) Equal loading and identical clock output configuration on each clock output is required for specification to be valid. Specification not valid
for delay mode.
(20) LVPECL uses 120 Ωemitter resistor, LVDS and HSDS uses 560 Ωshunt.
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SNAS605AR –MARCH 2013–REVISED DECEMBER 2015 www.ti.com
Electrical Characteristics (continued)
(3.15 V < VCC < 3.45 V, –40 °C < TA< 85 °C and TPCB ≤105 °C. Typical values at VCC = 3.3 V, TA= 25 °C, at the
Recommended Operating Conditions and are not assured.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
6 mA HSDS CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
VCC -
VOH 1.05
T = 25 °C, DC measurement
Termination = 50 Ωto VCC -
VOL VCC - 1.42 V 1.64
VOD Differential Output Voltage 590 |mV|
Change in VOD for complementary
ΔVOD –80 80 mVpp
output states
8 mA HSDS CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
Output Rise Time 245.76 MHz, 20% to 80%, RL= 100 Ω
TR/ T F170 ps
Output Fall Time 245.76 MHz, 80% to 20%, RL= 100 Ω
VCC -
VOH 1.26
T = 25 °C, DC measurement
Termination = 50 Ωto VCC
VOL VCC - 1.64 V –2.06
VOD Differential Output Voltage 800 |mV|
Change in VOD for complementary
ΔVOD –115 115 mVpp
output states
10 mA HSDS CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
VCC -
VOH 0.99
T = 25 °C, DC measurement
Termination = 50 Ωto VCC -
VOL VCC - 1.43 V 1.97
VOD 980 mVpp
Change in VOD for complementary
ΔVOD –115 115 mVpp
output states
LVPECL CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
20% to 80% Output Rise RL= 100 Ω, emitter resistors = 240 Ωto
GND
TR/ TF150 ps
DCLKoutX_TYPE = 4 or 5
80% to 20% Output Fall Time (1600 or 2000 mVpp)
1600 mVpp LVPECL CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
VCC -
VOH Output High Voltage V
1.04
DC Measurement VCC -
VOL Output Low Voltage Termination = 50 Ωto V
1.80
VCC - 2.0 V
Output Voltage
VOD 760 |mV|
Figure 9
2000 mVpp LVPECL CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
VCC -
VOH Output High Voltage V
1.09
DC Measurement VCC -
VOL Output Low Voltage V
Termination = 50 Ωto VCC - 2.3 V 2.05
Output Voltage
VOD 960 |mV|
Figure 9
LCPECL CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
VOH Output High Voltage 1.57 V
VOL Output Low Voltage DC Measurement 0.62 V
Termination = 50 Ωto 0.5 V
Output Voltage
VOD 950 |mV|
Figure 9
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