Texas Instruments ThunderLAN TNETE211 Manual

ThunderLAN
TNETE100A, TNETE110A, TNETE211
Programmer’s
Guide
October 1996 Network Business Products

Printed in U.S.A., October 1996
L411001–9761 revisionA SPWU013A

ThunderLAN t
Programmer’s Guide
TNETE100A, TNETE110A, TNETE211
Literature Number: SPWU013A
Manufacturing Part Number: L411001-9761 revision A
October 1996

Running Title—Attribute Reference
ii
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TIwarrantsperformanceofitssemiconductorproductsandrelatedsoftwaretothespecifications
applicableatthetimeofsaleinaccordancewithTI’sstandardwarranty.Testingandotherquality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Useof TIproducts insuch applicationsrequires thewritten approvalof anappropriate TIofficer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
representthatanylicense,eitherexpressorimplied,isgrantedunderanypatentright,copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.
Copyright 1996, Texas Instruments Incorporated

iii
Preface
Read This First
About This Manual
The ThunderLAN Programmer’s Guide assists you in using the following
implementations of ThunderLAN networking hardware:
- TNETE100A Ethernet t controller
- TNETE110A Ethernet controller
- TNETE211 100 VG-AnyLAN physical media interface (PMI)
How to Use This Manual
The goal of this book is to assist you in the development of drivers for the
ThunderLAN controllers. This document contains the following chapters:
- Chapter 1, ThunderLAN Overview, describes some Texas
Instruments-specific hardware features. These include the enhanced
media independent interface (MII), which passes interrupts from an
attached physical interface (PHY) to the host.
- Chapter 2, ThunderLAN Registers, shows how to access the various
ThunderLAN registers and how to use these registers to access external
devices attached to ThunderLAN.
- Chapter 3, Initializing and Resetting, discusses how to initialize and reset
the controller and the attached PHYs.
- Chapter 4, Interrupt Handling, describes what happens when interrupts
occur and how to correct failure conditions.
- Chapter 5, List Structures, describes how to pass data to ThunderLAN
using a system of linked list structures.
- Chapter 6, Transmitting and Receiving Frames, explains the format and
procedurefortransmittingandreceiving,aswellasthelinkedliststructure
required.
- Chapter 7, Physical Interface, discusses the features of ThunderLAN
which support IEEE 802.3- and 802.12-compliant devices.

Notational Conventions
iv
Notational Conventions
This document uses the following conventions:
- Program listings, program examples, and interactive displays are shown
in a special font. Examples use a bold version of the special font for
emphasis. Here is a sample program listing:
11 0005 0001 .field 1, 2
12 0005 0003 .field 3, 4
13 0005 0006 .field 6, 3
14 0006 .even
- A lower case ‘x’ in a number indicates that position can be anything (don’t
care). Here are some examples:
J 0x00
J 0x0004
J 0x4000501
Related Documentation
InformationTechnologyLocalandMetropolitanAreaNetworks–Part12:
Demand-Priority Access Method, Physical Layer and Repeater
Specifications for 100-Mb/s Operation,
Draft 8.0 of the Revision
Marked for Technical changes of IEEE Standard 802.12.
MAC Parameters, Physical Layer, Medium Attachment Units and
Repeater for 100-Mb/s Operation, Draft5.0oftheSupplementto 1993
version of ANSI/IEEE Std. 802.3: Carrier Sense Multiple Access with
Collision Detection (CSMA/CD) Access Method & Physical Layer
Specifications.
PCI Local Bus Specification , Revision 2.0 is the specification which
ThunderLAN is designed to meet. To obtain copies, contact PCI Special
InterestGroup,P.O.Box14070,Portland,OR97214,1–800–433–5177.
ThunderLAN Adaptive Performance Optimization Technical Brief (Texas
Instruments literature number SPWT089) discusses specific buffering
and pacing techniques for improving adapter performance by adjusting
the resources and transmit procedures to achieve optimal transmission
rate and minimal CPU use.
XL24C02 Data Sheet, EXEL Microelectronics, 1993, which contains the
device specifications for the XL24C02 2M-bit electrically erasable
EPROM.

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v Read This First
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Trademarks
vi
Trademarks
Ethernet is a trademark of Xerox Corporation.
ThunderLAN and Adaptive Performance Optimization are trademarks of Texas Instruments
Incorporated.

Contents
vii
Contents
1 ThunderLAN Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 ThunderLAN Architecture 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Networking Protocols 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 PCI Interface 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.1 PCI Cycles 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2 Byte Ordering 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 ThunderLAN Registers 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Register Addresses 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 PCI Configuration Space 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Host Registers 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Internal Registers 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 MII PHY Registers 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 External Devices 2-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1 BIOS ROM 2-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2 LEDs 2-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.3 EEPROM 2-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.4 ThunderLAN EEPROM Map 2-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Initializing and Resetting 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Initializing 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 Finding the Network Interface Card (NIC) 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 Finding the Controller in Memory and I/O Space 3-4. . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3 Finding Which Interrupt was Assigned 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.4 Turning on the I/O Port and Memory Address Decode 3-6. . . . . . . . . . . . . . . . . . . .
3.1.5 Recovering the Silicon Revision Value 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.6 Setting the PCI Bus Latency Timer 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Resetting 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Hardware Reset 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 Software Reset 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Interrupt Handling 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Loading and Unloading an Interrupt Service Routine (ISR) 4-2. . . . . . . . . . . . . . . . . . . . . . .
4.2 Prioritizing Adapter Interrupts 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Acknowledging Interrupts (Acking) 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Interrupt Type Codes 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
viii
4.4.1 No Interrupt (Invalid Code). Int_type = 000b 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2 Tx EOF Interrupt. Int_type = 001b 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.3 Statistics Overflow Interrupt. Int_type = 010b 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.4 Rx EOF Interrupt. Int_type = 011b 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.5 Dummy Interrupt. Int_type = 100b 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.6 Tx EOC Interrupt. Int_type = 101b 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.7 Network Status Interrupt. Int_type = 110b and Int_Vec = 00h 4-9. . . . . . . . . . . . . .
4.4.8 Adapter Check Interrupt. Int_type = 110b and Int_Vec ≠00h 4-10. . . . . . . . . . . . .
4.4.9 Rx EOC Interrupt. Int_type = 111b 4-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 List Structures 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 List Management 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 CSTAT Field Bit Requirements 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 One-Fragment Mode 5-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Receive List Format 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 Transmit List Format 5-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Transmitting and Receiving Frames 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Frame Format 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.1 Receive (Rx) Frame Format 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.2 Transmit (Tx) Frame Format 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 GO Command 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.1 Starting Frame Reception (Rx GO Command) 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.2 Starting Frame Transmission (Tx GO Command) 6-6. . . . . . . . . . . . . . . . . . . . . . . .
7 Physical Interface (PHY) 7-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 MII-Enhanced Interrupt Event Feature 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Nonmanaged MII Devices 7-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Bit-Rate Devices 7-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 PHY Initialization 7-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Register Definitions A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1 PCI Configuration Registers A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.1 PCI Autoconfiguration from External 24C02 Serial EEPROM A-3. . . . . . . . . . . . . .
A.1.2 PCI Vendor ID Register (@ 00h) Default = 104Ch A-4. . . . . . . . . . . . . . . . . . . . . . .
A.1.3 PCI Device ID Register (@ 02h) Default = 0500h A-4. . . . . . . . . . . . . . . . . . . . . . . .
A.1.4 PCI Command Register (@ 04h) A-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.5 PCI Status Register (@ 06h) A-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.6 PCI Base Class Register (@ 0Bh) A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.7 PCI Subclass Register (@ 0Ah) A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.8 PCI Program Interface Register (@ 09h) A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.9 PCI Revision Register (@ 08h) A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.10 PCI Cache Line Size Register (@ 0Ch) A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.11 PCI Latency Timer Register (@ 0Dh) A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.12 PCI I/O Base Address Register (@ 10h) A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
ix Contents
A.1.13 PCI Memory Base Address Register (@ 14h) A-8. . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.14 PCI BIOS ROM Base Address Register (@ 30h) A-8. . . . . . . . . . . . . . . . . . . . . . . .
A.1.15 PCI NVRAM Register (@ 34h) A-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.16 PCI Interrupt Line Register (@ 3Ch) A-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.17 PCI Interrupt Pin Register (@ 3Dh) A-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.18 PCI Min_Gnt (@ 3Eh) and Max_Lat (@ 3Fh) Registers A-10. . . . . . . . . . . . . . . . . .
A.1.19 PCI Reset Control Register (@ 40h) A-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.20 CardBus CIS Pointer (@ 28h) A-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2 Adapter Host Registers A-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2.1 Host Command Register–HOST_CMD @ Base_Address + 0 (Host) A-12. . . . . .
A.2.2 Channel Parameter Register–CH_PARM @ Base_Address + 4 (Host) A-17. . . .
A.2.3 Host Interrupt Register–HOST_INT @ Base_Address + 10 (Host) A-18. . . . . . . .
A.2.4 DIO Address Register–DIO_ADR @ Base_Address + 8 (Host) A-19. . . . . . . . . . .
RAM Addressing A-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2.5 DIO Data Register–DIO_DATA @ Base_Address + 12 (Host) A-20. . . . . . . . . . . .
A.3 Adapter Internal Registers A-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.3.1 Network Command Register–NetCmd @ 0x00 (DIO) A-23. . . . . . . . . . . . . . . . . . .
A.3.2 Network Serial I/O Register–NetSio @ 0x00 (DIO) A-24. . . . . . . . . . . . . . . . . . . . .
A.3.3 Network Status Register–NetSts @ 0x00 (DIO) A-25. . . . . . . . . . . . . . . . . . . . . . . .
A.3.4 Network Status Mask Register–NetMask @ 0x00 (DIO) A-26. . . . . . . . . . . . . . . . .
A.3.5 Network Configuration Register–NetConfig @ 0x04 (DIO) A-27. . . . . . . . . . . . . . .
A.3.6 Manufacturing Test Register–ManTest @ 0x04 (DIO) A-29. . . . . . . . . . . . . . . . . . .
A.3.7 Default PCI Parameter Registers–@ 0x08–0x0C (DIO) A-29. . . . . . . . . . . . . . . . .
A.3.8 General Address Registers–Areg_0-3 @ 0x10–0x24 (DIO) A-30. . . . . . . . . . . . . .
A.3.9 Hash Address Registers–HASH1/HASH2 @ 0x28–0x2C (DIO) A-31. . . . . . . . . .
A.3.10 Network Statistics Registers–@ 0x30–0x40 (DIO) A-32. . . . . . . . . . . . . . . . . . . . . .
A.3.11 Adapter Commit Register–Acommit @ 0x40 (DIO) (Byte 3) A-34. . . . . . . . . . . . . .
A.3.12 LED Register–LEDreg @ 0x44 (DIO) (Byte 0) A-35. . . . . . . . . . . . . . . . . . . . . . . . .
A.3.13 Burst Size Register–BSIZEreg @ 0x44 (DIO) (Byte 1) A-36. . . . . . . . . . . . . . . . . .
A.3.14 Maximum Rx Frame Size Register–MaxRx @ 0x44 (DIO) (Bytes 2+3) A-37. . .
A.3.15 Interrupt Disable Register - INTDIS @ 0x48 (DIO) (BYTE 0) A-38. . . . . . . . . . . . .
A.4 10Base-T PHY Registers A-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.4.1 PHY Generic Control Register–GEN_ctl @ 0x0 A-40. . . . . . . . . . . . . . . . . . . . . . . .
A.4.2 PHY Generic Status Register–GEN_sts @ 0x1 A-42. . . . . . . . . . . . . . . . . . . . . . . .
A.4.3 PHY Generic Identifier–GEN_id_hi/GEN_id_lo @ 0x2/0x3 A-44. . . . . . . . . . . . . . .
A.4.4 Autonegotiation Advertisement Register–AN_adv @ 0x4 A-45. . . . . . . . . . . . . . . .
A.4.5 Autonegotiation Link Partner Ability Register–AN_lpa @ 0x5 A-46. . . . . . . . . . . . .
A.4.6 Autonegotiation Expansion Register–AN_exp @ 0x6 A-47. . . . . . . . . . . . . . . . . . .
A.4.7 ThunderLAN PHY Identifier High/Low–TLPHY_id @ 0x10 A-48. . . . . . . . . . . . . . .
A.4.8 ThunderLAN PHY Control Register–TLPHY_ctl @ 0x11 A-49. . . . . . . . . . . . . . . . .
A.4.9 ThunderLAN PHY Status Register–TLPHY_sts @ 0x12 A-50. . . . . . . . . . . . . . . . .

Contents
x
B TNETE211 100VG-AnyLAN Demand Priority Physical Media Independent (PMI) Interface B-1
B.1 100VG-AnyLAN Training B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B.2 TNETE211 Register Descriptions B-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B.2.1 PHY Generic Control Register–GEN_ctl @ 0x0 B-7. . . . . . . . . . . . . . . . . . . . . . . . .
B.2.2 PHY Generic Status Register –GEN_sts @ 0x1 B-8. . . . . . . . . . . . . . . . . . . . . . . . .
B.2.3 PHY Generic Identifier–GEN_id_hi/GEN_id_lo @ 0x2/0x3 B-9. . . . . . . . . . . . . . . .
B.2.4 ThunderLAN PHY Identifier High/Low–TLPHY_id @ 0x10 B-9. . . . . . . . . . . . . . . .
B.2.5 ThunderLAN PHY Control Register–TLPHY_ctl @ 0x11 B-9. . . . . . . . . . . . . . . . . .
B.2.6 ThunderLAN PHY Status Register–TLPHY_sts @ 0x12 B-11. . . . . . . . . . . . . . . . .
C TNETE100PM/TNETE110PM C-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures
xi Contents
Figures
1–1 The ThunderLAN Controller 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 PCI Bus Byte Assignment 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 How ThunderLAN Registers are Addressed 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 The PCI Configuration Space Registers 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 Configuration EEPROM Data Format 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 Host Registers 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 Internal Registers 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 MII PHY Registers 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 Adapter Check Interrupt Fields 4-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 List Pointers and Buffers 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Linked List Management Technique 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 Receive List Format – One_Frag = 0 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 Receive List Format – One_Frag = 1 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–5 Receive CSTAT Request Fields 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–6 Receive CSTAT Complete Fields 5-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–7 Transmit List Format 5-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–8 Transmit CSTAT Request Fields 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–9 Transmit CSTAT Complete Fields 5-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Token Ring Logical Frame Format (Rx) 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 Ethernet Logical Frame Format (Rx) 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–3 Token Ring Logical Frame Format (Tx) 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–4 Ethernet Logical Frame Format (Tx) 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–1 100VG-AnyLAN Support Through ThunderLAN’s Enhanced 802.3u MII 7-2. . . . . . . . . . . . . .
7–2 MII Frame Format: Read 7-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–3 MII Frame Format: Write 7-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–4 Assertion of Interrupt Waveform on the MDIO Line 7-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–5 Waveform Showing Interrupt Between MII Frames 7-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–1 PCI Configuration Register Address Map A-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–2 Configuration EEPROM Data Format A-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–3 Host Interface Address Map A-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–4 ADAPTER Internal Register Map A-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–5 Default PCI Parameter Register A-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–6 Ethernet Error Counters A-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–7 Demand Priority Error Counters A-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–8 10Base-T PHY Registers A-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–1 802.12 Training Frame Format B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–2 Training Flowchart B-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–3 TNETE211 Registers B-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables
xii
Tables
2–1 ThunderLAN EEPROM Map 2-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 Adapter Check Bit Definitions 4-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 Adapter Check Failure Codes 4-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 Relevance of Error Status Bits for Adapter Check Failure Codes 4-13. . . . . . . . . . . . . . . . . . .
5–1 Receive Parameter List Fields 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Receive CSTAT Request Bits 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 Receive CSTAT Complete Bits 5-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 Transmit Parameter List Fields 5-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–5 Transmit CSTAT Request Bits 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–6 Transmit CSTAT Complete Bits 5-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–1 ThunderLAN MII Pins (100M-bps CSMA/CD) 7-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–2 Possible Sources of MII Event Interrupts 7-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–1 PCI Command Register Bits A-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–2 PCI Status Register Bits A-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–3 PCI NVRAM Register Bits A-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–4 PCI Reset Control Register Bits A-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–5 Host_CMD Register Bits A-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–6 HOST_INT Register Bits A-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–7 DIO_ADR Register Bits A-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–8 Network Command Register Bits A-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–9 Network Serial I/O Register Bits A-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–10 Network Status Register Bits A-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–11 Network Status Mask Register Bits A-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–12 Network Configuration Register Bits A-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–13 MAC Protocol Selection Codes A-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–14 Ethernet Error Counters A-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–15 Demand Priority Error Counters A-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–16 Adapter Commit Register Bits A-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–17 Burst Size Register Bits A-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–18 Demand Priority Error Counters A-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–19 PHY Generic Control Register Bits A-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–20 PHY Generic Status Register Bits A-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–21 Autonegotiation Advertisement Register Bits A-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–22 Autonegotiation Link Partner Ability Register Bits A-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–23 Autonegotiation Expansion Register Bits A-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–24 ThunderLAN PHY Control Register Bits A-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables
xiii Contents
A–25 ThunderLAN PHY Status Register Bits A-50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–1 PHY Generic Control Register Bits B-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–2 PHY Generic Status Register Bits B-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–3 ThunderLAN PHY Control Register Bits B-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–4 ThunderLAN PHY Status Register Bits B-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xiv

Running Title—Attribute Reference
1-1 Chapter Title—Attribute Reference
ThunderLAN Overview
The ThunderLAN family consists of highly integrated, single-chip networking
hardware.Itusesahigh-speedarchitecturethatprovidesacompleteperipher-
al component interconnect (PCI)- to-10Base-T/AUI (adapter unit interface)
Ethernet solution. It allows the flexibility to handle 100M-bps Ethernet proto-
cols as the user’s networking requirements change.
TheTNETE100A,oneimplementationoftheThunderLANarchitecture,isan
intelligent protocol network interface. Modular support for the 100 Base-T
(IEEE 802.3u) and 100VG-AnyLAN (IEEE 802.12) is provided via a media
independent interface (MII). The TNETE110A is the same device without the
MIIandis10Mbpsonly.ThunderLANusesasingledriversuitetosupportmul-
tiple networking protocols.
ThunderLAN architecture was designed to achieve the following goals:
- High performance with low use of host CPU
- Simplicity of design
- Ease of upgrade to higher speed networks
- Freedom of choice of network protocol
ThunderLANallowsasimplesystemdesignbyintegratingaPCIcontroller,an
internal first in, first out (FIFO) buffer, a LAN controller, and a 10Base-T physi-
cal interface (PHY).
Topic Page
1.1 ThunderLAN Architecture 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Networking Protocols 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 PCI Interface 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1

ThunderLAN Architecture
1-2
1.1 ThunderLAN Architecture
Figure 1–1.The ThunderLAN Controller
PCI Bus PCI
controller
FIFO
registers
Multiplexed
SRAM
LAN
controller PHY
LAN
802.3
100M-bps
MII
An integrated PHY provides interface functions for 10Base-T carrier sense
multiple access/collision detect (CSMA/CD) (Ethernet). A MII is used to com-
municate with the integrated PHY. The PHY is an independent module from
the rest of the ThunderLAN controller. This allows the PHY to be reset and
placed in a power-down mode.
The PCI controller is responsible for direct memory accesses (DMAs) to and
from the host memory. It is designed to relieve the host from time-consuming
data movements, thereby reducing use of the host CPU. The PCI interface
supports a 32-bit data path.
ThunderLAN supports two transmit and one receive channels. The demand
priority protocol supports two frame priorities: normal and priority. The two
transmit channels provide independent host channels for these two priority
types. CSMA/CD protocols only support a single frame priority, but the two
channels can be used to prioritize network access, if needed. All received
frames pass through the single receive channel.
ThunderLAN’smultiplexedSRAMis3.375Kbytesinsize.Thisallowsittosup-
portone 1.5KbyteFIFOfor receive,two0.75Kbyte FIFOsforthetwotransmit
(Tx)channels,andthree 128-byte lists (see section 5.1, ListManagement).In
one-channel mode, the two Tx channels are combined, giving a single 1.5K-
byte FIFO for a single Tx channel. Supporting 1.5K byte of FIFO per channel
allows full frame buffering of Ethernet frames. PCI latency is such that a mini-
mum of 500 bytes of storage is required to support 100M-bps LANs. (Refer to
the
PCI Local Bus Specification, revision 2.0, section 3.5, Latency).
ThunderLAN’s industry-standard MII permits ease of upgrade. External de-
vices can be connected to the MII and managed, if they support the two-wire
management interface. PHY layer functions for 100M-bps CSMA/CD and de-
mand priority are connected to the MII.

Networking Protocols
1-3 ThunderLAN Overview
1.2 Networking Protocols
The MII also allows freedom in choosing a networking protocol. It allows the
useofstandard100MbpsCSMA/CDPHYchips.ThunderLANusesthesesig-
nal lines to interface to an external 100M bps demand priority PHY. This gives
ThunderLAN the flexibility necessary to handle 10Base-T, 10Base-2,
10Base-5AUI,100Base-TX,100Base-T4,100Base-FX,and100VG-AnyLAN
today, while supporting emerging technologies.
ThunderLAN is designed to simplify the software used to transmit frames, re-
ceive frames, and service the PHY events. It accomplishes this by integrating
time-consuming tasks into the controller. These tasks include:
- The DMA of data into and out of the controller
- A simplified, interrupt-driven frame buffer management technique
- The elimination of PHY register polling through MII interrupts
DMA of data is handled through list structures. ThunderLAN’s method of han-
dling data through list structures has parallels with the method used in Texas
Instruments TI380 COMMprocessors. There are some differences, such as
the use of a 0 forward pointer.
ThunderLANisdesigned to meet PCILocalBusSpecification ,revision2.0 for
its PCI interface standards.