THine SerDes THCV231-Q User manual

THCV231-Q_THCV236-Q_Rev.2.60_E
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THCV231-Q and THCV236-Q
SerDes transmitter and receiver with bi-directional transceiver
General Description
The THCV231-Q and THCV236-Q are designed to
support video data transmission between the host and
display.
THCV231-Q
One high-speed lane can carry up to 14bits data at a
pixel clock frequency from 12MHz to 160MHz.
THCV236-Q
One high-speed lane can carry up to 32bit data and
3bits of synchronizing signals at a pixel clock
frequency from 6MHz to 160MHz by converting
RGB444 to YCbCr422.
The chipset, which has one high-speed data lane,
can transmit video data up to 1080p/60Hz.
The maximum serial data rate is 4.00Gbps/lane.
Features
Data width selectable
Wide frequency range
AC coupling for high-speed lanes
CDR requires no external frequency reference
Wide range supply voltage from 1.7V to 3.6V
Additional spread spectrum on data stream
2-wire serial interface bridge function(400kbps)
Remote side GPIO control and monitoring
THCV231-Q
QFN32 (5mm x 5mm) with exposed pad ground
THCV236-Q
QFN64 (9mm x 9mm) with exposed pad ground
AEC-Q100 Grade 2 (-40 to 105degC)
ISO/TS16949 compliant
EU RoHS compliant
Block Diagram
THCV236-Q
CDR
Controls
Formatter
YCbCr to RGB
D31-D0
HSYNC
VSYNC
DE
CLKOUT
Settings
2-wire I/F
SDA/SCL
RXP
RXN
Deserializer
RCMP
RCMN
LVCMOS output
THCV231-Q
LVCMOS input
PLL
Controls
Formatter
D11-D0
HSYNC
VSYNC
CLKIN
Settings
2-wire I/F
SDA/SCL
TXP
TXN
Serializer
OSC
TCMP
TCMN
LDO
OSC
LDO
CAPOUT
CAPINA
CAPINP
CAPOUT
CAPINA

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Contents Page
General Description .............................................................................................................................................. 1
Features.................................................................................................................................................................. 1
Block Diagram....................................................................................................................................................... 1
Pin Configuration.................................................................................................................................................. 4
Pin Description ...................................................................................................................................................... 5
Pin Description for THCV231-Q ........................................................................................................................ 5
Pin Description for THCV236-Q ........................................................................................................................ 6
Functional Overview........................................................................................................................................... 10
Functional Description........................................................................................................................................ 10
Internal Reference Output/Input Function (CAPOUT, CAPINA, CAPINP)............................................ 10
Power Down (PDN1, PDN0, PDN)................................................................................................................. 11
Pre-emphasis and Drive Select Function (THCV231-Q only)..................................................................... 11
Permanent Clock Output (THCV236-Q only).............................................................................................. 11
Spread Spectrum Clock Generator (SSCG).................................................................................................. 12
Data Enable...................................................................................................................................................... 14
Hot-Plug Function........................................................................................................................................... 15
Lock Detect Function...................................................................................................................................... 15
Field BET Operation....................................................................................................................................... 16
Data Width and Frequency Range Select Function ..................................................................................... 18
Data Mapping.................................................................................................................................................. 18
2-wire serial I/F Mode..................................................................................................................................... 19
2-wire serial I/F Device ID setting ................................................................................................................ 19
2-wire serial I/F Clock Stretching ................................................................................................................. 19
Read/Write access to Sub-Link Master Register ........................................................................................... 21
Read/Write access to Sub-Link Slave Register ............................................................................................. 22
Read/Write access to remote side 2-wire serial slave devices connected to Sub-Link Slave Device............ 24
GPIO.............................................................................................................................................................. 28
Interruption.................................................................................................................................................... 30
Register Map........................................................................................................................................................ 31
Absolute Maximum Ratings............................................................................................................................... 40
Recommended Operating Conditions................................................................................................................ 40
Electrical Specification........................................................................................................................................ 40
LVCMOS DC Specification .............................................................................................................................. 40
CML DC Specification...................................................................................................................................... 41
CML Bi-Directional DC Specification.............................................................................................................. 41

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Supply Current .................................................................................................................................................. 42
Switching Characteristics .................................................................................................................................. 42
AC Timing Diagrams and Test Circuits ............................................................................................................ 46
LVCMOS Input, Output Switching Characteristics .......................................................................................... 46
CML Output Switching Characteristics............................................................................................................. 47
CML Bi-directional Output Test Circuit............................................................................................................ 48
Latency Characteristics ..................................................................................................................................... 49
Lock and Unlock Sequence............................................................................................................................... 50
2-wire serial I/F Switching Characteristics ....................................................................................................... 51
GPIO Switching Characteristics........................................................................................................................ 53
PCB Layout Guideline regarding VDD and AVDD for THCV236-Q............................................................. 55
Package................................................................................................................................................................. 56
Notices and Requests........................................................................................................................................... 58

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Pin Configuration
PDN
D0
1
TEST1
2
TEST2
3
RF/BETOUT
4
SDA
5
SCL
6
GPIO3
7
GPIO4
8
9
10 D1
D2
11
12 D3
CLKIN
13
14 D4
D5
15
16 VDD
18 17
D7
20 19 D8 22 21
D10
23
VSYNC D11
28
27
26
25
TCMN
TCMP
CAPOUT
HSYNC
32
31
30
29
CAPINA
TXP
THCV231-Q (QFN 32pin)
24
(TOP VIEW)
33 EXPGND
TXN
CAPINP
A
VDD
D9 D6
THCV236-Q (QFN 64pin)
PDN0
D27
1
PDN1
2
LFSEL
3
TEST1
4
TEST2
5
RF/BETOUT
6
COL0/INT/GPIO2
7
COL1/SD0
8
OUTSEL/SD1
9
TTLDRV/SD2/AIN0/GPIO1
10
LATEN/SD3/AIN1/GPIO0
11
D31
12
D30
13
D29
14
D28
15
VDD
17
18 D26
D25/GPIO4
19
20 D24/GPIO3
D23
21
22 D22
D21
23
24 D20
VDD
25
26 CLKOUT
D19
27
28 D18
D17
29
30 D16
D15
31
32 VDD
34 33 D14 36 35
D11 D12
38 37
D9 D10
40 39
A
VDD
D8
42 41
D7 VDD
44 43
D5 D6
46 45
D3 D4
47
VSYNC D2
52
51
50
49
D1
DE
HSYNC
VDD
56
55
54
53
CAPOUT
LOCKN/MSSEL
HTPDN/SUBMODE
D0
60
59
58
57
MAINMODE/RCMN
CAPINA
RXP
RXN
64
63
62
61
BET
OE
HFSEL/RCMP
16
48
(TOP VIEW)
65 EXPGND
D13
RXDEFSEL

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Pin Description
Pin Description for THCV231-Q
Pin Name Pin No. Type Description
TXP 29 CO High-Speed CML Signal Output (Main-Link)
TXN 30 CO High-Speed CML Signal Output (Main-Link)
TCMP 27 CB CML Signal Bidirectional Input/Output (Sub-Link)
TCMN 28 CB CML Signal Bidirectional Input/Output (Sub-Link)
GPIO4 8 B GPIO4 : General Purpose Input/Output.
When GPIO4 is used as Open-Drain Output, it must be
connected with a pull-up resistor to VDD.
When GPIO4 is used as push pull output, no external
component is required.
LATEN : Latch select input under Field BET (Sub-
Link)
0 : Forbidden
1 : Latched result
GPIO3 7 B GPIO3 : General Purpose Input/Output.
When GPIO3 is used as Open-Drain Output, it must be
connected with a pull-up resistor to VDD.
When GPIO3 is used as push pull output, no external
component is required.
SCL 6 B SCL input/output for 2-wire serial I/F.
SDA 5 B SDA input/output for 2-wire serial I/F.
CLKIN 13 I Clock Input
D11-D0 23,22,20-17,15,14,12-
9
I Pixel Data Input
HSYNC 25 I HSYNC Input
VSYNC 24 I VSYNC Input
RF/BETOUT 4 B RF : Input Clock Triggering edge select. See Figure 17.
0 : Falling Edge
1 : Rising Edge
BETOUT : Field BET Result Output when Field BET
mode.
PDN 1 IL Power Down
0 : Power Down
1 : Normal Operation
TEST2 3 I Test pin. Must be tied to Ground for normal operation.
TEST1 2 IL Test pin. Must be tied to Ground for normal operation.
CAPOUT 26 PWR Decoupling Capacitor Pin, 1.2V output.
CAPINA 31 PWR Reference Input for Analog Circuit. Must be tied to
CAPOUT.
CAPINP 32 PWR Reference Input for Analog Circuit. Must be tied to
CAPOUT.
VDD 16 PWR 1.7-3.6V Digital Power Supply Pin for LVCMOS I/O
AVDD 21 PWR 1.7-3.6V Analog Power Supply Pin for LDO
EXPGND 33 GND Exposed Pad Ground. Must be tied to the PCB ground
plane through an array of vias.
CO : CML Output buffer , CB : CML Bi-directional buffer
I : LVCMOS Input buffer , IL : Low Speed LVCMOS Input buffer , B : LVCMOS Bi-directional buffer
PWR : Power supply , GND : Ground

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Pin Description for THCV236-Q
Pin Name Pin No. Type Description
RXP 58 CI High-Speed CML Signal Input(Main-Link)
RXN 57 CI High-Speed CML Signal Input(Main-Link)
HFSEL/RCM
P
61 CB/I HFSEL : High Frequency Mode select when PDN1=0.
0 : High Frequency Mode Disable
1 : High Frequency Mode Enable
RCMP : CML Signal Bi-directional Input/Output(Sub-Link)
when PDN1=1.
MAINMODE/
RCMN
60 CB/I MAINMODE : Setting V-by-One® HS Mode or Sync Free Mode
when PDN1=0
0 : V-by-One®HS Mode
1 : Sync Free Mode
RCMN : CML Signal Bi-directional Input/Output(Sub-Link)
when PDN1=1.
HTPDN/
SUBMODE
54 BO HTPDN : Hot Plug Detect Output when PDN1=0. Must be
connected to Tx HTPDN with 10kΩpull-up resistor.
SUBMODE : Sub-Link Mode Select when PDN1=1.
0 : 2-wire serial I/F Mode (default No Clock Stretching mode)
1 : Low Speed Data Bridge Mode
Forbid setting 1 when connecting with THCV231-Q.
LOCKN/
MSSEL
55 BO LOCKN : Lock Detect Output when PDN1=0. Must be connected
to Tx LOCKN with 10kΩpull-up resistor.
MSSEL : Sub-Link Master/Slave Select when PDN1=1.
0 : Sub-Link Master side(inside 2-wire serial I/F is slave)
1 : Sub-Link Slave side(inside 2-wire serial I/F is master)
Sub-Link Master is connected to HOST MPU.
Forbid setting 1 when connecting with THCV231-Q.
LATEN/SD3/
AIN1/GPIO0
11 B LATEN : Latch select input under Field BET(Main-Link or Sub-
Link).
0 : NOT Latched result
1 : Latched result
SD3 : Sub-Link Data Input/Output when PDN1=1 and
SUBMODE=1.
When Sub-Link is Master (MSSEL=0), SD3 is output.
When Sub-Link is Slave (MSSEL=1), SD3 is input.
AIN1 : Device ID setting for 2-wire serial I/F when
SUBMODE=0 and MSSEL=0. See Table 19.
GPIO0 : General Purpose Input/Output when SUBMODE=0 and
MSSEL=1.
When GPIO0 is used as Open-Drain Output, it must be connected
with a pull-up resistor to VDD.
When GPIO0 is used as push pull output or input, no external
component is required.

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TTLDRV/SD2
/
AIN0/GPIO1
10 B TTLDRV : LVCMOS Output Drive Strength Select when
PDN1=0.
0 : Weak Drive Strength
1 : Normal Drive Strength
SD2 : Sub-Link Data Input/Output when PDN1=1 and
SUBMODE=1.
When Sub-Link is Master (MSSEL=0), SD2 is input.
When Sub-Link is Slave (MSSEL=1), SD2 is output.
AIN0 : Device ID setting for 2-wire serial I/F when
SUBMODE=0 and MSSEL=0. See Table 19.
GPIO1 : General Purpose Input/Output when SUBMODE=0 and
MSSEL=1.
When GPIO1 is used as Open-Drain Output, it must be connected
with a pull-up resistor to VDD.
When GPIO1 is used as push pull output or input, no external
component is required.
OUTSEL/SD1 9 B OUTSEL : Permanent Clock Output Enable when PDN1=0.
0 : Permanent Clock Output Disable
1 : Permanent Clock Output Enable
SD1 : Sub-Link Data Input/Output when PDN1=1.
When SUBMODE=0, SD1 is used as SCL input/output for 2-wire
serial I/F, requires pull-up resistor to VDD.
When SUBMODE=1 and MSSEL=0, SD1 is input.
When SUBMODE=1 and MSSEL=1, SD1 is output.
COL1/SD0 8 B COL1 : Color Space Converter Enable when PDN1=0 and
MAINMODE=0.
0 : Color Space Converter Disable
1 : Color Space Converter Enable
Data Width Setting when PDN1=0 and MAINMODE=1. See
Table 16.
SD0 : Sub-Link Data Input/Output when PDN1=1.
When SUBMODE=0, SD0 is used as SDAinput/output for 2-wire
serial I/F, requires pull-up resistor to VDD.
When SUBMODE=1 and MSSEL=0, SD0 is input.
When SUBMODE=1 and MSSEL=1, SD0 is output.
COL0/INT/
GPIO2
7 B COL0 : Data Width Setting when PDN1=0. See Table 16.
INT : Interrupt signal output for Sub-Link when SUBMODE=0
and MSSEL=0. It must be connected with a pull-up resistor to
VDD.
L : Interrupt occurred
H : Steady state
GPIO2 : General Purpose Input/Output when SUBMODE=0 and
MSSEL=1.
When GPIO2 is used as Open-Drain Output, it must be connected
with a pull-up resistor to VDD.
When GPIO2 is used as push pull output or input, no external
component is required.
CLKOUT 26 O Clock Output
D31-D26 12-15,17,18 O Pixel Data Output

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D25/GPIO4 19 B D25 : Pixel Data Output
GPIO4 : General Purpose Input/Output when SUBMODE=0,
MSSEL=1 and RXDEFSEL=0.
When GPIO4 is used as Open-Drain Output, it must be connected
with a pull-up resistor to VDD. When GPIO4 is used as push pull
output or input, no external component is required.
D24/GPIO3 20 B D24 : Pixel Data Output
GPIO3 : General Purpose Input/Output when SUBMODE=0,
MSSEL=1 and RXDEFSEL=0.
When GPIO3 is used as Open-Drain Output, it must be connected
with a pull-up resistor to VDD. When GPIO3 is used as push pull
output or input, no external component is required.
D23-D0 21-24,27-31,33-
39,42-47,52,53
O Pixel Data Output
DE 51 O DE Output
HSYNC 50 O HSYNC Output
VSYNC 48 O VSYNC Output
OE 63 IL Output Enable
0 : LVCMOS Output Disable (Hi-Z) except for HTPDN,
LOCKN when PDN1=0 and except for BETOUT when BET=1
1 : LVCMOS Output Enable
BET 64 IL Field BET entry
0 : Normal Operation
1 : Field BET Operation
RF/BETOUT 6 B RF : Output Clock Triggering edge select. See Figure 18.
0 : Falling Edge
1 : Rising Edge
BETOUT : Field BET Result Output
RXDEFSEL 62 I Internal Register Default Setting Select. See Table 36, Table 37
0 : for THCV231-Q
1 : for THCV235-Q
LFSEL 3 I Low Frequency mode select
0 : Low Frequency mode Disable
1 : Low Frequency mode Enable
Forbid setting 1 when connecting with THCV231-Q.
PDN1 2 IL Sub-Link Power Down
0 : Power Down. Main-Link setting by external pin
1 : Normal Operation. Main-Link Setting by 2-wire serial I/F
PDN0 1 IL Main-Link Power Down
0 : Power Down
1 : Normal Operation
TEST2 5 I Test pin. Must be tied to Ground for normal operation.
TEST1 4 IL Test pin. Must be tied to Ground for normal operation.
CAPOUT 56 PWR Decoupling Capacitor Pin, 1.2V output.
CAPINA 59 PWR Reference Input for Analog Circuit. Must be tied to CAPOUT.
VDD 49,41,32,25,16 PWR 1.7-3.6V Digital Power Supply Pin for LVCMOS I/O
AVDD 40 PWR 1.7-3.6V Analog Power Supply Pin for LDO
EXPGND 65 GND Exposed Pad Ground. Must be tied to the PCB ground plane
through an array of vias.
CI : CML Input buffer , CB : CML Bi-directional buffer
I : LVCMOS Input buffer , IL : Low Speed LVCMOS Input buffer , O: LVCMOS Output buffer
B : LVCMOS Bi-directional buffer , BO : Open-Drain LVCMOS Bi-directional buffer
PWR : Power supply , GND : Ground

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Table 1. Pin Sharing Description (THCV236-Q)
Sub-Link State →2-wire serial
I/F Mode
Sub-Link
Master/Slave →Master
PDN1 1
HTPDN/SUBMODE 0
LOCKN/MSSEL 0
BET 0
RXDEFSEL 0
RF/BETOUT RF
BETOUT(*1)
COL0/INT/GPIO2 INT
COL1/SD0 SD0(SDA)
OUTSEL/SD1 SD1(SCL)
TTLDRV/SD2/AIN0/GPIO1 AIN0
LATEN/SD3/AIN1/GPIO0 AIN1
LATEN(*2)
D24/GPIO3 GPIO3(*3)
D25/GPIO4 GPIO4(*3)
HTPDN/SUBMODE SUBMODE
LOCKN/MSSEL MSSEL
MAINMODE/RCMN RCMN
HFSEL/RCMP RCMP
*1 When Field BET mode (Main-Link or Sub-Link), it functions as BETOUT output.
*2 When Field BET mode (Main-Link or Sub-Link), it functions as LATEN input.
*3 Through GPIO input is default on register setting

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Functional Overview
With High Speed CML SerDes, proprietary encoding scheme and CDR (Clock and Data Recovery) architecture,
the THCV231-Q and THCV236-Q enable transmission of 14bit data through Main-Link by single differential pair
cable with minimal external components. In addition, the THCV231-Q and THCV236-Q have Sub-Link which
enables bi-directional transmission of 2-wire serial interface signals, GPIO signals and also HTPDN/LOCKN
signals for Main-Link through the other 1-pair of CML-Line. It does not need any external frequency reference
such as a crystal oscillator. The THCV231-Q - THCV236-Q system is able to watch peripheral devices and to
control them via 2-wire serial interface or GPIOs. They also can report interrupt events caused by change of GPIO
inputs and internal statuses.
Functional Description
Internal Reference Output/Input Function (CAPOUT, CAPINA, CAPINP)
An internal regulator produces the 1.2V (CAPOUT). This 1.2V linear regulator can’t supply any other external
loads. Bypass CAPOUT to GND with 10uF.
CAPINP (THCV231-Q only) supplies reference voltage for internal PLL, and CAPINA supplies reference
voltage for any internal analog circuit. Bypass CAPINP/CAPINA to GND with 0.1uF to remove high frequency
noise. CAPOUT, CAPINA and CAPINP must be tied together.
Power supply AVDD is supposed to be stabilized with de-coupling capacitor and series noise filter (for example,
ferrite bead).
Figure 1. Connection of CAPOUT, CAPINA, CAPINP and Decoupling Capacitor

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Power Down (PDN1, PDN0, PDN)
PDN1, PDN0 and PDN turn off internal circuitry of Main-Link and Sub-Link separately.
Table 2. Power Down Setting(THCV231-Q)
PDN Operation
0 Both Main-Link and Sub-Link power down
1 Both Main-Link and Sub-Link active
Table 3. Power Down Setting(THCV236-Q)
PDN1 PDN0 Operation
0 0 Both Main-Link and Sub-Link power down
0 1 Only Main-Link is active
1 0 Only Sub-Link is active
1 1 Both Main-Link and Sub-Link active
Pre-emphasis and Drive Select Function (THCV231-Q only)
Pre-emphasis can equalize severe signal degradation caused by long-distance or high-speed transmission. PRE
register selects the strength of pre-emphasis. CMLDRV register controls CML Main-Link output swing level. See
Table 4.
Table 4. Pre-emphasis and Drive Select function table
CMLDRV[1:0]
(register)
PRE
(register)
Condition
Swing Level Pre-emphasis Level
00 0 400mV diff p-p 0dB
1 6dB
01 0 600mV diff p-p 0dB
1 3.5dB
10 * 800mV diff p-p 0dB
11 * Forbidden
Permanent Clock Output (THCV236-Q only)
When there is no input from Main-Link, the THCV236-Q will output internal oscillator clock from CLKOUT
pin. This function is controlled by OUTSEL pin or OUTSEL_ENABLE register and OUTSEL_SETTING register.
See Table 5.
Table 5. Permanent Clock Output function table (PDN1=1)
OUTSEL
_
ENABLE
(register)
OUTSEL
_
SETTING
(register)
Output Clock
Frequency(*1)
0 * -
1
00 80MHz
01 40MHz(default)
10 20MHz
11 10MHz
*1 typical value

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Spread Spectrum Clock Generator (SSCG)
The THCV231-Q serial data output and the THCV236-Q parallel data and clock outputs are modulated by
programmable SSCG. The THCV231-Q and THCV236-Q SSCG are enabled by only SSEN register. The
modulation rate and modulation frequency variation of output spread is controlled through the SSCG control
registers on each device. Do not enable spread spectrum for both the THCV231-Q and THCV236-Q at the same
time.
Table 6. SSCG enable signal
Mode Entry Signal Description
SSEN(register) 0:SSCG Disable
1:SSCG Enable
When customer use the mode and frequency range shown in Table 7, register setting is required according to
Table 8.
Table 7. Main-Link mode and frequency range requiring register setting
Mode Setting Freq.Range[MHz]
(SSCG Enable)
Register
Setting
(*2)
MAINMODE HFSEL COL1 COL0 min max
1 0 0 0 26.6 40 Case1
1 0 0 1 26.6 50 Case1
1 0 1 0 33.3 66.6 Case2
1 1
(*1) (*1) 50 100 Case3
*1 Don’t care
*2 See Table 8
Table 8. SSCG register setting
Step
Register Address(HEX) Register Value(HEX)
Description
Sub-Link
Master side
Sub-Link
Slave side Case1 Case2 Case3
THCV231-Q THCV236-Q
1 0x70 0xF0 0x01 Set 1 to PLL_SET_EN
2 0x76 0xF6 0x02 0x02 0x01 Set PLL_SET0
3 0x78 0xF8 0x3C 0x30 0x20 Set PLL_SET1
4 0x7C 0xFC 0x35 0x34 0x24 Set PLL_SET2
Modulation frequency fmod can be determined by HFSEL and LFSEL settings, input clock frequency and FMOD
register setting (default value 0xD). Refer to following formula.
FMOD
f
fCLKSSCG


128
mod
fCLKSSCG is the frequency listed in Table 9 and Table 10.

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Table 9. fCLKSSCG (THCV231-Q)
HFSEL
(register) fCLKSSCG
0 (1/tTCIP)/2
1 (1/tTCIP)/4
Table 10. fCLKSSCG (THCV236-Q)
HFSEL LFSEL fCLKSSCG
0 0 (1/tRCP)/2
1 0 (1/tRCP)/4
* 1 Forbidden Setting
Up to 0.5 % spread at the 30kHz modulation frequency is stable for most cases. In case of using out of this range,
please verify at the actual system.

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Data Enable
V-by-One® HS mode operation (MAINMODE=0) are shown below. THCV231-Q HSYNC pin input is DE signal.
Table 11 and related note shows requirements for DE. Video HSYNC signal may meet DE input requirement.
HSYNC output of THCV236-Q under THCV231-Q V-by-One® HS mode operation is invalid.
D11-D0
VSYNC
1
DE (HSYNC pin input)
THCV236-QTHCV231-Q
Vi d eo Da ta
CONT
VSYN C
DE=1, D31-D0
DE=0, Low fixed
DE=1, VSYNC=Fixed
DE=0, VSYNC
0
Figure 2. Conceptual Diagram of the Basic Operation of the Chipset in V-by-One®HS mode
HighLow High
Valid Data
Valid Data
Invalid
Invalid
DE
(HSYNC pin inut)
VSYNC
D11-D0
THCV231-Q
Input
Invalid
Valid Data
CLKIN
Low
Valid Data
Invalid Invalid
Valid Data
Low High
Invalid
Vali d Data
(RF=1)
HighLow High
Valid Data
Valid Data
Keep t he last data
of DE=L perio d
DE
(DE pin output)
VSYNC
Valid Data
CLKOUT
Low
Valid Data Vali d Data
Low High
Vali d Data
(RF=1)
Keep the last data
of DE=L period
Keep the last data
of DE=L period
tDEH tDEL
tDEH tDEL
THCV236-Q
Output
tDEINT
(MAINMODE=0)
D11-D0
(MAINMODE=0)
Low fixed Low fixed Low fixed
Figure 3. Data and Synchronizing Signals Transmission Timing Diagram in V-by-One®HS mode
Table 11. DE Requirement
Symbol Paramete
r
Condition Min Typ Max Unit
tDEH DE=1 Duration
MAINMODE=0 and HFSEL=0 2×tTCIP - - ns
MAINMODE=0 and HFSEL=1 4×tTCIP *Note - ns
MAINMODE=1 Don’t care
tDEL DE=0 Duration
MAINMODE=0 and HFSEL=0 2×tTCIP - - ns
MAINMODE=0 and HFSEL=1 4×tTCIP *Note - ns
MAINMODE=1 Don’t care
*Note: In V-by-One® HS Mode (MAINMODE=0) and High Frequency Mode (HFSEL=1), the period between rising edges of DE
(tDEINT), high time of DE (tDEH) should always satisfy following equations.
tDEH = tTCIP*(2m) and tDEINT = tTCIP*(2n), m,n=2,3,4,5,6……

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Hot-Plug Function
HTPDN signal indicates connecting condition between the Transmitter and the Receiver. HTPDN of the
transmitter side is high when the Receiver is not active or not connected. Then the Transmitter can enter into the
power down mode. HTPDN is set to low by the Receiver when the Receiver is active and connects to the
Transmitter, and then the Transmitter must start up and transmit CDR training pattern for link training.
HTPDN is transferred to the Transmitter via Sub-Link line. HOST MPU can confirm HTPDN state by reading
Sub-Link Master register (0x00 bit0 HTPDN).
Lock Detect Function
LOCKN indicates whether the receiver CDR PLL is in the lock state or not. LOCKN at the Transmitter input is
set to High when the Receiver is not active or at the CDR PLL training state. LOCKN is set to low by the Receiver
when CDR lock is done. Then the CDR training mode finishes and the Transmitter shifts to the normal operation.
LOCKN is transferred via Sub-Link line. HOST MPU can confirm LOCKN state by reading Sub-Link Master
register (0x00 bit1 LOCKN).
Figure 4. HTPDN, LOCKN transmission route

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Field BET Operation
In order to help users to check validity of CML serial line (Main-Link and Sub-Link), the THCV231-Q and
THCV236-Q have an operation mode in which they act as a bit error tester (BET). In Main-Link Field BET mode,
the THCV231-Q internally generates a test pattern which is then serialized onto the Main-Link CML line. The
THCV236-Q also has BET function mode. The THCV236-Q receives the data stream and checks bit errors. The
generated data pattern is then 8b/10b encoded, scrambled, and serialized onto the CML channel. As for the
THCV236-Q, the internal test pattern check circuit gets enabled and reports result on a certain pin named BETOUT.
In Sub-Link Field BET mode, Sub-Link Master device internally generates test pattern which is then serialized
onto the Sub-Link CML line. Sub-Link Slave device also has BET function mode. Sub-Link Slave device receives
the data stream and checks bit errors. Note that Sub-Link Slave device must be set this mode prior to Sub-Link
Master device. Pattern check result is output from BETOUT pin of the Sub-Link Slave device. The BETOUT pin
goes LOW whenever bit errors occur, or it stays HIGH when there is no bit error.
In Main-Link Field BET mode, user can select two kinds of check result, latched result or NOT latched result by
setting LATEN pin input. The latched result is reset by setting LATEN=0. In Sub-Link Field BET mode, only
latched result is available. In order to reset the latched result, please once turn off the power and entry Sub-Link
Field BET from power on sequence.
GPIO4 pin (THCV231-Q) and LATEN/SD3/AIN1/GPIO0 pin (THCV236-Q) function as LATEN in Field BET
mode (Main-Link or Sub-Link).
It is not possible to realize Main-Link Field BET and Sub-Link Field BET at the same time.
Table 12. Main-Link Field BET Operation Settings
THCV231-Q/236-Q
Common Setting
THCV236-Q
Setting Condition
PDN0/PDN1/PDN SUBMODE BET BET_SEL LATEN Main-Link Sub-Link Output Latch
Select
1 0
1
(*1)
0
(*2)
0 Field BET
Operation
Normal
Operation
NOT Latched Result
1 Latched Result
*1 THCV231-Q: Register setting (0x53 bit1), THCV236-Q: Pin setting
*2 Register setting (0x53 bit0, Default 0)
Table 13. THCV236-Q Main-Link Field BET Result
BETOUT Output
L Bit Error Occurred
H No Error

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Table 14. Sub-Link Field BET Operation Setting
THCV231-Q/THCV236-Q
Common Setting
THCV231-Q
Setting
THCV236-Q
Setting Condition
BET BET_SEL PDN GPIO3 GPIO4 PDN1 MSSEL LATEN Sub-Link
Output
Latch
Select
1
(*1)
1
(*2) 1
0 -
1
1 1
(*3)
Field BET
Operation
(THCV231-Q→THCV236-Q) Latched
Result
1 1
(*3) 0 -
Field BET
Operation
(THCV236-Q→THCV231-Q)
*1 THCV231-Q: Register setting (0x53 bit1), THCV236-Q: Pin setting. Note that BET pin should be 0 at power on sequence.
*2 Register setting (0x53 bit0, Default 0)
*3 Forbidden 0 setting
Table 15. Sub-Link Slave device Sub-Link Field BET Result
BETOUT Output
L Bit Error Occurred
H No Error
Figure 5. Main-Link Field BET Configuration
THCV231-Q THCV236-Q
Test Pattern
Checker
Test Pattern
Generator RF/BETOUT
Test Point
for
Field BET
OSC
BET=1
(Register)
BET_SEL=1
(Register)
LATEN/SD3/AIN1/GPIO0 =1
BET=1
(Pin)
BET_SEL=1
(Register)
Sub-Link
Figure 6. Sub-Link Field BET Configuration

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Data Width and Frequency Range Select Function
The THCV231-Q and THCV236-Q support a variety of data width and frequency range. Frequency range is
different depending on the mode setting SSCG enable and disable setting. Refer to Table 16 for details.
Table 16. Main-Link Operation Mode Select
Mode Setting
Freq.Range
[MHz] Main-Link
CML
Bit Rate
Data Width Comment
SSCG
Disable
SSCG
Enable(*1)
MAINMODE HFSEL COL1 COL0 min max min max Data Sync
0 * 1 * - - - - - - Forbidden
0 0 0 0 15 100 26.6 100 x40 12 2
0 0 0 1 20
133.3 33.3 133.3 x30 12 2
0 1 0 0 - - - - - - - Forbidden
0 1 0 1
50 70 50 70 x20 12 2 (*2)
70 160 70 160 -
1 0 0 0 12
30 26.6 60 x50 14 -
1 0 0 1 15 40 26.6 75 x40 14 -
1 0 1 0 20
75 33.3 100 x30 14 -
1 0 1 1 - - - - - - Forbidden
1 1 0 0 - - - - - - Forbidden
1 1 0 1
50 70 50 70 x20 14 (*2)
70 160 70 160 -
1 1 1 0
50 70 50 70 x15 10 (*2)
70 160 70 160 -
1(*3) 1 1 1
50 70 50 70 x15 8 2 (*2) (*3)
70 160 70 160 (*3)
*1 Note that register setting is required depending on the mode setting and used frequency range. See Table 7.
*2 Register setting is required. See Table 17.
*3 While Register MAINMODE setting = 1, however, behavior of this exceptional setting is V-by-One® HS Mode whose meaning is MAINMODE = 0.
Table 17. Register setting (HFSEL=1 and Frequency range is from 50MHz to 70MHz)
Step
Register Address(HEX) Register Value(HEX)
Description
Sub-Link
Master side
Sub-Link
Slave side THCV231-Q THCV236-Q
1 0x70 0xF0 0x01 Set 1 to PLL_SET_EN
2 0x76 0xF6 0x02 0x01 Set PLL_SET0
3 0x78 0xF8 0x20 Set PLL_SET1
4 0x7C 0xFC 0x24 Set PLL_SET2
Data Mapping
Table 18. Data Mapping
MAINMODE 0 0 0 1 1 1 1 1 1
HFSEL 0 0 1 0 0 0 1 1 1
COL1 0 0 0 0 0 1 0 1 1
COL0 0 1 1 0 1 0 1 0 1
D0 D0/RAW4 D0/RAW4 D0/RAW4/YC0 D0 D0 D0 D0/RAW4 D0/YC0 D0/RAW0/YC0
D1 D1/RAW5 D1/RAW5 D1/RAW5/YC1 D1 D1 D1 D1/RAW5 D1/YC1 D1/RAW1/YC1
D2 D2/RAW6 D2/RAW6 D2/RAW6/YC2 D2 D2 D2 D2/RAW6 D2/YC2 D2/RAW2/YC2
D3 D3/RAW7 D3/RAW7 D3/RAW7/YC3 D3 D3 D3 D3/RAW7 D3/YC3 D3/RAW3/YC3
D4 D4/RAW8 D4/RAW8 D4/RAW8/YC4 D4 D4 D4 D4/RAW8 D4/YC4 D4/RAW4/YC4
D5 D5/RAW9 D5/RAW9 D5/RAW9/YC5 D5 D5 D5 D5/RAW9 D5/YC5 D5/RAW5/YC5
D6 D6/RAW10 D6/RAW10 D6/RAW10/YC6 D6 D6 D6 D6/RAW10 D6/YC6 D6/RAW6/YC6
D7 D7/RAW11 D7/RAW11 D7/RAW11/YC7 D7 D7 D7 D7/RAW11 D7/YC7 D7/RAW7/YC7
D8 D8/RAW0 D8/RAW0 D8/RAW0 D8 D8 D8 D8/RAW0 - -
D9 D9/RAW1 D9/RAW1 D9/RAW1 D9 D9 D9 D9/RAW1 - -
D10 D10/RAW2 D10/RAW2 D10/RAW2 D10 D10 D10 D10/RAW2 - -
D11 D11/RAW3 D11/RAW3 D11/RAW3 D11 D11 D11 D11/RAW3 - -
HSYNC DE*2 (HSYNC*3) DE*2 (HSYNC*3) DE*2 (HSYNC*3) HSYNC*1 HSYNC*1 HSYNC*1 HSYNC*1 HSYNC*1 DE*2 (HSYNC*3)
V
SYNC VSYNC VSYNC VSYNC VSYNC*1 VSYNC*1 VSYNC*1 VSYNC*1 VSYNC*1 VSYNC*1
*1 Any signal as well as sync signal can be transmitted when MAINMODE=1.
*2 V-by-One®HS mode operation requires Data Enable (DE) signal rule. Please refer to the related section.
*3 HSYNC signal can be assigned to Data Enable input when V-by-One® HS mode requirements are met.

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Sub-Link Mode Setting
2-wire serial I/F Mode
2-wire serial I/F Mode enables register access, using GPIO (General Purpose Input/Output) pin and interrupt
function. Sub-Link Master device has 2-wire serial slave block and can be connected to HOST MPU, Sub-Link
Slave device has 2-wire serial master block and can be connected to remote side 2-wire serial slave devices.
HOST MPU can access register of Sub-Link Master device, Sub-Link Slave device and remote side 2-wire serial
slave devices.
2-wire serial I/F Device ID setting
AIN1 and AIN0 pins determine Device ID setting of the THCV236-Q. Only Sub-Link Master device has AIN1
and AIN0 pin. AIN1 and AIN0 choose one of 4 addresses which give an identification address to the THCV236-
Q under 2-wire serial interface bus topology.
Table 19. 2-wire serial I/F Device ID select (Sub-Link Master device Only)
AIN1
A
IN0 Device ID
0 0 0x0B
0 1 0x34
1 0 0x77
1 1 0x65
2-wire serial I/F Clock Stretching
In principle, when Sub-Link bridges 2-wire serial interface communication from Sub-Link Master to Sub-Link
Slave or remote side 2-wire serial slave devices, time lag occurs between HOST MPU side 2-wire serial access
and Sub-Link Slave internal bus access or remote side 2-wire serial access.
2WIRE_MODE (Sub-Link Master side register, 0x0F bit1-0) selects whether 2-wire serial slave of Sub-Link
Master perform clock stretching or not.
When 2WIRE_MODE = 00, Sub-Link Master device wait HOST MPU until Sub-Link Slave register access or
remote side 2-wire serial slave register access is completed by clock stretching.
When 2WIRE_MODE = 01, Sub-Link Master device informs HOST MPU that Sub-Link Slave register access
or remote side 2-wire serial register access has been completed by interruption (INT pin) without clock stretching.

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Figure 7. 2WIRE_MODE Operation