Wiznet W7500 User manual

© Copyright 2015 WIZnet Co., Ltd. All rights reserved.
W7500 Reference Manual
Version 1.0.0
http://www.wiznet.co.kr

W7500 Datasheet Version1.0.0 2 / 512
Table of Contents
1Documentation conventions ........................................................................ 29
List of abbreviations....................................................................... 291.1
Glossary ...................................................................................... 291.2
Register Bit Conventions .................................................................. 311.3
2System and memory overview ..................................................................... 32
2.1 System architecture ....................................................................... 32
2.2 Memory organization ...................................................................... 33
2.2.1 Introduction ......................................................................... 33
2.2.2 Memory map......................................................................... 34
3System configuration controller (SYSCFG)....................................................... 35
3.1 Introduction ................................................................................. 35
3.2 Registers (Base address : 0x4001_F000)................................................ 35
3.2.1 REMAP register ...................................................................... 35
3.2.2 RESETOP register ................................................................... 35
3.2.3 RSTINFO register.................................................................... 36
4Interrupt and events ................................................................................. 36
4.1 Introduction ................................................................................. 36
4.2 Interrupt assignments ..................................................................... 37
4.3 Event ......................................................................................... 38
5Power supply ........................................................................................... 38
5.1 Introduction ................................................................................. 38
5.2 Voltage regulator........................................................................... 38
5.3 Power supply supervisor .................................................................. 38
5.4 Low-power modes.......................................................................... 39
5.4.1 Sleep mode .......................................................................... 39
5.4.2 Peripheral clock gating ............................................................ 39
6System tick timer ..................................................................................... 40
6.1 Introduction ................................................................................. 40
6.2 Features ..................................................................................... 40
6.3 Functional description .................................................................... 40
6.4 Registers (Base : 0xE000_E000).......................................................... 41
6.4.1 System Timer control and status register (SYST_CSR) ....................... 41
6.4.2 SysTick Reload Value Register (SYST_RVR) ..................................... 41
6.4.3 SysTick Current Value Register (SYST_CVR) .................................... 42
6.4.4 SysTick Calibration Value Register (SYST_CALIB) ............................. 42
7TCPIPCore Offload Engine (TOE) ................................................................... 43
Introduction ................................................................................. 437.1

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Features ..................................................................................... 437.2
Functional description .................................................................... 437.3
TOE Memory map........................................................................... 447.4
Common register map ............................................................. 467.4.1
Socket register map................................................................ 467.4.2
Memory ............................................................................... 477.4.3
Common register (Base : 0x4100_0000)................................................ 497.5
VERSIONR (TOE Version Register) ................................................ 497.5.1
TCKCNTR (Ticker Counter Register) ............................................. 497.5.2
IR (Interrupt Register) ............................................................. 497.5.3
IMR (Interrupt Mask Register) .................................................... 507.5.4
IRCR (Interrupt Clear Register)................................................... 517.5.5
SIR (Socket Interrupt Register)................................................... 517.5.6
SIMR (Socket Interrupt Mask Register) .......................................... 527.5.7
MD (Mode Register)................................................................. 527.5.8
PTIMER (PPP Link Control Protocol Request Timer Register)................ 537.5.9
PMAGICR (PPP Link Control Protocol Magic number Register) .............. 547.5.10
PHAR (Destination Hardware Address Register in PPPoE) ................... 547.5.11
PSIDR (Session ID Register in PPPoE) ............................................ 557.5.12
PMRUR (Maximum Receive Unit Register in PPPoE)........................... 557.5.13
SHAR (Source Hardware Address Register) ..................................... 567.5.14
GAR (Gateway Address) ........................................................... 577.5.15
SUBR ( Subnet Mask Register) .................................................... 577.5.16
SIPR (Source IP address Register) ................................................ 587.5.17
NCONFLR ( Network Configuration Lock Register) ............................ 587.5.18
RTR (Retry Time Register)......................................................... 597.5.19
RCR (Retry Counter Register)..................................................... 597.5.20
UIPR (Unreachable IP address Register) ........................................ 617.5.21
UPORTR (Unreachable Port Register) ........................................... 627.5.22
Socket register (Base : 0x4101_0000 + 0x0004_000 x n)[n=0,…7, where n is 7.6
socket number] ......................................................................................... 62
Sn_MR (Socket n Mode Register) ................................................. 627.6.1
Sn_CR (Socket n Command Register)............................................ 647.6.2
Sn_IR (Socket n Interrupt Register) ............................................. 677.6.3
Sn_IMR (Socket n Interrupt Mask Register)..................................... 677.6.4
Sn_ICR (Socket n Interrupt Clear Register) .................................... 687.6.5
Sn_SR (Socket n Status Register) ................................................ 697.6.6
Sn_PNR (Socket n Protocol Number Register) ................................. 717.6.7
Sn_TOSR (Socket n IP Type of Service Register) ............................... 717.6.8

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Sn_TTLR (Socket n TTL Register) ................................................ 727.6.9
Sn_FRAGR (Socket n Fragment offset Register) ............................... 727.6.10
Sn_MSSR (Socket n Maximum Segment Register).............................. 737.6.11
Sn_PORTR (Socket n Source Port Register)..................................... 737.6.12
Sn_DHAR (Socket n Destination Hardware address Register) ............... 747.6.13
Sn_DPORTR (Socket n Destination Port Number Register)................... 757.6.14
Sn_DIPR (Socket n Destination IP address Register) .......................... 757.6.15
Sn_KATMR (Socket n Keep Alive Timer Register) .............................. 767.6.16
Sn_RTR (Socket n Retry Time Register) ....................................... 777.6.17
Sn_RCR (Socket n Retry Counter Register) ..................................... 777.6.18
Sn_TXBUF_SIZE (Socket n TX Buffer Size Register) ........................... 787.6.19
Sn_TX_FSR (Socket n TX Free Size Register)................................... 797.6.20
Sn_TX_RD (Socket n TX Read Pointer Register) ............................... 807.6.21
Sn_TX_WR (Socket n TX Write Pointer Register) .............................. 807.6.22
Sn_RXBUF_SIZE (Socket n RX Buffer Size Register) ........................... 817.6.23
Sn_RX_RSR (Socket n RX Received Size Register) ............................. 827.6.24
Sn_RX_RD (Socket n RX Read Pointer Register) ............................... 827.6.25
Sn_RX_WR (Socket n RX Write Pointer Register) .............................. 837.6.26
8Booting Sequence ..................................................................................... 84
9Embedded Flash memory............................................................................85
Flash main features........................................................................ 859.1
Flash memory functional description................................................... 859.2
Flash memory organization ....................................................... 859.2.1
Read operations..................................................................... 879.2.2
Flash erase operations............................................................. 889.2.3
Flash program operation .......................................................... 909.2.4
Memory protection......................................................................... 919.3
Read protection..................................................................... 919.3.1
Write protection .................................................................... 919.3.2
10Clock Reset generator (CRG)........................................................................92
10.1 Introduction ................................................................................. 92
10.2 Features ..................................................................................... 92
10.2.1 Reset .................................................................................. 92
10.2.2 Clock.................................................................................. 92
10.3 Functional description .................................................................... 93
10.3.1 External Oscillator Clock .......................................................... 93
10.3.2 RC oscillator clock.................................................................. 94
10.3.3 PLL .................................................................................... 94
10.3.4 Generated clock .................................................................... 94

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10.4 Registers (Base address : 0x4100_1000)................................................ 95
10.4.1 OSC power down register (OSC_PDR) ........................................... 95
10.4.2 PLL power down register (PLL_PDR) ............................................ 95
10.4.3 PLL frequency calculating register (PLL_FCR)................................. 95
10.4.4 PLL output enable register (PLL_OER) .......................................... 96
10.4.5 PLL bypass register (PLL_BPR) ................................................... 96
10.4.6 PLL input clock source select register (PLL_IFSR) ............................ 97
10.4.7 FCLK source select register (FCLK_SSR) ........................................ 97
10.4.8 FCLK prescale value select register (FCLK_PVSR) ............................ 98
10.4.9 SSPCLK source select register (SSPCLK_SSR) .................................. 98
10.4.10 SSPCLK prescale value select register (SSPCLK_PVSR) ....................... 99
10.4.11 ADCCLK source select register (ADCCLK_SSR) ................................. 99
10.4.12 ADCCLK prescale value select register (ADCCLK_PVSR) ....................100
10.4.13 TIMER0CLK source select register (TIMER0CLK_SSR) ........................100
10.4.14 TIMER0CLK prescale value select register (TIMER0CLK_PVSR) ............100
10.4.15 TIMER1CLK source select register (TIMER1CLK_SSR) ........................101
10.4.16 TIMER1CLK prescale value select register (TIMER1CLK_PVSR) ............101
10.4.17 PWM0CLK source select register (PWM0CLK_SSR) ...........................102
10.4.18 PWM0CLK prescale value select register (PWM0CLK_PVSR)................103
10.4.19 PWM1CLK source select register (PWM1CLK_SSR) ...........................103
10.4.20 PWM1CLK prescale value select register (PWM1CLK_PVSR)................104
10.4.21 PWM2CLK source select register (PWM2CLK_SSR) ...........................104
10.4.22 PWM2CLK prescale value select register (PWM2CLK_PVSR)................105
10.4.23 PWM3CLK source select register (PWM3CLK_SSR) ...........................105
10.4.24 PWM3CLK prescale value select register (PWM3CLK_PVSR)................106
10.4.25 PWM4CLK source select register (PWM4CLK_SSR) ...........................106
10.4.26 PWM4CLK prescale value select register (PWM4CLK_PVSR)................107
10.4.27 PWM5CLK source select register (PWM5CLK_SSR) ...........................107
10.4.28 PWM5CLK prescale value select register (PWM5CLK_PVSR)................108
10.4.29 PWM6CLK source select register (PWM6CLK_SSR) ...........................108
10.4.30 PWM6CLK prescale value select register (PWM6CLK_PVSR)................109
10.4.31 PWM7CLK source select register (PWM7CLK_SSR) ...........................109
10.4.32 PWM7CLK prescale value select register (PWM7CLK_PVSR)................110
10.4.33 WDOGCLK High Speed source select register (WDOGCLK_HS_SSR) .......110
10.4.34 WDOGCLK High Speed prescale value select register (WDOGCLK_HS_PVSR)
111
10.4.35 UARTCLK source select register (UARTCLK_SSR) .............................111
10.4.36 UARTCLK prescale value select register (UARTCLK_PVSR) .................112
10.4.37 MIICLK enable control register (MIICLK_ECR).................................112

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10.4.38 Monitoring Clock source select register (MONCLK_SSR) ....................113
10.5 Register map ...............................................................................115
11Random number generator (RNG) ............................................................... 117
Introduction ................................................................................11711.1
Features ....................................................................................11711.2
Functional description ...................................................................11711.3
Operation RNG .....................................................................11811.3.1
Registers (Base address : 0x4000_7000)...............................................11911.4
RNG run register (RNG_RUN) ....................................................11911.4.1
RNG SEED register (RNG_SEED) .................................................11911.4.2
RNG clock select register (RNG_CLKSEL)......................................11911.4.3
RNG manual mode select register (RNG_MODE) .............................12011.4.4
RNG random number value register (RNG_RN) ...............................12011.4.5
RNG polynomial register (RNG_POLY)..........................................12111.4.6
Register map ...............................................................................12211.5
12Alternate Function Controller (AFC) ............................................................ 123
Introduction ................................................................................12312.1
Features ....................................................................................12312.2
Functional description ...................................................................12312.3
Registers (Base address : 0x4100_2000)...............................................12512.4
PA_00 pad alternate function select register (PA_00_AFR) ................12512.4.1
PA_01 pad alternate function select register (PA_01_AFR) ................12512.4.2
PA_02 pad alternate function select register (PA_02_AFR) ................12612.4.3
PA_03 pad alternate function select register (PA_03_AFR) ................12612.4.4
PA_04 pad alternate function select register (PA_04_AFR) ................12712.4.5
PA_05 pad alternate function select register (PA_05_AFR) ................12712.4.6
PA_06 pad alternate function select register (PA_06_AFR) ................12812.4.7
PA_07 pad alternate function select register (PA_07_AFR) ................12812.4.8
PA_08 pad alternate function select register (PA_08_AFR) ................12912.4.9
PA_09 pad alternate function select register (PA_09_AFR) ................12912.4.10
PA_10 pad alternate function select register (PA_10_AFR) ................13012.4.11
PA_11 pad alternate function select register (PA_11_AFR) ................13012.4.12
PA_12 pad alternate function select register (PA_12_AFR) ................13112.4.13
PA_13 pad alternate function select register (PA_13_AFR) ................13112.4.14
PA_14 pad alternate function select register (PA_14_AFR) ................13212.4.15
PA_15 pad alternate function select register (PA_15_AFR) ................13212.4.16
PB_00 pad alternate function select register (PB_00_AFR) ................13312.4.17
PB_01 pad alternate function select register (PB_01_AFR) ................13312.4.18
PB_02 pad alternate function select register (PB_02_AFR) ................13412.4.19

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PB_03 pad alternate function select register (PB_03_AFR) ................13412.4.20
PB_04 pad alternate function select register (PB_04_AFR) ................13512.4.21
PB_05 pad alternate function select register (PB_05_AFR) ................13512.4.22
PB_06 pad alternate function select register (PB_06_AFR) ................13612.4.23
PB_07 pad alternate function select register (PB_07_AFR) ................13612.4.24
PB_08 pad alternate function select register (PB_08_AFR) ................13712.4.25
PB_09 pad alternate function select register (PB_09_AFR) ................13712.4.26
PB_10 pad alternate function select register (PB_10_AFR) ................13812.4.27
PB_11 pad alternate function select register (PB_11_AFR) ................13812.4.28
PB_12 pad alternate function select register (PB_12_AFR) ................13912.4.29
PB_13 pad alternate function select register (PB_13_AFR) ................13912.4.30
PB_14 pad alternate function select register (PB_14_AFR) ................14012.4.31
PB_15 pad alternate function select register (PB_15_AFR) ................14012.4.32
PC_00 pad alternate function select register (PC_00_AFR)................14112.4.33
PC_01 pad alternate function select register (PC_01_AFR)................14112.4.34
PC_02 pad alternate function select register (PC_02_AFR)................14212.4.35
PC_03 pad alternate function select register (PC_03_AFR)................14212.4.36
PC_04 pad alternate function select register (PC_04_AFR)................14312.4.37
PC_05 pad alternate function select register (PC_05_AFR)................14312.4.38
PC_06 pad alternate function select register (PC_06_AFR)................14412.4.39
PC_07 pad alternate function select register (PC_07_AFR)................14412.4.40
PC_08 pad alternate function select register (PC_08_AFR)................14512.4.41
PC_09 pad alternate function select register (PC_09_AFR)................14512.4.42
PC_10 pad alternate function select register (PC_10_AFR)................14612.4.43
PC_11 pad alternate function select register (PC_11_AFR)................14612.4.44
PC_12 pad alternate function select register (PC_12_AFR)................14712.4.45
PC_13 pad alternate function select register (PC_13_AFR)................14712.4.46
PC_14 pad alternate function select register (PC_14_AFR)................14812.4.47
PC_15 pad alternate function select register (PC_15_AFR)................14812.4.48
PD_00 pad alternate function select register (PD_00_AFR)................14912.4.49
PD_01 pad alternate function select register (PD_01_AFR)................14912.4.50
PD_02 pad alternate function select register (PD_02_AFR)................15012.4.51
PD_03 pad alternate function select register (PD_03_AFR)................15012.4.52
PD_04 pad alternate function select register (PD_04_AFR)................15112.4.53
Register map ...............................................................................15212.5
13External Interrupt (EXTI) .......................................................................... 155
Introduction ................................................................................15513.1
Features ....................................................................................15513.2
Functional description ...................................................................15513.3

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Registers (Base address : 0x4100_2000)...............................................15713.4
PA_00 external interrupt enable register (PA_00_EXTINT) .................15713.4.1
PA_01 external interrupt enable register (PA_01_EXTINT) .................15713.4.2
PA_02 external interrupt enable register (PA_02_EXTINT) .................15813.4.3
PA_03 external interrupt enable register (PA_03_EXTINT) .................15813.4.4
PA_04 external interrupt enable register (PA_04_EXTINT) .................15913.4.5
PA_05 external interrupt enable register (PA_05_EXTINT) .................15913.4.6
PA_06 external interrupt enable register (PA_06_EXTINT) .................16013.4.7
PA_07 external interrupt enable register (PA_07_EXTINT) .................16013.4.8
PA_08 external interrupt enable register (PA_08_EXTINT) .................16113.4.9
PA_09 external interrupt enable register (PA_09_EXTINT) .................16213.4.10
PA_10 external interrupt enable register (PA_10_EXTINT) .................16213.4.11
PA_11 external interrupt enable register (PA_11_EXTINT) .................16313.4.12
PA_12 external interrupt enable register (PA_12_EXTINT) .................16313.4.13
PA_13 external interrupt enable register (PA_13_EXTINT) .................16413.4.14
PA_14 external interrupt enable register (PA_14_EXTINT) .................16413.4.15
PA_15 external interrupt enable register (PA_15_EXTINT) .................16513.4.16
PB_00 external interrupt enable register (PB_00_EXTINT) ................16513.4.17
PB_01 external interrupt enable register (PB_01_EXTINT) ................16613.4.18
PB_02 external interrupt enable register (PB_02_EXTINT) ................16613.4.19
PB_03 external interrupt enable register (PB_03_EXTINT) ................16713.4.20
PB_04 external interrupt enable register (PB_04_EXTINT) ................16813.4.21
PB_05 external interrupt enable register (PB_05_EXTINT) ................16813.4.22
PB_06 external interrupt enable register (PB_06_EXTINT) ................16913.4.23
PB_07 external interrupt enable register (PB_07_EXTINT) ................16913.4.24
PB_08 external interrupt enable register (PB_08_EXTINT) ................17013.4.25
PB_09 external interrupt enable register (PB_09_EXTINT) ................17013.4.26
PB_10 external interrupt enable register (PB_10_EXTINT) ................17113.4.27
PB_11 external interrupt enable register (PB_11_EXTINT) ................17113.4.28
PB_12 external interrupt enable register (PB_12_EXTINT) ................17213.4.29
PB_13 external interrupt enable register (PB_13_EXTINT) ................17213.4.30
PB_14 external interrupt enable register (PB_14_EXTINT) ................17313.4.31
PB_15 external interrupt enable register (PB_15_EXTINT) ................17413.4.32
PC_00 external interrupt enable register (PC_00_EXTINT) ................17413.4.33
PC_01 external interrupt enable register (PC_01_EXTINT) ................17513.4.34
PC_02 external interrupt enable register (PC_02_EXTINT) ................17513.4.35
PC_03 external interrupt enable register (PC_03_EXTINT) ................17613.4.36
PC_04 external interrupt enable register (PC_04_EXTINT) ................17613.4.37
PC_05 external interrupt enable register (PC_05_EXTINT) ................17713.4.38

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PC_06 external interrupt enable register (PC_06_EXTINT) ................17713.4.39
PC_07 external interrupt enable register (PC_07_EXTINT) ................17813.4.40
PC_08 external interrupt enable register (PC_08_EXTINT) ................17813.4.41
PC_09 external interrupt enable register (PC_09_EXTINT) ................17913.4.42
PC_10 external interrupt enable register (PC_10_EXTINT) ................18013.4.43
PC_11 external interrupt enable register (PC_11_EXTINT) ................18013.4.44
PC_12 external interrupt enable register (PC_12_EXTINT) ................18113.4.45
PC_13 external interrupt enable register (PC_13_EXTINT) ................18113.4.46
PC_14 external interrupt enable register (PC_14_EXTINT) ................18213.4.47
PC_15 external interrupt enable register (PC_15_EXTINT) ................18213.4.48
PD_00 external interrupt enable register (PD_00_EXTINT) ................18313.4.49
PD_01 external interrupt enable register (PD_01_EXTINT) ................18313.4.50
PD_02 external interrupt enable register (PD_02_EXTINT) ................18413.4.51
PD_03 external interrupt enable register (PD_03_EXTINT) ................18413.4.52
PD_04 external interrupt enable register (PD_04_EXTINT) ................18513.4.53
Register map ...............................................................................18613.5
14Pad Controller (PADCON) .......................................................................... 189
Introduction ................................................................................18914.1
Features ....................................................................................18914.2
Functional description ...................................................................18914.3
14.4 Registers (Base address : 0x4100_3000)...............................................190
14.4.1 PA_00 pad control register.......................................................190
14.4.2 PA_01 pad control register.......................................................191
14.4.3 PA_02 pad control register.......................................................192
14.4.4 PA_03 pad control register.......................................................192
14.4.5 PA_04 pad control register.......................................................193
14.4.6 PA_05 pad control register.......................................................194
14.4.7 PA_06 pad control register.......................................................194
14.4.8 PA_07 pad control register.......................................................195
14.4.9 PA_08 pad control register.......................................................196
14.4.10 PA_09 pad control register.......................................................196
14.4.11 PA_10 pad control register.......................................................197
14.4.12 PA_11 pad control register.......................................................198
14.4.13 PA_12 pad control register.......................................................199
14.4.14 PA_13 pad control register.......................................................199
14.4.15 PA_14 pad control register.......................................................200
14.4.16 PA_15 pad control register.......................................................201
14.4.17 PB_00 pad control register.......................................................201
14.4.18 PB_01 pad control register.......................................................202

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14.4.19 PB_02 pad control register.......................................................203
14.4.20 PB_03 pad control register.......................................................203
14.4.21 PB_04 pad control register.......................................................204
14.4.22 PB_05 pad control register.......................................................205
14.4.23 PB_06 pad control register.......................................................205
14.4.24 PB_07 pad control register.......................................................206
14.4.25 PB_08 pad control register.......................................................207
14.4.26 PB_09 pad control register.......................................................208
14.4.27 PB_10 pad control register.......................................................208
14.4.28 PB_11 pad control register.......................................................209
14.4.29 PB_12 pad control register.......................................................210
14.4.30 PB_13 pad control register.......................................................210
14.4.31 PB_14 pad control register.......................................................211
14.4.32 PB_15 pad control register.......................................................212
14.4.33 PC_00 pad control register ......................................................212
14.4.34 PC_01 pad control register ......................................................213
14.4.35 PC_02 pad control register ......................................................214
14.4.36 PC_03 pad control register ......................................................214
14.4.37 PC_04 pad control register ......................................................215
14.4.38 PC_05 pad control register ......................................................216
14.4.39 PC_06 pad control register ......................................................216
14.4.40 PC_07 pad control register ......................................................217
14.4.41 PC_08 pad control register ......................................................218
14.4.42 PC_09 pad control register ......................................................219
14.4.43 PC_10 pad control register ......................................................219
14.4.44 PC_11 pad control register ......................................................220
14.4.45 PC_12 pad control register ......................................................221
14.4.46 PC_13 pad control register ......................................................221
14.4.47 PC_14 pad control register ......................................................222
14.4.48 PC_15 pad control register ......................................................223
14.4.49 PD_00 pad control register ......................................................223
14.4.50 PD_01 pad control register ......................................................224
14.4.51 PD_02 pad control register ......................................................225
14.4.52 PD_03 pad control register ......................................................225
14.4.53 PD_04 pad control register ......................................................226
Register map ...............................................................................22814.5
15General-purpose I/Os(GPIO)....................................................................... 232
Introduction ................................................................................23215.1
Features ....................................................................................23215.2

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Functional description ...................................................................23215.3
Masked access......................................................................23315.3.1
GPIOA Registers(Address Base: 0x4200_0000)........................................23515.4
GPIOA Data Register(GPIOA_DATA) .............................................23515.4.1
GPIOA Output Latch Register(GPIOA_DATAOUT) .............................23515.4.2
GPIOA Enable Set Register(GPIOA_OUTENSET) ...............................23515.4.3
GPIOA Enable Clear Register(GPIOA_OUTENCLR) ............................23615.4.4
GPIOA Interrupt Enable Set Register(GPIOA_ INTENSET) ...................23615.4.5
GPIOA Interrupt Enable Clear Register(GPIOA_ INTENCLR) ................23715.4.6
GPIOA Interrupt Type Set Register(GPIOA_ INTTYPESET) ...................23715.4.7
GPIOA Interrupt Type Clear Register(GPIOA_ INTTYPECLR) ................23815.4.8
GPIOA Interrupt Polarity Set Register(GPIOA_ INTPOLSET) ................23815.4.9
GPIOA Interrupt Polarity Clear Register(GPIOA_ INTPOLCLR)..............23915.4.10
GPIOA Interrupt Status/Interrupt Clear Register(GPIOA_ INTSTATUS/15.4.11
INTCLEAR) 239
GPIOA Lower Byte Masked Access Register(GPIOA_ LB_MASKED) .........24015.4.12
GPIOA Upper Byte Masked Access Register(GPIOA_ UB_MASKED) .........24015.4.13
Register map ...............................................................................24215.5
GPIOB Registers(Address Base: 0x4300_0000)........................................24315.6
GPIOB Data Register(GPIOB_DATA) .............................................24315.6.1
GPIOB Output Latch Register(GPIOB_DATAOUT) .............................24315.6.2
GPIOB Enable Set Register(GPIOB_OUTENSET) ...............................24315.6.3
GPIOB Enable Clear Register(GPIOB_OUTENCLR) ............................24415.6.4
GPIOB Interrupt Enable Set Register(GPIOB_ INTENSET) ...................24415.6.5
GPIOB Interrupt Enable Clear Register(GPIOB_ INTENCLR) ................24515.6.6
GPIOB Interrupt Type Set Register(GPIOB_ INTTYPESET) ...................24515.6.7
GPIOB Interrupt Type Clear Register(GPIOB_ INTTYPECLR) ................24615.6.8
GPIOB Interrupt Polarity Set Register(GPIOB_ INTPOLSET) ................24615.6.9
GPIOB Interrupt Polarity Clear Register(GPIOB_ INTPOLCLR)..............24715.6.10
GPIOB Interrupt Status/Interrupt Clear Register(GPIOB_ INTSTATUS/15.6.11
INTCLEAR) 248
GPIOB Lower Byte Masked Access Register(GPIOB_ LB_MASKED) .........24815.6.12
GPIOB Upper Byte Masked Access Register(GPIOB_ UB_MASKED) .........24815.6.13
Register map ...............................................................................25015.7
GPIOC Registers(Address Base: 0x4400_0000)........................................25115.8
GPIOC Data Register(GPIOC_DATA) .............................................25115.8.1
GPIOC Output Latch Register(GPIOC_DATAOUT) .............................25115.8.2
GPIOC Enable Set Register(GPIOC_OUTENSET)...............................25115.8.3
GPIOC Enable Clear Register(GPIOC_OUTENCLR) ............................25215.8.4

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GPIOC Interrupt Enable Set Register(GPIOC_ INTENSET) ...................25215.8.5
GPIOC Interrupt Enable Clear Register(GPIOC_ INTENCLR) ................25315.8.6
GPIOC Interrupt Type Set Register(GPIOC_ INTTYPESET)...................25315.8.7
GPIOC Interrupt Type Clear Register(GPIOC_ INTTYPECLR) ................25415.8.8
GPIOC Interrupt Polarity Set Register(GPIOC_ INTPOLSET) ................25415.8.9
GPIOC Interrupt Polarity Clear Register(GPIOC_ INTPOLCLR) .............25515.8.10
GPIOC Interrupt Status/Interrupt Clear Register(GPIOC_ INTSTATUS/15.8.11
INTCLEAR) 256
GPIOC Lower Byte Masked Access Register(GPIOC_ LB_MASKED) .........25615.8.12
GPIOC Upper Byte Masked Access Register(GPIOC_ UB_MASKED) .........25715.8.13
Register map ...............................................................................25815.9
GPIOD Registers(Address Base: 0x4500_0000) .......................................25915.10
GPIOD Data Register(GPIOD_DATA) .............................................25915.10.1
GPIOD Output Latch Register(GPIOD_DATAOUT) .............................25915.10.2
GPIOD Enable Set Register(GPIOD_OUTENSET)...............................25915.10.3
GPIOD Enable Clear Register(GPIOD_OUTENCLR) ............................26015.10.4
GPIOD Interrupt Enable Set Register(GPIOD_ INTENSET) ...................26015.10.5
GPIOD Interrupt Enable Clear Register(GPIOD_ INTENCLR) ................26115.10.6
GPIOD Interrupt Type Set Register(GPIOD_ INTTYPESET)...................26115.10.7
GPIOD Interrupt Type Clear Register(GPIOD_ INTTYPECLR) ................26215.10.8
GPIOD Interrupt Polarity Set Register(GPIOD_ INTPOLSET) ................26215.10.9
GPIOD Interrupt Polarity Clear Register(GPIOD_ INTPOLCLR) .............26315.10.10
GPIOD Interrupt Status/Interrupt Clear Register(GPIOD_ INTSTATUS/15.10.11
INTCLEAR) 264
GPIOD Lower Byte Masked Access Register(GPIOD_ LB_MASKED) .........26415.10.12
GPIOD Upper Byte Masked Access Register(GPIOD_ UB_MASKED) .........26515.10.13
Register map ...............................................................................26615.11
16Direct memory access controller (DMA)........................................................ 267
Introduction ................................................................................26716.1
Features ....................................................................................26716.2
Functional description ...................................................................26716.3
DMA request mapping .............................................................26816.3.1
DMA arbitration ....................................................................26816.3.2
DMA cycle types....................................................................26816.3.3
Registers (Base address : 0x4100_4000)...............................................27216.4
DMA status register (DMA_STATUS) .............................................27216.4.1
DMA configuration register (DMA_CFG) ........................................27216.4.2
DMA control data base pointer register (DMA_CTRL_BASE_PTR) ..........27316.4.3

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DMA channel alternate control data base pointer register16.4.4
(DMA_ALT_CTRL_BASE_PTR) ..........................................................................273
DMA channel wait on request status register (DMA_WAITONREQ_STATUS)16.4.5
274
DMA channel software request register (DMA_CHNL_SW_REQUEST) .....27416.4.6
DMA channel useburst set register (DMA_CHNL_USEBURST_SET) .........27516.4.7
DMA channel useburst clear register (DMA_CHNL_USEBURST_CLR) ......27616.4.8
DMA channel request mask set register (DMA_CHNL_REQ_MASK_SET) ...27616.4.9
DMA channel request mask clear register (DMA_CHNL_REQ_MASK_CLR) 27716.4.10
DMA channel enable set register (DMA_CHNL_ENABLE_SET)...............27716.4.11
DMA channel enable clear register (DMA_CHNL_ENABLE_CLR) ............27816.4.12
DMA channel primary-alternate set register (DMA_CHNL_PRI_ALT_SET) 27816.4.13
DMA channel primary-alternate clear register (DMA_CHNL_PRI_ALT _CLR)16.4.14
279
DMA channel priority set register (DMA_CHNL_PRIORITY_SET)............28016.4.15
DMA channel priority clear register (DMA_CHNL_PRIORITY_CLR) .........28016.4.16
DMA bus error clear register (DMA_ERR_CLR) ................................28116.4.17
Register map ...............................................................................28216.5
17Analog-to-digital converter (ADC) ............................................................... 283
Introduction ................................................................................28317.1
Features ....................................................................................28317.2
Functional description ...................................................................28417.3
Operation ADC with non-interrupt..............................................28417.3.1
Operation ADC with interrupt ...................................................28617.3.2
Registers (Base address : 0x4100_0000)...............................................28617.4
ADC control register (ADC_CTR) ................................................28617.4.1
ADC channel select register (ADC_CHSEL) ....................................28717.4.2
ADC start register (ADC_START).................................................28817.4.3
ADC conversion data register (ADC_DATA) ....................................28817.4.4
ADC Interrupt register (ADC_INT)...............................................28817.4.5
ADC Interrupt Clear register (ADC_INTCLR) ..................................28917.4.6
Register map ...............................................................................29017.5
18Pulse-Width Modulation (PWM)................................................................... 291
Introduction ................................................................................29118.1
Features ....................................................................................29118.2
Functional description ...................................................................29218.3
Timer/Counter control ...........................................................29218.3.1
Timer/Counter .....................................................................29218.3.2
PWM mode ..........................................................................29618.3.3

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Interrupt ............................................................................29718.3.4
Dead zone generation ............................................................29818.3.5
Capture event ......................................................................29918.3.6
How to set the PWM ..............................................................30118.3.7
PWM Channel-0 Registers (Base address : 0x4000_5000)...........................30218.4
Channel-0 interrupt register(PWMCH0IR) .....................................30218.4.1
Channel-0 interrupt enable register(PWMCH0IER)...........................30218.4.2
Channel-0 interrupt clear register(PWMCH0ICR).............................30318.4.3
Channel-0 Timer/Counter Register (PWMCH0TCR) ..........................30318.4.4
Channel-0 Prescale Counter Register (PWMCH0PCR) ........................30418.4.5
Channel-0 Prescale Register (PWMCH0PR) ....................................30418.4.6
Channel-0 Match Register (PWMCH0MR).......................................30518.4.7
Channel-0 Limit Register (PWMCH0LR) ........................................30518.4.8
Channel-0 Up-Down Mode Register (PWMCH0UDMR) ........................30618.4.9
Channel-0 Timer/Counter Mode Register (PWMCH0TCMR) .................30618.4.10
Channel-0 PWM output Enable and External input Enable Register18.4.11
(PWMCH0PEEER) 307
Channel-0 Capture Mode Register (PWMCH0CMR) ...........................30718.4.12
Channel-0 Capture Register (PWMCH0CR).....................................30718.4.13
Channel-0 Periodic Mode Register (PWMCH0PDMR) .........................30818.4.14
Channel-0 Dead Zone Enable Register (PWMCH0DZER) .....................30818.4.15
Channel-0 Dead Zone Counter Register (PWMCH0DZCR) ...................30918.4.16
Register map ...............................................................................31018.5
PWM Channel-1 Registers (Base address : 0x4000_5100)...........................31118.6
Channel-1 interrupt register(PWMCH1IR) .....................................31118.6.1
Channel-1 interrupt enable register(PWMCH1IER)...........................31118.6.2
Channel-1 interrupt clear register(PWMCH1ICR).............................31218.6.3
Channel-1 Timer/Counter Register (PWMCH1TCR) ..........................31218.6.4
Channel-1 Prescale Counter Register (PWMCH1PCR) ........................31318.6.5
Channel-1 Prescale Register (PWMCH1PR) ....................................31318.6.6
Channel-1 Match Register (PWMCH1MR).......................................31418.6.7
Channel-1 Limit Register (PWMCH1LR) ........................................31418.6.8
Channel-1 Up-Down Mode Register (PWMCH1UDMR) ........................31518.6.9
Channel-1 Timer/Counter Mode Register (PWMCH1TCMR) .................31518.6.10
Channel-1 PWM output Enable and External input Enable Register18.6.11
(PWMCH1PEEER) 316
Channel-1 Capture Mode Register (PWMCH1CMR) ...........................31618.6.12
Channel-1 Capture Register (PWMCH1CR).....................................31618.6.13
Channel-1 Periodic Mode Register (PWMCH1PDMR) .........................31718.6.14

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Channel-1 Dead Zone Enable Register (PWMCH1DZER) .....................31718.6.15
Channel-1 Dead Zone Counter Register (PWMCH1DZCR) ...................31818.6.16
Register map ...............................................................................31918.7
PWM Channel-2 Registers (Base address : 0x4000_5200)...........................32018.8
Channel-2 interrupt register(PWMCH2IR) .....................................32018.8.1
Channel-2 interrupt enable register(PWMCH2IER)...........................32018.8.2
Channel-2 interrupt clear register(PWMCH2ICR).............................32118.8.3
Channel-2 Timer/Counter Register (PWMCH2TCR) ..........................32118.8.4
Channel-2 Prescale Counter Register (PWMCH2PCR) ........................32218.8.5
Channel-2 Prescale Register (PWMCH2PR) ....................................32218.8.6
Channel-2 Match Register (PWMCH2MR).......................................32318.8.7
Channel-2 Limit Register (PWMCH2LR) ........................................32318.8.8
Channel-2 Up-Down Mode Register (PWMCH2UDMR) ........................32318.8.9
Channel-2 Timer/Counter Mode Register (PWMCH2TCMR) .................32418.8.10
Channel-2 PWM output Enable and External input Enable Register18.8.11
(PWMCH2PEEER) 324
Channel-2 Capture Mode Register (PWMCH2CMR) ...........................32518.8.12
Channel-2 Capture Register (PWMCH2CR).....................................32518.8.13
Channel-2 Periodic Mode Register (PWMCH2PDMR) .........................32618.8.14
Channel-2 Dead Zone Enable Register (PWMCH2DZER) .....................32618.8.15
Channel-2 Dead Zone Counter Register (PWMCH2DZCR) ...................32718.8.16
Register map ...............................................................................32818.9
PWM Channel-3 Registers (Base address : 0x4000_5300)...........................32918.10
Channel-3 interrupt register(PWMCH3IR) .....................................32918.10.1
Channel-3 interrupt enable register(PWMCH3IER)...........................32918.10.2
Channel-3 interrupt clear register(PWMCH3ICR).............................33018.10.3
Channel-3 Timer/Counter Register (PWMCH3TCR) ..........................33018.10.4
Channel-3 Prescale Counter Register (PWMCH3PCR) ........................33118.10.5
Channel-3 Prescale Register (PWMCH3PR) ....................................33118.10.6
Channel-3 Match Register (PWMCH3MR).......................................33218.10.7
Channel-3 Limit Register (PWMCH3LR) ........................................33218.10.8
Channel-3 Up-Down Mode Register (PWMCH3UDMR) ........................33318.10.9
Channel-3 Timer/Counter Mode Register (PWMCH3TCMR) .................33318.10.10
Channel-3 PWM output Enable and External input Enable Register18.10.11
(PWMCH3PEEER) 334
Channel-3 Capture Mode Register (PWMCH3CMR) ...........................33418.10.12
Channel-3 Capture Register (PWMCH3CR).....................................33418.10.13
Channel-3 Periodic Mode Register (PWMCH3PDMR) .........................33518.10.14
Channel-3 Dead Zone Enable Register (PWMCH3DZER) .....................33518.10.15

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Channel-3 Dead Zone Counter Register (PWMCH3DZCR) ...................33618.10.16
Register map ...............................................................................33718.11
PWM Channel-4 Registers (Base address : 0x4000_5400)...........................33818.12
Channel-4 interrupt register(PWMCH4IR) .....................................33818.12.1
Channel-4 interrupt enable register(PWMCH4IER)...........................33818.12.2
Channel-4 interrupt clear register(PWMCH4ICR).............................33918.12.3
Channel-4 Timer/Counter Register (PWMCH4TCR) ..........................33918.12.4
Channel-4 Prescale Counter Register (PWMCH4PCR) ........................34018.12.5
Channel-4 Prescale Register (PWMCH4PR) ....................................34018.12.6
Channel-4 Match Register (PWMCH4MR).......................................34118.12.7
Channel-4 Limit Register (PWMCH4LR) ........................................34118.12.8
Channel-4 Up-Down Mode Register (PWMCH4UDMR) ........................34118.12.9
Channel-4 Timer/Counter Mode Register (PWMCH4TCMR) .................34218.12.10
Channel-4 PWM output Enable and External input Enable Register18.12.11
(PWMCH4PEEER) 342
Channel-4 Capture Mode Register (PWMCH4CMR) ...........................34318.12.12
Channel-4 Capture Register (PWMCH4CR).....................................34318.12.13
Channel-4 Periodic Mode Register (PWMCH4PDMR) .........................34418.12.14
Channel-4 Dead Zone Enable Register (PWMCH4DZER) .....................34418.12.15
Channel-4 Dead Zone Counter Register (PWMCH4DZCR) ...................34518.12.16
Register map ...............................................................................34618.13
PWM Channel-5 Registers (Base address : 0x4000_5500)...........................34718.14
Channel-5 interrupt register(PWMCH5IR) .....................................34718.14.1
Channel-5 interrupt enable register(PWMCH5IER)...........................34718.14.2
Channel-5 interrupt clear register(PWMCH5ICR).............................34818.14.3
Channel-5 Timer/Counter Register (PWMCH5TCR) ..........................34818.14.4
Channel-5 Prescale Counter Register (PWMCH5PCR) ........................34918.14.5
Channel-5 Prescale Register (PWMCH5PR) ....................................34918.14.6
Channel-5 Match Register (PWMCH5MR).......................................35018.14.7
Channel-5 Limit Register (PWMCH5LR) ........................................35018.14.8
Channel-5 Up-Down Mode Register (PWMCH5UDMR) ........................35018.14.9
Channel-5 Timer/Counter Mode Register (PWMCH5TCMR) .................35118.14.10
Channel-5 PWM output Enable and External input Enable Register18.14.11
(PWMCH5PEEER) 351
Channel-5 Capture Mode Register (PWMCH5CMR) ...........................35218.14.12
Channel-5 Capture Register (PWMCH5CR).....................................35218.14.13
Channel-5 Periodic Mode Register (PWMCH5PDMR) .........................35318.14.14
Channel-5 Dead Zone Enable Register (PWMCH5DZER) .....................35318.14.15
Channel-5 Dead Zone Counter Register (PWMCH5DZCR) ...................35418.14.16

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Register map ...............................................................................35518.15
PWM Channel-6 Registers (Base address : 0x4000_5600)...........................35618.16
Channel-6 interrupt register(PWMCH6IR) .....................................35618.16.1
Channel-6 interrupt enable register(PWMCH6IER)...........................35618.16.2
Channel-6 interrupt clear register(PWMCH6ICR).............................35718.16.3
Channel-6 Timer/Counter Register (PWMCH6TCR) ..........................35718.16.4
Channel-6 Prescale Counter Register (PWMCH6PCR) ........................35818.16.5
Channel-6 Prescale Register (PWMCH6PR) ....................................35818.16.6
Channel-6 Match Register (PWMCH6MR).......................................35918.16.7
Channel-6 Limit Register (PWMCH6LR) ........................................35918.16.8
Channel-6 Up-Down Mode Register (PWMCH6UDMR) ........................35918.16.9
Channel-6 Timer/Counter Mode Register (PWMCH6TCMR) .................36018.16.10
Channel-6 PWM output Enable and External input Enable Register18.16.11
(PWMCH6PEEER) 360
Channel-6 Capture Mode Register (PWMCH6CMR) ...........................36118.16.12
Channel-6 Capture Register (PWMCH6CR).....................................36118.16.13
Channel-6 Periodic Mode Register (PWMCH6PDMR) .........................36218.16.14
Channel-6 Dead Zone Enable Register (PWMCH6DZER) .....................36218.16.15
Channel-6 Dead Zone Counter Register (PWMCH6DZCR) ...................36318.16.16
Register map ...............................................................................36418.17
PWM Channel-7 Registers (Base address : 0x4000_5700)...........................36518.18
Channel-7 interrupt register(PWMCH7IR) .....................................36518.18.1
Channel-7 interrupt enable register(PWMCH7IER)...........................36518.18.2
Channel-7 interrupt clear register(PWMCH7ICR).............................36618.18.3
Channel-7 Timer/Counter Register (PWMCH7TCR) ..........................36618.18.4
Channel-7 Prescale Counter Register (PWMCH7PCR) ........................36718.18.5
Channel-7 Prescale Register (PWMCH7PR) ....................................36718.18.6
Channel-7 Match Register (PWMCH7MR).......................................36818.18.7
Channel-7 Limit Register (PWMCH7LR) ........................................36818.18.8
Channel-7 Up-Down Mode Register (PWMCH7UDMR) ........................36818.18.9
Channel-7 Timer/Counter Mode Register (PWMCH7TCMR) .................36918.18.10
Channel-7 PWM output Enable and External input Enable Register18.18.11
(PWMCH7PEEER) 369
Channel-7 Capture Mode Register (PWMCH7CMR) ...........................37018.18.12
Channel-7 Capture Register (PWMCH7CR).....................................37018.18.13
Channel-7 Periodic Mode Register (PWMCH7PDMR) .........................37118.18.14
Channel-7 Dead Zone Enable Register (PWMCH7DZER) .....................37118.18.15
Channel-7 Dead Zone Counter Register (PWMCH7DZCR) ...................37218.18.16
Register map ...............................................................................37318.19

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PWM Common Registers (Base address : 0x4000_5800) ............................37418.20
Interrupt Enable Register (IER)..................................................37418.20.1
Start/Stop Register (SSR).........................................................37518.20.2
Pause Register (PSR) ..............................................................37618.20.3
Register map ...............................................................................37718.21
19Dual timers ........................................................................................... 378
Introduction ................................................................................37819.1
Features ....................................................................................37819.2
Functional description ...................................................................37919.3
Clock and clock enable ...........................................................37919.3.1
Timer size ...........................................................................37919.3.2
Prescaler ............................................................................37919.3.3
Repetition mode ...................................................................37919.3.4
Interrupt ............................................................................38019.3.5
Operation ...........................................................................38019.3.6
How to set the dual timers ......................................................38119.3.7
Dual timer0_0 Registers (Base address : 0x4000_1000) ............................38219.4
Timer0_0 Load Register(DUALTIMER0_0TimerLoad) .........................38219.4.1
Timer0_0 Value Register(DUALTIMER0_0TimerValue)........................38219.4.2
Timer0_0 Control Register(DUALTIMER0_0TimerControl)...................38219.4.3
Timer0_0 Interrupt Clear Register (DUALTIMER0_0TimerIntClr)...........38319.4.4
Timer0_0 Raw Interrupt Status Register (DUALTIMER0_0TimerRIS).......38419.4.5
Timer0_0 Masked Interrupt Status Register (DUALTIMER0_0TimerMIS) ..38419.4.6
Timer0_0 Background Load Register (DUALTIMER0_0TimerBGLoad)......38519.4.7
Register map ...............................................................................38619.5
Dual timer0_1 Registers (Base address : 0x4000_1020) ............................38719.6
Timer0_1 Load Register(DUALTIMER0_1TimerLoad) .........................38719.6.1
Timer0_1 Value Register(DUALTIMER0_1TimerValue)........................38719.6.2
Timer0_1 Control Register(DUALTIMER0_1TimerControl)...................38719.6.3
Timer0_1 Interrupt Clear Register (DUALTIMER0_1TimerIntClr)...........38819.6.4
Timer0_1 Raw Interrupt Status Register (DUALTIMER0_1TimerRIS).......38819.6.5
Timer0_1 Masked Interrupt Status Register (DUALTIMER0_1TimerMIS) ..38919.6.6
Timer0_1 Background Load Register (DUALTIMER0_1TimerBGLoad)......38919.6.7
Register map ...............................................................................39119.7
Dual Timer 0 Clock Enable Register (Base address : 0x4000_1080) ..............39219.8
Timer0_0 Clock Enable Register (TIMCLKEN0_0) .............................39219.8.1
Timer0_1 Clock Enable Register (TIMCLKEN0_1) .............................39219.8.2
Register map ...............................................................................39319.9
Dual timer1_0 Registers (Base address : 0x4000_2000) ............................39419.10

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Timer1_0 Load Register(DUALTIMER1_0TimerLoad) .........................39419.10.1
Timer1_0 Value Register(DUALTIMER1_0TimerValue)........................39419.10.2
Timer1_0 Control Register(DUALTIMER1_0TimerControl)...................39419.10.3
Timer1_0 Interrupt Clear Register (DUALTIMER1_0TimerIntClr)...........39519.10.4
Timer1_0 Raw Interrupt Status Register (DUALTIMER1_0TimerRIS).......39519.10.5
Timer1_0 Masked Interrupt Status Register (DUALTIMER1_0TimerMIS) ..39619.10.6
Timer1_0 Background Load Register (DUALTIMER1_0TimerBGLoad)......39619.10.7
Register map ...............................................................................39819.11
Dual timer1_1 Registers (Base address : 0x4000_2020) ............................39919.12
Timer1_1 Load Register(DUALTIMER1_1TimerLoad) .........................39919.12.1
Timer1_1 Value Register(DUALTIMER1_1TimerValue)........................39919.12.2
Timer1_1 Control Register(DUALTIMER1_1TimerControl)...................39919.12.3
Timer1_1 Interrupt Clear Register (DUALTIMER1_1TimerIntClr)...........40019.12.4
Timer1_1 Raw Interrupt Status Register (DUALTIMER1_1TimerRIS).......40019.12.5
Timer1_1 Masked Interrupt Status Register (DUALTIMER1_1TimerMIS) ..40119.12.6
Timer1_1 Background Load Register (DUALTIMER1_1TimerBGLoad)......40119.12.7
Register map ...............................................................................40319.13
Dual Timer 1 Clock Enable Register (Base address : 0x4000_2080) ..............40419.14
Timer1_0 Clock Enable Register (TIMCLKEN1_0) .............................40419.14.1
Timer1_1 Clock Enable Register (TIMCLKEN1_1) .............................40419.14.2
Register map ...............................................................................40519.15
20Watchdog timer...................................................................................... 406
20.1 Introduction ................................................................................406
20.2 Features ....................................................................................406
20.3 Functional description ...................................................................406
20.3.1 Clock.................................................................................406
20.3.2 Interrupt and reset request......................................................406
20.4 Watchdog timer Registers (Base address : 0x4000_0000) ..........................407
20.4.1 Watchdog timer Load Register(WDTLoad).....................................407
20.4.2 Watchdog timer Value Register(WDTValue) ...................................407
20.4.3 Watchdog timer Control Register(WDTControl) ..............................408
20.4.4 Watchdog timer Interrupt Clear Register (WDTIntClr) ......................408
20.4.5 Watchdog timer Raw Interrupt Status Register (WDTRIS) ..................408
20.4.6 Watchdog timer Raw Interrupt Status Register (WDTMIS) ..................409
20.4.7 Watchdog timer Lock Register(WDTLock) .....................................409
Register map ...............................................................................41120.5
21Inter-integrated circuit interface (I2C)......................................................... 412
Introduction ................................................................................41221.1
Features ....................................................................................41221.2

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Functional description ...................................................................41221.3
Data validity........................................................................41321.3.1
Acknowledge .......................................................................41421.3.2
Bit Command Controller..........................................................41421.3.3
Slave address .......................................................................41521.3.4
Read/Write bit .....................................................................41521.3.5
Acknowledge(ACK) and Not Acknowledge(NACK) ............................41621.3.6
Data transfer .......................................................................41621.3.7
Operating Modes ...................................................................41621.3.8
Interrupts ...........................................................................41721.3.9
Master mode........................................................................41821.3.10
Slave mode .........................................................................42121.3.11
I2C0 Registers(Base address: 0x4000_8000) ..........................................42221.4
I2C0 Prescaler Register(I2C0_PRER) ............................................42221.4.1
I2C0 Control Register(I2C0_CTR)................................................42321.4.2
I2C0 Command Register(I2C0_CMDR) ..........................................42421.4.3
I2C0 Status Register(I2C0_SR) ...................................................42421.4.4
I2C0 Timeout Set Register(I2C0_TSR) ..........................................42621.4.5
I2C0 Slave Address Register(I2C0_SADDR) .....................................42621.4.6
I2C0 Transmit Register(I2C0_TXR) ..............................................42721.4.7
I2C0 Receive Register(I2C0_RXR) ...............................................42721.4.8
I2C0 Interrupt Status Register(I2C0_ISR) ......................................42821.4.9
I2C0 Interrupt Status Clear Register(I2C0_ISCR) .............................42821.4.10
I2C0 Interrupt Status Mask Register(I2C0_ISMR) .............................42921.4.11
Register map ...............................................................................43121.5
I2C1 Registers(Base address : 0x4000_9000) .........................................43221.6
I2C1 Prescaler Register(I2C1_PRER) ............................................43221.6.1
I2C1 Control Register(I2C1_CTR)................................................43321.6.2
I2C1 Command Register(I2C1_CMDR) ..........................................43421.6.3
I2C1 Status Register(I2C1_SR) ...................................................43421.6.4
I2C1 Timeout Set Register(I2C1_TSR) ..........................................43621.6.5
I2C1 Slave Address Register(I2C1_SADDR) .....................................43621.6.6
I2C1 Transmit Register(I2C1_TXR) ..............................................43721.6.7
I2C1 Receive Register(I2C1_RXR) ...............................................43721.6.8
I2C1 Interrupt Status Register(I2C1_ISR) ......................................43821.6.9
I2C1 Interrupt Status Clear Register(I2C1_ISCR) .............................43821.6.10
I2C1 Interrupt Status Mask Register(I2C1_ISMR) .............................43921.6.11
Register map ...............................................................................44121.7
22UART(Universal Asynchronous Receive Transmit)............................................ 442