Wiznet W7500 User manual

© Copyright 2018 WIZnet Co., Ltd. All rights reserved.
W7500x
Reference Manual
Version 1.1.0
http://www.wiznet.io

W7500x Reference Manual Version1.1.0 2 / 399
1Table of Contents
1Table of Contents....................................................................................... 2
2List of table............................................................................................. 19
3List of figures........................................................................................... 21
4Documentation conventions ........................................................................ 23
4.1 Glossary ...................................................................................... 23
4.2 Register Bit Conventions .................................................................. 25
5System and memory overview ..................................................................... 26
5.1 System architecture ....................................................................... 26
5.2 Memory organization ...................................................................... 27
Introduction ....................................................................................... 27
Memory map ...................................................................................... 28
6System configuration controller (SYSCFG)....................................................... 29
7Interrupt and events ................................................................................. 29
7.1 Nested vectored interrupt controller (NVIC) .......................................... 29
NVIC main features .............................................................................. 29
SysTick calibration value register ............................................................. 29
Interrupt and exception vectors............................................................... 29
7.2 Event ......................................................................................... 30
8Power supply ........................................................................................... 31
8.1 Introduction ................................................................................. 31
8.2 Voltage regulator........................................................................... 31
8.3 Low-power modes.......................................................................... 31
Sleep mode........................................................................................ 32
Peripheral clock gating.......................................................................... 32
9System tick timer ..................................................................................... 33
9.1 Introduction ................................................................................. 33
9.2 Features ..................................................................................... 33
9.3 Functional description .................................................................... 33
9.4 Registers (Base : 0xE000_E000).......................................................... 34
System Timer control and status register (SYST_CSR)..................................... 34
SysTick Reload Value Register (SYST_RVR)................................................... 34
SysTick Current Value Register (SYST_CVR) ................................................. 35
SysTick Calibration Value Register (SYST_CALIB) ........................................... 35
10Booting Sequence ..................................................................................... 36
11Embedded Flash memory............................................................................ 37
11.1 Flash main features........................................................................ 37
11.2 Flash memory organization............................................................... 37

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12Clock Reset generator (CRG)........................................................................ 39
12.1 Introduction ................................................................................. 39
12.2 Features ..................................................................................... 39
Reset....... ........................................................................................ 39
Clock....... ........................................................................................ 40
12.3 Functional description .................................................................... 41
External Oscillator Clock ....................................................................... 41
RC oscillator clock ............................................................................... 42
PLL.................................................................................................. 42
Generated clock.................................................................................. 42
12.4 Registers (Base address : 0x4100_1000)................................................ 44
OSC power down register (OSC_PDR)......................................................... 44
PLL power down register (PLL_PDR) .......................................................... 44
PLL frequency calculating register (PLL_FCR) .............................................. 44
PLL output enable register (PLL_OER) ....................................................... 45
PLL bypass register (PLL_BPR) ................................................................. 45
PLL input clock source select register (PLL_IFSR).......................................... 46
FCLK source select register (FCLK_SSR)...................................................... 46
FCLK prescale value select register (FCLK_PVSR) .......................................... 47
SSPCLK source select register (SSPCLK_SSR) ................................................ 47
SSPCLK prescale value select register (SSPCLK_PVSR) .................................... 48
ADCCLK source select register (ADCCLK_SSR) .............................................. 48
ADCCLK prescale value select register (ADCCLK_PVSR) ................................... 48
TIMER0CLK source select register (TIMER0CLK_SSR)....................................... 49
TIMER0CLK prescale value select register (TIMER0CLK_PVSR) ........................... 49
TIMER1CLK source select register (TIMER1CLK_SSR)....................................... 50
TIMER1CLK prescale value select register (TIMER1CLK_PVSR) ........................... 50
PWM0CLK source select register (PWM0CLK_SSR) .......................................... 51
PWM0CLK prescale value select register (PWM0CLK_PVSR) .............................. 51
PWM1CLK source select register (PWM1CLK_SSR) .......................................... 52
PWM1CLK prescale value select register (PWM1CLK_PVSR) .............................. 52
PWM2CLK source select register (PWM2CLK_SSR) .......................................... 53
PWM2CLK prescale value select register (PWM2CLK_PVSR) .............................. 53
PWM3CLK source select register (PWM3CLK_SSR) .......................................... 54
PWM3CLK prescale value select register (PWM3CLK_PVSR) .............................. 55
PWM4CLK source select register (PWM4CLK_SSR) .......................................... 55
PWM4CLK prescale value select register (PWM4CLK_PVSR) .............................. 56
PWM5CLK source select register (PWM5CLK_SSR) .......................................... 56
PWM5CLK prescale value select register (PWM5CLK_PVSR) .............................. 57

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PWM6CLK source select register (PWM6CLK_SSR) .......................................... 57
PWM6CLK prescale value select register (PWM6CLK_PVSR) .............................. 58
PWM7CLK source select register (PWM7CLK_SSR).......................................... 58
PWM7CLK prescale value select register (PWM7CLK_PVSR) .............................. 59
RTC High Speed source select register (RTC_HS_SSR) ..................................... 59
RTC High Speed prescale value select register (RTC_HS_PVSR) ......................... 60
RTC source select register (RTC_SSR) ........................................................ 60
WDOGCLK High Speed source select register (WDOGCLK_HS_SSR)...................... 61
WDOGCLK High Speed prescale value select register (WDOGCLK_HS_PVSR) .......... 61
WDOGCLK clock source select register (WDOGCLK_SSR).................................. 62
UARTCLK source select register (UARTCLK_SSR) ........................................... 62
UARTCLK prescale value select register (UARTCLK_PVSR)................................ 63
MIICLK enable control register (MIICLK_ECR) ............................................... 63
Monitoring Clock source select register (MONCLK_SSR) ................................... 64
12.5 Register map ................................................................................ 65
13Tcp/ip core Offload Engine (TOE) ..................................................................67
13.1 Introduction ................................................................................. 67
13.2 Features ..................................................................................... 67
13.3 Functional description .................................................................... 68
13.4 TOE Memory map........................................................................... 68
Common register map........................................................................... 70
Socket register map ............................................................................. 70
Memory............................................................................................. 71
13.5 Common register (Base : 0x4600_0000) ................................................ 73
VERSIONR (TOE Version Register).............................................................. 73
TCKCNTR (Ticker Counter Register) .......................................................... 73
IR (Interrupt Register)........................................................................... 74
IMR (Interrupt Mask Register) .................................................................. 74
IRCR (Interrupt Clear Register) ................................................................ 75
SIR (Socket Interrupt Register) ................................................................ 76
SIMR (Socket Interrupt Mask Register)........................................................ 76
MR (Mode Register) .............................................................................. 77
PTIMER (PPP Link Control Protocol Request Timer Register) ............................. 78
PMAGICR (PPP Link Control Protocol Magic number Register) ........................... 78
PHAR (Destination Hardware Address Register in PPPoE) ................................. 78
PSIDR (Session ID Register in PPPoE).......................................................... 79
PMRUR (Maximum Receive Unit Register in PPPoE) ........................................ 80
SHAR (Source Hardware Address Register)................................................... 80
GAR (Gateway Address) ......................................................................... 81

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SUBR ( Subnet Mask Register) .................................................................. 81
SIPR (Source IP address Register) ............................................................. 82
NCONFLR ( Network Configuration Lock Register) ......................................... 82
RTR (Retry Time Register) ...................................................................... 83
RCR (Retry Counter Register) .................................................................. 84
UIPR (Unreachable IP address Register)...................................................... 85
UPORTR (Unreachable Port Register) ......................................................... 86
13.6 Socket register (Base : 0x4601_0000 + 0x0004_000 x n)[n=0,…7, where n is
socket number] ......................................................................................... 86
Sn_MR (Socket n Mode Register)............................................................... 86
Sn_CR (Socket n Command Register) ......................................................... 89
Sn_IR (Socket n Interrupt Register) ........................................................... 91
Sn_IMR (Socket n Interrupt Mask Register) .................................................. 91
Sn_ICR (Socket n Interrupt Clear Register) .................................................. 92
Sn_SR (Socket n Status Register) .............................................................. 93
Sn_PNR (Socket n Protocol Number Register) ............................................... 95
Sn_TOSR (Socket n IP Type of Service Register) ............................................ 96
Sn_TTLR (Socket n TTL Register) .............................................................. 96
Sn_FRAGR (Socket n Fragment offset Register) ............................................ 97
Sn_MSSR (Socket n Maximum Segment Register) ........................................... 97
Sn_PORTR (Socket n Source Port Register) .................................................. 98
Sn_DHAR (Socket n Destination Hardware address Register)............................. 98
Sn_DPORTR (Socket n Destination Port Number Register) ................................ 99
Sn_DIPR (Socket n Destination IP address Register).......................................100
Sn_KATMR (Socket n Keep Alive Timer Register)...........................................101
Sn_RTR (Socket n Retry Time Register) ...................................................101
Sn_RCR (Socket n Retry Counter Register) .................................................102
Sn_TXBUF_SIZE (Socket n TX Buffer Size Register)........................................102
Sn_TX_FSR (Socket n TX Free Size Register) ...............................................103
Sn_TX_RD (Socket n TX Read Pointer Register) ............................................104
Sn_TX_WR (Socket n TX Write Pointer Register)...........................................105
Sn_RXBUF_SIZE (Socket n RX Buffer Size Register)........................................105
Sn_RX_RSR (Socket n RX Received Size Register) .........................................106
Sn_RX_RD (Socket n RX Read Pointer Register) ............................................107
Sn_RX_WR (Socket n RX Write Pointer Register)...........................................108
14Random number generator (RNG) ............................................................... 109
14.1 Introduction ................................................................................109
14.2 Features ....................................................................................109
14.3 Functional description ...................................................................109

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Operation RNG...................................................................................110
14.4 Registers (Base address : 0x4000_7000)...............................................111
RNG run register (RNG_RUN)..................................................................111
RNG SEED register (RNG_SEED) ...............................................................111
RNG clock select register (RNG_CLKSEL) ...................................................111
RNG manual mode select register (RNG_MODE) ...........................................112
RNG random number value register (RNG_RN) ............................................112
RNG polynomial register (RNG_POLY) .......................................................113
14.5 Register map ...............................................................................114
15Alternate Function Controller (AFC) ............................................................ 114
15.1 Introduction ................................................................................114
15.2 Features ....................................................................................114
15.3 Functional description ...................................................................114
15.4 Registers (Base address : 0x4100_2000)...............................................117
PA_00 pad alternate function select register (PA_00_AFR) ..............................117
PA_01 pad alternate function select register (PA_01_AFR) ..............................117
PA_02 pad alternate function select register (PA_02_AFR) ..............................118
PA_03 pad alternate function select register (PA_03_AFR) ..............................118
PA_04 pad alternate function select register (PA_04_AFR) ..............................119
PA_05 pad alternate function select register (PA_05_AFR) ..............................119
PA_06 pad alternate function select register (PA_06_AFR) ..............................120
PA_07 pad alternate function select register (PA_07_AFR) ..............................120
PA_08 pad alternate function select register (PA_08_AFR) ..............................121
PA_09 pad alternate function select register (PA_09_AFR) ..............................121
PA_10 pad alternate function select register (PA_10_AFR) ..............................122
PA_11 pad alternate function select register (PA_11_AFR) ..............................122
PA_12 pad alternate function select register (PA_12_AFR) ..............................123
PA_13 pad alternate function select register (PA_13_AFR) ..............................123
PA_14 pad alternate function select register (PA_14_AFR) ..............................124
PA_15 pad alternate function select register (PA_15_AFR) ..............................124
PB_00 pad alternate function select register (PB_00_AFR) .............................125
PB_01 pad alternate function select register (PB_01_AFR) .............................125
PB_02 pad alternate function select register (PB_02_AFR) .............................126
PB_03 pad alternate function select register (PB_03_AFR) .............................126
PB_04 pad alternate function select register (PB_04_AFR) .............................127
PB_05 pad alternate function select register (PB_05_AFR) .............................127
PB_06 pad alternate function select register (PB_06_AFR) .............................128
PB_07 pad alternate function select register (PB_07_AFR) .............................128
PB_08 pad alternate function select register (PB_08_AFR) .............................129

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PB_09 pad alternate function select register (PB_09_AFR) .............................129
PB_10 pad alternate function select register (PB_10_AFR) .............................130
PB_11 pad alternate function select register (PB_11_AFR) .............................130
PB_12 pad alternate function select register (PB_12_AFR) .............................131
PB_13 pad alternate function select register (PB_13_AFR) .............................131
PB_14 pad alternate function select register (PB_14_AFR) .............................132
PB_15 pad alternate function select register (PB_15_AFR) .............................132
PC_00 pad alternate function select register (PC_00_AFR) .............................133
PC_01 pad alternate function select register (PC_01_AFR) .............................133
PC_02 pad alternate function select register (PC_02_AFR) .............................134
PC_03 pad alternate function select register (PC_03_AFR) .............................134
PC_04 pad alternate function select register (PC_04_AFR) .............................135
PC_05 pad alternate function select register (PC_05_AFR) .............................135
PC_06 pad alternate function select register (PC_06_AFR) .............................136
PC_07 pad alternate function select register (PC_07_AFR) .............................136
PC_08 pad alternate function select register (PC_08_AFR) .............................137
PC_09 pad alternate function select register (PC_09_AFR) .............................137
PC_10 pad alternate function select register (PC_10_AFR) .............................138
PC_11 pad alternate function select register (PC_11_AFR) .............................138
PC_12 pad alternate function select register (PC_12_AFR) .............................139
PC_13 pad alternate function select register (PC_13_AFR) .............................139
PC_14 pad alternate function select register (PC_14_AFR) .............................140
PC_15 pad alternate function select register (PC_15_AFR) .............................140
PD_00 pad alternate function select register (PD_00_AFR) .............................141
PD_01 pad alternate function select register (PD_01_AFR) .............................141
PD_02 pad alternate function select register (PD_02_AFR) .............................142
PD_03 pad alternate function select register (PD_03_AFR) .............................142
PD_04 pad alternate function select register (PD_04_AFR) .............................143
15.5 Register map ...............................................................................144
16External Interrupt (EXTI) .......................................................................... 147
16.1 Introduction ................................................................................147
16.2 Features ....................................................................................147
16.3 Functional description ...................................................................147
16.4 Registers (Base address : 0x4100_2000)...............................................149
External interrupt enable register (Px_y EXTINT).........................................149
16.5 Register map ...............................................................................149
17Pad Controller (PADCON) .......................................................................... 150
17.1 Introduction ................................................................................150
17.2 Features ....................................................................................150

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17.3 Functional description ...................................................................150
17.4 Registers (Base address : 0x4100_3000)...............................................152
PAD Control register (Px_y PCR)(x=A..D, y=0..15) ........................................152
17.5 Register map ...............................................................................152
18General-purpose I/Os(GPIO)....................................................................... 153
18.1 Introduction ................................................................................153
18.2 Features ....................................................................................153
18.3 Functional description ...................................................................153
Masked access ...................................................................................154
18.4 GPIO Registers(Address Base: 0x4200_0000) .........................................156
GPIO Data Register(GPIOx_DATA) (x=A..D) .................................................156
GPIO Output Latch Register(GPIOx_DATAOUT) (x=A..D)..................................156
GPIO Enable Set Register(GPIOx_OUTENSET) (x=A..D) ...................................156
GPIO Enable Clear Register(GPIOx_OUTENCLR) (x=A..D) ................................157
GPIO Interrupt Enable Set Register(GPIOx_ INTENSET) (x=A..D) .......................157
GPIO Interrupt Enable Clear Register(GPIOx_ INTENCLR) (x=A..D).....................158
GPIO Interrupt Type Set Register(GPIOx_ INTTYPESET) (x=A..D) .......................158
GPIO Interrupt Type Clear Register(GPIOx_ INTTYPECLR) (x=A..D) ....................159
GPIO Interrupt Polarity Set Register(GPIOx_ INTPOLSET) (x=A..D).....................159
GPIO Interrupt Polarity Clear Register(GPIOx_ INTPOLCLR) (x=A..D) ..................160
GPIO Interrupt Status/Clear Register(GPIO_ INTSTATUS/INTCLEAR) (x=A..D)........161
GPIO Lower Byte Masked Access Register(GPIOx_ LB_MASKED) (x=A..D)..............161
GPIO Upper Byte Masked Access Register(GPIOx_ UB_MASKED) (x=A..D) .............162
18.5 Register map ...............................................................................163
19Direct memory access controller (DMA)........................................................ 164
19.1 Introduction ................................................................................164
19.2 Features ....................................................................................164
19.3 Functional description ...................................................................164
DMA request mapping ..........................................................................165
DMA arbitration..................................................................................165
DMA cycle types .................................................................................165
19.4 Registers (Base address : 0x4100_4000)...............................................168
DMA status register (DMA_STATUS) ...........................................................168
DMA configuration register (DMA_CFG) .....................................................169
DMA control data base pointer register (DMA_CTRL_BASE_PTR) .......................170
DMA channel alternate control data base pointer register
(DMA_ALT_CTRL_BASE_PTR) ..........................................................................170
DMA channel wait on request status register (DMA_WAITONREQ_STATUS) ............171
DMA channel software request register (DMA_CHNL_SW_REQUEST) ...................171

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DMA channel useburst set register (DMA_CHNL_USEBURST_SET) .......................172
DMA channel useburst clear register (DMA_CHNL_USEBURST_CLR) ....................172
DMA channel request mask set register (DMA_CHNL_REQ_MASK_SET) ................173
DMA channel request mask clear register (DMA_CHNL_REQ_MASK_CLR)..............174
DMA channel enable set register (DMA_CHNL_ENABLE_SET) ............................174
DMA channel enable clear register (DMA_CHNL_ENABLE_CLR) .........................175
DMA channel primary-alternate set register (DMA_CHNL_PRI_ALT_SET) ..............175
DMA channel primary-alternate clear register (DMA_CHNL_PRI_ALT _CLR) ..........176
DMA channel priority set register (DMA_CHNL_PRIORITY_SET) .........................176
DMA channel priority clear register (DMA_CHNL_PRIORITY_CLR) ......................177
DMA bus error clear register (DMA_ERR_CLR) ..............................................177
19.5 Register map ...............................................................................179
20Analog-to-digital converter (ADC) ............................................................... 180
20.1 Introduction ................................................................................180
20.2 Features ....................................................................................180
20.3 Functional description ...................................................................181
Operation ADC with non-interrupt ...........................................................181
Operation ADC with interrupt.................................................................183
20.4 Registers (Base address : 0x4100_0000)...............................................183
ADC control register (ADC_CTR)..............................................................183
ADC channel select register (ADC_CHSEL) ..................................................184
ADC start register (ADC_START) ..............................................................185
ADC conversion data register (ADC_DATA) ..................................................185
ADC Interrupt register (ADC_INT) ............................................................185
ADC Interrupt Clear register (ADC_INTCLR) ................................................186
20.5 Register map ...............................................................................187
21Pulse-Width Modulation (PWM)................................................................... 188
21.1 Introduction ................................................................................188
21.2 Features ....................................................................................188
21.3 Functional description ...................................................................189
Timer/Counter control .........................................................................189
Timer/Counter...................................................................................189
PWM mode .......................................................................................193
Interrupt..........................................................................................194
Dead zone generation ..........................................................................195
Capture event ...................................................................................196
How to set the PWM ............................................................................198
21.4 PWM Channel-0 Registers (Base address : 0x4000_5000)...........................198
Channel-0 interrupt register(PWMCH0IR) ...................................................198

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Channel-0 interrupt enable register(PWMCH0IER) ........................................199
Channel-0 interrupt clear register(PWMCH0ICR) ..........................................200
Channel-0 Timer/Counter Register (PWMCH0TCR) ........................................200
Channel-0 Prescale Counter Register (PWMCH0PCR) .....................................201
Channel-0 Prescale Register (PWMCH0PR)..................................................201
Channel-0 Match Register (PWMCH0MR) ....................................................201
Channel-0 Limit Register (PWMCH0LR)......................................................202
Channel-0 Up-Down Mode Register (PWMCH0UDMR)......................................202
Channel-0 Timer/Counter Mode Register (PWMCH0TCMR)...............................203
Channel-0 PWM output Enable and External input Enable Register (PWMCH0PEEER)
203
Channel-0 Capture Mode Register (PWMCH0CMR).........................................204
Channel-0 Capture Register (PWMCH0CR) ..................................................204
Channel-0 Periodic Mode Register (PWMCH0PDMR) .......................................204
Channel-0 Dead Zone Enable Register (PWMCH0DZER)...................................205
Channel-0 Dead Zone Counter Register (PWMCH0DZCR) .................................205
21.5 Register map ...............................................................................206
21.6 PWM Channel-1 Registers (Base address : 0x4000_5100)...........................208
Channel-1 interrupt register(PWMCH1IR) ...................................................208
Channel-1 interrupt enable register(PWMCH1IER) ........................................208
Channel-1 interrupt clear register(PWMCH1ICR) ..........................................209
Channel-1 Timer/Counter Register (PWMCH1TCR) ........................................209
Channel-1 Prescale Counter Register (PWMCH1PCR) .....................................210
Channel-1 Prescale Register (PWMCH1PR) ..................................................210
Channel-1 Match Register (PWMCH1MR) ....................................................211
Channel-1 Limit Register (PWMCH1LR)......................................................211
Channel-1 Up-Down Mode Register (PWMCH1UDMR)......................................212
Channel-1 Timer/Counter Mode Register (PWMCH1TCMR)...............................212
Channel-1 PWM output Enable and External input Enable Register (PWMCH1PEEER)
213
Channel-1 Capture Mode Register (PWMCH1CMR).........................................213
Channel-1 Capture Register (PWMCH1CR) ..................................................213
Channel-1 Periodic Mode Register (PWMCH1PDMR) .......................................214
Channel-1 Dead Zone Enable Register (PWMCH1DZER)...................................214
Channel-1 Dead Zone Counter Register (PWMCH1DZCR) .................................215
21.7 Register map ...............................................................................216
21.8 PWM Channel-2 Registers (Base address : 0x4000_5200)...........................217
Channel-2 interrupt register(PWMCH2IR) ...................................................217
Channel-2 interrupt enable register(PWMCH2IER) ........................................217