Wiznet W7500 User manual

© Copyright 2018 WIZnet Co., Ltd. All rights reserved.
W7500x
Reference Manual
Version 1.1.0
http://www.wiznet.io

W7500x Reference Manual Version1.1.0 2 / 399
1Table of Contents
1Table of Contents....................................................................................... 2
2List of table............................................................................................. 19
3List of figures........................................................................................... 21
4Documentation conventions ........................................................................ 23
4.1 Glossary ...................................................................................... 23
4.2 Register Bit Conventions .................................................................. 25
5System and memory overview ..................................................................... 26
5.1 System architecture ....................................................................... 26
5.2 Memory organization ...................................................................... 27
Introduction ....................................................................................... 27
Memory map ...................................................................................... 28
6System configuration controller (SYSCFG)....................................................... 29
7Interrupt and events ................................................................................. 29
7.1 Nested vectored interrupt controller (NVIC) .......................................... 29
NVIC main features .............................................................................. 29
SysTick calibration value register ............................................................. 29
Interrupt and exception vectors............................................................... 29
7.2 Event ......................................................................................... 30
8Power supply ........................................................................................... 31
8.1 Introduction ................................................................................. 31
8.2 Voltage regulator........................................................................... 31
8.3 Low-power modes.......................................................................... 31
Sleep mode........................................................................................ 32
Peripheral clock gating.......................................................................... 32
9System tick timer ..................................................................................... 33
9.1 Introduction ................................................................................. 33
9.2 Features ..................................................................................... 33
9.3 Functional description .................................................................... 33
9.4 Registers (Base : 0xE000_E000).......................................................... 34
System Timer control and status register (SYST_CSR)..................................... 34
SysTick Reload Value Register (SYST_RVR)................................................... 34
SysTick Current Value Register (SYST_CVR) ................................................. 35
SysTick Calibration Value Register (SYST_CALIB) ........................................... 35
10Booting Sequence ..................................................................................... 36
11Embedded Flash memory............................................................................ 37
11.1 Flash main features........................................................................ 37
11.2 Flash memory organization............................................................... 37

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12Clock Reset generator (CRG)........................................................................ 39
12.1 Introduction ................................................................................. 39
12.2 Features ..................................................................................... 39
Reset....... ........................................................................................ 39
Clock....... ........................................................................................ 40
12.3 Functional description .................................................................... 41
External Oscillator Clock ....................................................................... 41
RC oscillator clock ............................................................................... 42
PLL.................................................................................................. 42
Generated clock.................................................................................. 42
12.4 Registers (Base address : 0x4100_1000)................................................ 44
OSC power down register (OSC_PDR)......................................................... 44
PLL power down register (PLL_PDR) .......................................................... 44
PLL frequency calculating register (PLL_FCR) .............................................. 44
PLL output enable register (PLL_OER) ....................................................... 45
PLL bypass register (PLL_BPR) ................................................................. 45
PLL input clock source select register (PLL_IFSR).......................................... 46
FCLK source select register (FCLK_SSR)...................................................... 46
FCLK prescale value select register (FCLK_PVSR) .......................................... 47
SSPCLK source select register (SSPCLK_SSR) ................................................ 47
SSPCLK prescale value select register (SSPCLK_PVSR) .................................... 48
ADCCLK source select register (ADCCLK_SSR) .............................................. 48
ADCCLK prescale value select register (ADCCLK_PVSR) ................................... 48
TIMER0CLK source select register (TIMER0CLK_SSR)....................................... 49
TIMER0CLK prescale value select register (TIMER0CLK_PVSR) ........................... 49
TIMER1CLK source select register (TIMER1CLK_SSR)....................................... 50
TIMER1CLK prescale value select register (TIMER1CLK_PVSR) ........................... 50
PWM0CLK source select register (PWM0CLK_SSR) .......................................... 51
PWM0CLK prescale value select register (PWM0CLK_PVSR) .............................. 51
PWM1CLK source select register (PWM1CLK_SSR) .......................................... 52
PWM1CLK prescale value select register (PWM1CLK_PVSR) .............................. 52
PWM2CLK source select register (PWM2CLK_SSR) .......................................... 53
PWM2CLK prescale value select register (PWM2CLK_PVSR) .............................. 53
PWM3CLK source select register (PWM3CLK_SSR) .......................................... 54
PWM3CLK prescale value select register (PWM3CLK_PVSR) .............................. 55
PWM4CLK source select register (PWM4CLK_SSR) .......................................... 55
PWM4CLK prescale value select register (PWM4CLK_PVSR) .............................. 56
PWM5CLK source select register (PWM5CLK_SSR) .......................................... 56
PWM5CLK prescale value select register (PWM5CLK_PVSR) .............................. 57

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PWM6CLK source select register (PWM6CLK_SSR) .......................................... 57
PWM6CLK prescale value select register (PWM6CLK_PVSR) .............................. 58
PWM7CLK source select register (PWM7CLK_SSR).......................................... 58
PWM7CLK prescale value select register (PWM7CLK_PVSR) .............................. 59
RTC High Speed source select register (RTC_HS_SSR) ..................................... 59
RTC High Speed prescale value select register (RTC_HS_PVSR) ......................... 60
RTC source select register (RTC_SSR) ........................................................ 60
WDOGCLK High Speed source select register (WDOGCLK_HS_SSR)...................... 61
WDOGCLK High Speed prescale value select register (WDOGCLK_HS_PVSR) .......... 61
WDOGCLK clock source select register (WDOGCLK_SSR).................................. 62
UARTCLK source select register (UARTCLK_SSR) ........................................... 62
UARTCLK prescale value select register (UARTCLK_PVSR)................................ 63
MIICLK enable control register (MIICLK_ECR) ............................................... 63
Monitoring Clock source select register (MONCLK_SSR) ................................... 64
12.5 Register map ................................................................................ 65
13Tcp/ip core Offload Engine (TOE) ..................................................................67
13.1 Introduction ................................................................................. 67
13.2 Features ..................................................................................... 67
13.3 Functional description .................................................................... 68
13.4 TOE Memory map........................................................................... 68
Common register map........................................................................... 70
Socket register map ............................................................................. 70
Memory............................................................................................. 71
13.5 Common register (Base : 0x4600_0000) ................................................ 73
VERSIONR (TOE Version Register).............................................................. 73
TCKCNTR (Ticker Counter Register) .......................................................... 73
IR (Interrupt Register)........................................................................... 74
IMR (Interrupt Mask Register) .................................................................. 74
IRCR (Interrupt Clear Register) ................................................................ 75
SIR (Socket Interrupt Register) ................................................................ 76
SIMR (Socket Interrupt Mask Register)........................................................ 76
MR (Mode Register) .............................................................................. 77
PTIMER (PPP Link Control Protocol Request Timer Register) ............................. 78
PMAGICR (PPP Link Control Protocol Magic number Register) ........................... 78
PHAR (Destination Hardware Address Register in PPPoE) ................................. 78
PSIDR (Session ID Register in PPPoE).......................................................... 79
PMRUR (Maximum Receive Unit Register in PPPoE) ........................................ 80
SHAR (Source Hardware Address Register)................................................... 80
GAR (Gateway Address) ......................................................................... 81

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SUBR ( Subnet Mask Register) .................................................................. 81
SIPR (Source IP address Register) ............................................................. 82
NCONFLR ( Network Configuration Lock Register) ......................................... 82
RTR (Retry Time Register) ...................................................................... 83
RCR (Retry Counter Register) .................................................................. 84
UIPR (Unreachable IP address Register)...................................................... 85
UPORTR (Unreachable Port Register) ......................................................... 86
13.6 Socket register (Base : 0x4601_0000 + 0x0004_000 x n)[n=0,…7, where n is
socket number] ......................................................................................... 86
Sn_MR (Socket n Mode Register)............................................................... 86
Sn_CR (Socket n Command Register) ......................................................... 89
Sn_IR (Socket n Interrupt Register) ........................................................... 91
Sn_IMR (Socket n Interrupt Mask Register) .................................................. 91
Sn_ICR (Socket n Interrupt Clear Register) .................................................. 92
Sn_SR (Socket n Status Register) .............................................................. 93
Sn_PNR (Socket n Protocol Number Register) ............................................... 95
Sn_TOSR (Socket n IP Type of Service Register) ............................................ 96
Sn_TTLR (Socket n TTL Register) .............................................................. 96
Sn_FRAGR (Socket n Fragment offset Register) ............................................ 97
Sn_MSSR (Socket n Maximum Segment Register) ........................................... 97
Sn_PORTR (Socket n Source Port Register) .................................................. 98
Sn_DHAR (Socket n Destination Hardware address Register)............................. 98
Sn_DPORTR (Socket n Destination Port Number Register) ................................ 99
Sn_DIPR (Socket n Destination IP address Register).......................................100
Sn_KATMR (Socket n Keep Alive Timer Register)...........................................101
Sn_RTR (Socket n Retry Time Register) ...................................................101
Sn_RCR (Socket n Retry Counter Register) .................................................102
Sn_TXBUF_SIZE (Socket n TX Buffer Size Register)........................................102
Sn_TX_FSR (Socket n TX Free Size Register) ...............................................103
Sn_TX_RD (Socket n TX Read Pointer Register) ............................................104
Sn_TX_WR (Socket n TX Write Pointer Register)...........................................105
Sn_RXBUF_SIZE (Socket n RX Buffer Size Register)........................................105
Sn_RX_RSR (Socket n RX Received Size Register) .........................................106
Sn_RX_RD (Socket n RX Read Pointer Register) ............................................107
Sn_RX_WR (Socket n RX Write Pointer Register)...........................................108
14Random number generator (RNG) ............................................................... 109
14.1 Introduction ................................................................................109
14.2 Features ....................................................................................109
14.3 Functional description ...................................................................109

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Operation RNG...................................................................................110
14.4 Registers (Base address : 0x4000_7000)...............................................111
RNG run register (RNG_RUN)..................................................................111
RNG SEED register (RNG_SEED) ...............................................................111
RNG clock select register (RNG_CLKSEL) ...................................................111
RNG manual mode select register (RNG_MODE) ...........................................112
RNG random number value register (RNG_RN) ............................................112
RNG polynomial register (RNG_POLY) .......................................................113
14.5 Register map ...............................................................................114
15Alternate Function Controller (AFC) ............................................................ 114
15.1 Introduction ................................................................................114
15.2 Features ....................................................................................114
15.3 Functional description ...................................................................114
15.4 Registers (Base address : 0x4100_2000)...............................................117
PA_00 pad alternate function select register (PA_00_AFR) ..............................117
PA_01 pad alternate function select register (PA_01_AFR) ..............................117
PA_02 pad alternate function select register (PA_02_AFR) ..............................118
PA_03 pad alternate function select register (PA_03_AFR) ..............................118
PA_04 pad alternate function select register (PA_04_AFR) ..............................119
PA_05 pad alternate function select register (PA_05_AFR) ..............................119
PA_06 pad alternate function select register (PA_06_AFR) ..............................120
PA_07 pad alternate function select register (PA_07_AFR) ..............................120
PA_08 pad alternate function select register (PA_08_AFR) ..............................121
PA_09 pad alternate function select register (PA_09_AFR) ..............................121
PA_10 pad alternate function select register (PA_10_AFR) ..............................122
PA_11 pad alternate function select register (PA_11_AFR) ..............................122
PA_12 pad alternate function select register (PA_12_AFR) ..............................123
PA_13 pad alternate function select register (PA_13_AFR) ..............................123
PA_14 pad alternate function select register (PA_14_AFR) ..............................124
PA_15 pad alternate function select register (PA_15_AFR) ..............................124
PB_00 pad alternate function select register (PB_00_AFR) .............................125
PB_01 pad alternate function select register (PB_01_AFR) .............................125
PB_02 pad alternate function select register (PB_02_AFR) .............................126
PB_03 pad alternate function select register (PB_03_AFR) .............................126
PB_04 pad alternate function select register (PB_04_AFR) .............................127
PB_05 pad alternate function select register (PB_05_AFR) .............................127
PB_06 pad alternate function select register (PB_06_AFR) .............................128
PB_07 pad alternate function select register (PB_07_AFR) .............................128
PB_08 pad alternate function select register (PB_08_AFR) .............................129

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PB_09 pad alternate function select register (PB_09_AFR) .............................129
PB_10 pad alternate function select register (PB_10_AFR) .............................130
PB_11 pad alternate function select register (PB_11_AFR) .............................130
PB_12 pad alternate function select register (PB_12_AFR) .............................131
PB_13 pad alternate function select register (PB_13_AFR) .............................131
PB_14 pad alternate function select register (PB_14_AFR) .............................132
PB_15 pad alternate function select register (PB_15_AFR) .............................132
PC_00 pad alternate function select register (PC_00_AFR) .............................133
PC_01 pad alternate function select register (PC_01_AFR) .............................133
PC_02 pad alternate function select register (PC_02_AFR) .............................134
PC_03 pad alternate function select register (PC_03_AFR) .............................134
PC_04 pad alternate function select register (PC_04_AFR) .............................135
PC_05 pad alternate function select register (PC_05_AFR) .............................135
PC_06 pad alternate function select register (PC_06_AFR) .............................136
PC_07 pad alternate function select register (PC_07_AFR) .............................136
PC_08 pad alternate function select register (PC_08_AFR) .............................137
PC_09 pad alternate function select register (PC_09_AFR) .............................137
PC_10 pad alternate function select register (PC_10_AFR) .............................138
PC_11 pad alternate function select register (PC_11_AFR) .............................138
PC_12 pad alternate function select register (PC_12_AFR) .............................139
PC_13 pad alternate function select register (PC_13_AFR) .............................139
PC_14 pad alternate function select register (PC_14_AFR) .............................140
PC_15 pad alternate function select register (PC_15_AFR) .............................140
PD_00 pad alternate function select register (PD_00_AFR) .............................141
PD_01 pad alternate function select register (PD_01_AFR) .............................141
PD_02 pad alternate function select register (PD_02_AFR) .............................142
PD_03 pad alternate function select register (PD_03_AFR) .............................142
PD_04 pad alternate function select register (PD_04_AFR) .............................143
15.5 Register map ...............................................................................144
16External Interrupt (EXTI) .......................................................................... 147
16.1 Introduction ................................................................................147
16.2 Features ....................................................................................147
16.3 Functional description ...................................................................147
16.4 Registers (Base address : 0x4100_2000)...............................................149
External interrupt enable register (Px_y EXTINT).........................................149
16.5 Register map ...............................................................................149
17Pad Controller (PADCON) .......................................................................... 150
17.1 Introduction ................................................................................150
17.2 Features ....................................................................................150

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17.3 Functional description ...................................................................150
17.4 Registers (Base address : 0x4100_3000)...............................................152
PAD Control register (Px_y PCR)(x=A..D, y=0..15) ........................................152
17.5 Register map ...............................................................................152
18General-purpose I/Os(GPIO)....................................................................... 153
18.1 Introduction ................................................................................153
18.2 Features ....................................................................................153
18.3 Functional description ...................................................................153
Masked access ...................................................................................154
18.4 GPIO Registers(Address Base: 0x4200_0000) .........................................156
GPIO Data Register(GPIOx_DATA) (x=A..D) .................................................156
GPIO Output Latch Register(GPIOx_DATAOUT) (x=A..D)..................................156
GPIO Enable Set Register(GPIOx_OUTENSET) (x=A..D) ...................................156
GPIO Enable Clear Register(GPIOx_OUTENCLR) (x=A..D) ................................157
GPIO Interrupt Enable Set Register(GPIOx_ INTENSET) (x=A..D) .......................157
GPIO Interrupt Enable Clear Register(GPIOx_ INTENCLR) (x=A..D).....................158
GPIO Interrupt Type Set Register(GPIOx_ INTTYPESET) (x=A..D) .......................158
GPIO Interrupt Type Clear Register(GPIOx_ INTTYPECLR) (x=A..D) ....................159
GPIO Interrupt Polarity Set Register(GPIOx_ INTPOLSET) (x=A..D).....................159
GPIO Interrupt Polarity Clear Register(GPIOx_ INTPOLCLR) (x=A..D) ..................160
GPIO Interrupt Status/Clear Register(GPIO_ INTSTATUS/INTCLEAR) (x=A..D)........161
GPIO Lower Byte Masked Access Register(GPIOx_ LB_MASKED) (x=A..D)..............161
GPIO Upper Byte Masked Access Register(GPIOx_ UB_MASKED) (x=A..D) .............162
18.5 Register map ...............................................................................163
19Direct memory access controller (DMA)........................................................ 164
19.1 Introduction ................................................................................164
19.2 Features ....................................................................................164
19.3 Functional description ...................................................................164
DMA request mapping ..........................................................................165
DMA arbitration..................................................................................165
DMA cycle types .................................................................................165
19.4 Registers (Base address : 0x4100_4000)...............................................168
DMA status register (DMA_STATUS) ...........................................................168
DMA configuration register (DMA_CFG) .....................................................169
DMA control data base pointer register (DMA_CTRL_BASE_PTR) .......................170
DMA channel alternate control data base pointer register
(DMA_ALT_CTRL_BASE_PTR) ..........................................................................170
DMA channel wait on request status register (DMA_WAITONREQ_STATUS) ............171
DMA channel software request register (DMA_CHNL_SW_REQUEST) ...................171

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DMA channel useburst set register (DMA_CHNL_USEBURST_SET) .......................172
DMA channel useburst clear register (DMA_CHNL_USEBURST_CLR) ....................172
DMA channel request mask set register (DMA_CHNL_REQ_MASK_SET) ................173
DMA channel request mask clear register (DMA_CHNL_REQ_MASK_CLR)..............174
DMA channel enable set register (DMA_CHNL_ENABLE_SET) ............................174
DMA channel enable clear register (DMA_CHNL_ENABLE_CLR) .........................175
DMA channel primary-alternate set register (DMA_CHNL_PRI_ALT_SET) ..............175
DMA channel primary-alternate clear register (DMA_CHNL_PRI_ALT _CLR) ..........176
DMA channel priority set register (DMA_CHNL_PRIORITY_SET) .........................176
DMA channel priority clear register (DMA_CHNL_PRIORITY_CLR) ......................177
DMA bus error clear register (DMA_ERR_CLR) ..............................................177
19.5 Register map ...............................................................................179
20Analog-to-digital converter (ADC) ............................................................... 180
20.1 Introduction ................................................................................180
20.2 Features ....................................................................................180
20.3 Functional description ...................................................................181
Operation ADC with non-interrupt ...........................................................181
Operation ADC with interrupt.................................................................183
20.4 Registers (Base address : 0x4100_0000)...............................................183
ADC control register (ADC_CTR)..............................................................183
ADC channel select register (ADC_CHSEL) ..................................................184
ADC start register (ADC_START) ..............................................................185
ADC conversion data register (ADC_DATA) ..................................................185
ADC Interrupt register (ADC_INT) ............................................................185
ADC Interrupt Clear register (ADC_INTCLR) ................................................186
20.5 Register map ...............................................................................187
21Pulse-Width Modulation (PWM)................................................................... 188
21.1 Introduction ................................................................................188
21.2 Features ....................................................................................188
21.3 Functional description ...................................................................189
Timer/Counter control .........................................................................189
Timer/Counter...................................................................................189
PWM mode .......................................................................................193
Interrupt..........................................................................................194
Dead zone generation ..........................................................................195
Capture event ...................................................................................196
How to set the PWM ............................................................................198
21.4 PWM Channel-0 Registers (Base address : 0x4000_5000)...........................198
Channel-0 interrupt register(PWMCH0IR) ...................................................198

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Channel-0 interrupt enable register(PWMCH0IER) ........................................199
Channel-0 interrupt clear register(PWMCH0ICR) ..........................................200
Channel-0 Timer/Counter Register (PWMCH0TCR) ........................................200
Channel-0 Prescale Counter Register (PWMCH0PCR) .....................................201
Channel-0 Prescale Register (PWMCH0PR)..................................................201
Channel-0 Match Register (PWMCH0MR) ....................................................201
Channel-0 Limit Register (PWMCH0LR)......................................................202
Channel-0 Up-Down Mode Register (PWMCH0UDMR)......................................202
Channel-0 Timer/Counter Mode Register (PWMCH0TCMR)...............................203
Channel-0 PWM output Enable and External input Enable Register (PWMCH0PEEER)
203
Channel-0 Capture Mode Register (PWMCH0CMR).........................................204
Channel-0 Capture Register (PWMCH0CR) ..................................................204
Channel-0 Periodic Mode Register (PWMCH0PDMR) .......................................204
Channel-0 Dead Zone Enable Register (PWMCH0DZER)...................................205
Channel-0 Dead Zone Counter Register (PWMCH0DZCR) .................................205
21.5 Register map ...............................................................................206
21.6 PWM Channel-1 Registers (Base address : 0x4000_5100)...........................208
Channel-1 interrupt register(PWMCH1IR) ...................................................208
Channel-1 interrupt enable register(PWMCH1IER) ........................................208
Channel-1 interrupt clear register(PWMCH1ICR) ..........................................209
Channel-1 Timer/Counter Register (PWMCH1TCR) ........................................209
Channel-1 Prescale Counter Register (PWMCH1PCR) .....................................210
Channel-1 Prescale Register (PWMCH1PR) ..................................................210
Channel-1 Match Register (PWMCH1MR) ....................................................211
Channel-1 Limit Register (PWMCH1LR)......................................................211
Channel-1 Up-Down Mode Register (PWMCH1UDMR)......................................212
Channel-1 Timer/Counter Mode Register (PWMCH1TCMR)...............................212
Channel-1 PWM output Enable and External input Enable Register (PWMCH1PEEER)
213
Channel-1 Capture Mode Register (PWMCH1CMR).........................................213
Channel-1 Capture Register (PWMCH1CR) ..................................................213
Channel-1 Periodic Mode Register (PWMCH1PDMR) .......................................214
Channel-1 Dead Zone Enable Register (PWMCH1DZER)...................................214
Channel-1 Dead Zone Counter Register (PWMCH1DZCR) .................................215
21.7 Register map ...............................................................................216
21.8 PWM Channel-2 Registers (Base address : 0x4000_5200)...........................217
Channel-2 interrupt register(PWMCH2IR) ...................................................217
Channel-2 interrupt enable register(PWMCH2IER) ........................................217

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Channel-2 interrupt clear register(PWMCH2ICR) ..........................................218
Channel-2 Timer/Counter Register (PWMCH2TCR) ........................................218
Channel-2 Prescale Counter Register (PWMCH2PCR) .....................................219
Channel-2 Prescale Register (PWMCH2PR) ..................................................219
Channel-2 Match Register (PWMCH2MR) ....................................................220
Channel-2 Limit Register (PWMCH2LR)......................................................220
Channel-2 Up-Down Mode Register (PWMCH2UDMR)......................................220
Channel-2 Timer/Counter Mode Register (PWMCH2TCMR)...............................221
Channel-2 PWM output Enable and External input Enable Register (PWMCH2PEEER)
221
Channel-2 Capture Mode Register (PWMCH2CMR).........................................222
Channel-2 Capture Register (PWMCH2CR) ..................................................222
Channel-2 Periodic Mode Register (PWMCH2PDMR) .......................................223
Channel-2 Dead Zone Enable Register (PWMCH2DZER)...................................223
Channel-2 Dead Zone Counter Register (PWMCH2DZCR) .................................224
21.9 Register map ...............................................................................225
21.10 PWM Channel-3 Registers (Base address : 0x4000_5300)...........................226
Channel-3 interrupt register(PWMCH3IR) ...................................................226
Channel-3 interrupt enable register(PWMCH3IER) ........................................226
Channel-3 interrupt clear register(PWMCH3ICR) ..........................................227
Channel-3 Timer/Counter Register (PWMCH3TCR) ........................................227
Channel-3 Prescale Counter Register (PWMCH3PCR) .....................................228
Channel-3 Prescale Register (PWMCH3PR) ..................................................228
Channel-3 Match Register (PWMCH3MR) ....................................................229
Channel-3 Limit Register (PWMCH3LR)......................................................229
Channel-3 Up-Down Mode Register (PWMCH3UDMR)......................................230
Channel-3 Timer/Counter Mode Register (PWMCH3TCMR)...............................230
Channel-3 PWM output Enable and External input Enable Register (PWMCH3PEEER)
231
Channel-3 Capture Mode Register (PWMCH3CMR).........................................231
Channel-3 Capture Register (PWMCH3CR) ..................................................231
Channel-3 Periodic Mode Register (PWMCH3PDMR) .......................................232
Channel-3 Dead Zone Enable Register (PWMCH3DZER)...................................232
Channel-3 Dead Zone Counter Register (PWMCH3DZCR) .................................233
21.11 Register map ...............................................................................234
21.12 PWM Channel-4 Registers (Base address : 0x4000_5400)...........................235
Channel-4 interrupt register(PWMCH4IR) ...................................................235
Channel-4 interrupt enable register(PWMCH4IER) ........................................235
Channel-4 interrupt clear register(PWMCH4ICR) ..........................................236

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Channel-4 Timer/Counter Register (PWMCH4TCR) ........................................236
Channel-4 Prescale Counter Register (PWMCH4PCR) .....................................237
Channel-4 Prescale Register (PWMCH4PR)..................................................237
Channel-4 Match Register (PWMCH4MR) ....................................................238
Channel-4 Limit Register (PWMCH4LR)......................................................238
Channel-4 Up-Down Mode Register (PWMCH4UDMR)......................................238
Channel-4 Timer/Counter Mode Register (PWMCH4TCMR)...............................239
Channel-4 PWM output Enable and External input Enable Register (PWMCH4PEEER)
239
Channel-4 Capture Mode Register (PWMCH4CMR).........................................240
Channel-4 Capture Register (PWMCH4CR) ..................................................240
Channel-4 Periodic Mode Register (PWMCH4PDMR) .......................................241
Channel-4 Dead Zone Enable Register (PWMCH4DZER)...................................241
Channel-4 Dead Zone Counter Register (PWMCH4DZCR) .................................242
21.13 Register map ...............................................................................243
21.14 PWM Channel-5 Registers (Base address : 0x4000_5500)...........................244
Channel-5 interrupt register(PWMCH5IR) ...................................................244
Channel-5 interrupt enable register(PWMCH5IER) ........................................244
Channel-5 interrupt clear register(PWMCH5ICR) ..........................................245
Channel-5 Timer/Counter Register (PWMCH5TCR) ........................................245
Channel-5 Prescale Counter Register (PWMCH5PCR) .....................................246
Channel-5 Prescale Register (PWMCH5PR) ..................................................246
Channel-5 Match Register (PWMCH5MR) ....................................................247
Channel-5 Limit Register (PWMCH5LR)......................................................247
Channel-5 Up-Down Mode Register (PWMCH5UDMR)......................................247
Channel-5 Timer/Counter Mode Register (PWMCH5TCMR)...............................248
Channel-5 PWM output Enable and External input Enable Register (PWMCH5PEEER)
248
Channel-5 Capture Mode Register (PWMCH5CMR).........................................249
Channel-5 Capture Register (PWMCH5CR) ..................................................249
Channel-5 Periodic Mode Register (PWMCH5PDMR) .......................................250
Channel-5 Dead Zone Enable Register (PWMCH5DZER)...................................250
Channel-5 Dead Zone Counter Register (PWMCH5DZCR) .................................251
21.15 Register map ...............................................................................252
21.16 PWM Channel-6 Registers (Base address : 0x4000_5600)...........................253
Channel-6 interrupt register(PWMCH6IR)...................................................253
Channel-6 interrupt enable register(PWMCH6IER) ........................................253
Channel-6 interrupt clear register(PWMCH6ICR) ..........................................254
Channel-6 Timer/Counter Register (PWMCH6TCR) ........................................254

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Channel-6 Prescale Counter Register (PWMCH6PCR) .....................................255
Channel-6 Prescale Register (PWMCH6PR) ..................................................255
Channel-6 Match Register (PWMCH6MR) ....................................................256
Channel-6 Limit Register (PWMCH6LR)......................................................256
Channel-6 Up-Down Mode Register (PWMCH6UDMR)......................................257
Channel-6 Timer/Counter Mode Register (PWMCH6TCMR)...............................257
Channel-6 PWM output Enable and External input Enable Register (PWMCH6PEEER)
258
Channel-6 Capture Mode Register (PWMCH6CMR).........................................258
Channel-6 Capture Register (PWMCH6CR) ..................................................258
Channel-6 Periodic Mode Register (PWMCH6PDMR) .......................................259
Channel-6 Dead Zone Enable Register (PWMCH6DZER)...................................259
Channel-6 Dead Zone Counter Register (PWMCH6DZCR) .................................260
21.17 Register map ...............................................................................261
21.18 PWM Channel-7 Registers (Base address : 0x4000_5700)...........................262
Channel-7 interrupt register(PWMCH7IR) ...................................................262
Channel-7 interrupt enable register(PWMCH7IER) ........................................262
Channel-7 interrupt clear register(PWMCH7ICR) ..........................................263
Channel-7 Timer/Counter Register (PWMCH7TCR) ........................................263
Channel-7 Prescale Counter Register (PWMCH7PCR) .....................................264
Channel-7 Prescale Register (PWMCH7PR) ..................................................264
Channel-7 Match Register (PWMCH7MR) ....................................................265
Channel-7 Limit Register (PWMCH7LR)......................................................265
Channel-7 Up-Down Mode Register (PWMCH7UDMR)......................................266
Channel-7 Timer/Counter Mode Register (PWMCH7TCMR)...............................266
Channel-7 PWM output Enable and External input Enable Register (PWMCH7PEEER)
267
Channel-7 Capture Mode Register (PWMCH7CMR).........................................267
Channel-7 Capture Register (PWMCH7CR) ..................................................267
Channel-7 Periodic Mode Register (PWMCH7PDMR) .......................................268
Channel-7 Dead Zone Enable Register (PWMCH7DZER)...................................268
Channel-7 Dead Zone Counter Register (PWMCH7DZCR) .................................269
21.19 Register map ...............................................................................270
21.20 PWM Common Registers (Base address : 0x4000_5800) ............................271
Interrupt Enable Register (IER) ...............................................................271
Start/Stop Register (SSR) ......................................................................272
Pause Register (PSR) ............................................................................273
21.21 Register map ...............................................................................274
22Dual timers ........................................................................................... 275

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22.1 Introduction ................................................................................275
22.2 Features ....................................................................................275
22.3 Functional description ...................................................................276
Clock and clock enable ........................................................................276
Timer size.... ....................................................................................276
Prescaler.... ......................................................................................276
Repetition mode.................................................................................276
Interrupt..........................................................................................277
Operation.........................................................................................277
How to set the dual timers ....................................................................278
22.4 Dual timer0_0 Registers (Base address : 0x4000_1000) ............................279
Timer0_0 Load Register(DUALTIMER0_0TimerLoad).......................................279
Timer0_0 Value Register(DUALTIMER0_0TimerValue) .....................................279
Timer0_0 Control Register(DUALTIMER0_0TimerControl) ................................279
Timer0_0 Interrupt Clear Register (DUALTIMER0_0TimerIntClr) ........................280
Timer0_0 Raw Interrupt Status Register (DUALTIMER0_0TimerRIS) ....................280
Timer0_0 Masked Interrupt Status Register (DUALTIMER0_0TimerMIS) ................281
Timer0_0 Background Load Register (DUALTIMER0_0TimerBGLoad) ...................281
22.5 Register map ...............................................................................283
22.6 Dual timer0_1 Registers (Base address : 0x4000_1020) ............................284
Timer0_1 Load Register(DUALTIMER0_1TimerLoad).......................................284
Timer0_1 Value Register(DUALTIMER0_1TimerValue) .....................................284
Timer0_1 Control Register(DUALTIMER0_1TimerControl) ................................284
Timer0_1 Interrupt Clear Register (DUALTIMER0_1TimerIntClr) ........................285
Timer0_1 Raw Interrupt Status Register (DUALTIMER0_1TimerRIS) ....................285
Timer0_1 Masked Interrupt Status Register (DUALTIMER0_1TimerMIS) ................286
Timer0_1 Background Load Register (DUALTIMER0_1TimerBGLoad) ...................286
22.7 Register map ...............................................................................288
22.8 Dual Timer 0 Clock Enable Register (Base address : 0x4000_1080) ..............289
Timer0_0 Clock Enable Register (TIMCLKEN0_0) ..........................................289
Timer0_1 Clock Enable Register (TIMCLKEN0_1) ..........................................289
22.9 Register map ...............................................................................290
22.10 Dual timer1_0 Registers (Base address : 0x4000_2000) ............................291
Timer1_0 Load Register(DUALTIMER1_0TimerLoad).......................................291
Timer1_0 Value Register(DUALTIMER1_0TimerValue) .....................................291
Timer1_0 Control Register(DUALTIMER1_0TimerControl) ................................291
Timer1_0 Interrupt Clear Register (DUALTIMER1_0TimerIntClr) ........................292
Timer1_0 Raw Interrupt Status Register (DUALTIMER1_0TimerRIS) ....................292
Timer1_0 Masked Interrupt Status Register (DUALTIMER1_0TimerMIS) ................293

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Timer1_0 Background Load Register (DUALTIMER1_0TimerBGLoad) ...................293
22.11 Register map ...............................................................................295
22.12 Dual timer1_1 Registers (Base address : 0x4000_2020) ............................296
Timer1_1 Load Register(DUALTIMER1_1TimerLoad).......................................296
Timer1_1 Value Register(DUALTIMER1_1TimerValue) .....................................296
Timer1_1 Control Register(DUALTIMER1_1TimerControl) ................................296
Timer1_1 Interrupt Clear Register (DUALTIMER1_1TimerIntClr) ........................297
Timer1_1 Raw Interrupt Status Register (DUALTIMER1_1TimerRIS) ....................297
Timer1_1 Masked Interrupt Status Register (DUALTIMER1_1TimerMIS) ................298
Timer1_1 Background Load Register (DUALTIMER1_1TimerBGLoad) ...................298
22.13 Register map ...............................................................................300
22.14 Dual Timer 1 Clock Enable Register (Base address : 0x4000_2080) ..............301
Timer1_0 Clock Enable Register (TIMCLKEN1_0) ..........................................301
Timer1_1 Clock Enable Register (TIMCLKEN1_1) ..........................................301
22.15 Register map ...............................................................................302
23Watchdog timer...................................................................................... 302
23.1 Introduction ................................................................................302
23.2 Features ....................................................................................302
23.3 Functional description ...................................................................302
Clock........ ......................................................................................302
Interrupt and reset request ...................................................................303
23.4 Watchdog timer Registers (Base address : 0x4000_0000) ..........................303
Watchdog timer Load Register(WDTLoad) ..................................................303
Watchdog timer Value Register(WDTValue) ................................................304
Watchdog timer Control Register(WDTControl)............................................304
Watchdog timer Interrupt Clear Register (WDTIntClr)....................................304
Watchdog timer Raw Interrupt Status Register (WDTRIS)................................305
Watchdog timer Masked Interrupt Status Register (WDTMIS) ...........................305
Watchdog timer Lock Register(WDTLock)...................................................306
23.5 Register map ...............................................................................307
24Real-time Clock(RTC) ............................................................................... 307
24.1 Introduction ................................................................................307
24.2 Features ....................................................................................307
24.3 Functional description ...................................................................307
RTC clock.... .....................................................................................308
RTC interrupt ....................................................................................308
RTC Counter and Calendar ....................................................................308
RTC Setting flow ................................................................................309
24.4 RTC Registers (Base Address : 0x4000_E000) .........................................310

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RTC control register (RTCCON) ...............................................................310
RTC Interrupt Mask register (RTCINTE)......................................................311
RTC Interrupt Pending register (RTCINTP) ..................................................313
RTC Alarm Mask register (RTCAMR) ..........................................................314
RTC BCD Second register (BCDSEC) ..........................................................315
RTC BCD Minute register (BCDMIN)...........................................................315
RTC BCD Hour register (BCDHOUR) ..........................................................315
RTC BCD Day register (BCDDAY) ..............................................................316
RTC BCD Date register (BCDDATE) ...........................................................316
RTC BCD Month register (BCDMON) ..........................................................316
RTC BCD Year register (BCDYEAR) ............................................................317
RTC Predetermining Second register (PRESEC) ............................................317
RTC Predetermining Minute register (PREMIN).............................................317
RTC Predetermining Hour register (PREHOUR).............................................318
RTC Predetermining Day register (PREDAY) ................................................318
RTC Predetermining Date register (PREDATE)..............................................318
RTC Predetermining Month register (PREMON) ............................................319
RTC Predetermining Year register (PREYEAR) ..............................................319
RTC Consolidated Time0 register (RTCTIME0)..............................................319
RTC Consolidated Time1 register (RTCTIME1)..............................................320
24.5 Register map ...............................................................................321
25UART(Universal Asynchronous Receive Transmit)............................................ 322
25.1 Introduction ................................................................................322
25.2 Features ....................................................................................322
25.3 Functional description ...................................................................323
Baud rate calculation ..........................................................................325
Data transmission ...............................................................................326
Data receive .....................................................................................326
Hardware flow control .........................................................................327
25.4 UART0 Registers(Base address: 0x4000_C000) .......................................328
UART0DR (UART0 Data Register) .............................................................328
UART0RSR/ECR (UART0 Receive Status Register/Error Clear Register)................329
UART0FR (UART0 Flag Register) ..............................................................330
UART0ILPR (UART0 IrDA Low-Power Counter Register) ...................................331
UART0IBRD (UART0 Integer Baud Rate Register) ..........................................332
UART0FBRD (UART0 Fractional Baud Rate Register) ......................................332
UART0LCR_H (UART0 Line Control Register) ...............................................333
UART0CR (UART0 Control register) ..........................................................334
UART0IFLS (UART0 Interrupt FIFO Level Select Register) ................................336

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UART0IMSC (UART0 Interrupt Mask Set/Clear Register) ..................................336
UART0RIS (UART0 Raw Interrupt Status Register) .........................................338
UART0MIS (UART0 Masked Interrupt Status Register) .....................................339
UART0ICR (UART0 Interrupt Clear Register) ................................................340
25.5 Register map ...............................................................................341
25.6 UART1 Registers(Base address: 0x4000_D000) .......................................342
UART1DR (UART1 Data Register) .............................................................342
UART1RSR/ECR (UART1 Receive Status Register/Error Clear Register)................342
UART1FR (UART1 Flag Register) ..............................................................343
UART1ILPR (UART1 IrDA Low-Power Counter Register) ...................................344
UART1IBRD (UART1 Integer Baud Rate Register) ..........................................345
UART1FBRD (UART1 Fractional Baud Rate Register) ......................................345
UART1LCR_H (UART1 Line Control Register) ...............................................346
UART1CR (UART1 Control register) ..........................................................347
UART1IFLS (UART1 Interrupt FIFO Level Select Register) ................................349
UART1IMSC (UART1 Interrupt Mask Set/Clear Register) ..................................349
UART1RIS (UART1 Raw Interrupt Status Register) .........................................351
UART1MIS (UART1 Masked Interrupt Status Register) .....................................352
UART1ICR (UART1 Interrupt Clear Register) ................................................353
25.7 Register map ...............................................................................354
26Universal Asynchronous Receive Transmit(UART2) .......................................... 355
26.1 Introduction ................................................................................355
26.2 Feature......................................................................................355
26.3 Functional description ...................................................................355
Baud rate calculation ..........................................................................355
26.4 UART2 Registers(Base address: 0x4000_6000) .......................................357
UART2DR (UART2 Data Register) .............................................................357
UART2SR (UART2 Status Register) ............................................................357
UART2CR (UART2 Control Register) ..........................................................358
UART2ISR/ICR (UART2 Interrupt Status/Interrupt Clear Register) .....................358
UART2BDR (UART2 Baud Rate Divider Register) ...........................................359
26.5 Register map ...............................................................................360
27Synchronous Serial Port (SSP) .................................................................... 361
27.1 Introduction ................................................................................361
27.2 Features ....................................................................................361
27.3 Functional description ...................................................................362
Clock prescaler ..................................................................................362
Transmit FIFO ....................................................................................362
Receive FIFO .....................................................................................363

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Interrupt generation logic .....................................................................363
DMA interface....................................................................................363
Interface reset...................................................................................365
Configuring the SSP .............................................................................365
Enable PrimeCell SSP operation ..............................................................366
Clock ratios ......................................................................................366
Programming the SSPCR0 Control Register .................................................367
Programming the SSPCR1 Control Register .................................................367
Frame format ....................................................................................368
Texas Instruments synchronous serial frame format......................................369
Motorola SPI frame format ....................................................................370
National Semiconductor Microwire frame format .........................................376
Master and Slave configurations..............................................................378
SSP Flow chart ...................................................................................379
27.4 SSP0 Registers (Base Address : 0x4000_A000) ........................................380
SSP0 Control register 0 (SSP0CR0) ...........................................................380
SSP0 Control register 1 (SSP0CR1) ...........................................................382
SSP0 Data register (SSP0DR)...................................................................382
SSP0 Status register (SSP0SR) .................................................................383
SSP0 Clock prescale register (SSP0CPSR) ...................................................384
SSP0 Interrupt mask set or clear register (SSP0IMSC) ....................................384
SSP0 Raw interrupt status register (SSP0RIS) ..............................................385
SSP0 Masked interrupt status register, (SSP0MIS)..........................................385
SSP0 Interrupt clear register (SSP0ICR) .....................................................386
SSP0 DMA control register, (SSP0DMACR) ...................................................386
27.5 Register map ...............................................................................388
27.6 SSP1 Registers (Base Address : 0x4000_B000) ........................................389
SSP1 Control register 0 (SSP1CR0) ...........................................................389
SSP1 Control register 1 (SSP1CR1) ...........................................................390
SSP1 Data register (SSP1DR)...................................................................392
SSP1 Status register (SSP1SR) .................................................................392
SSP1 Clock prescale register (SSP1CPSR) ...................................................393
SSP1 Interrupt mask set or clear register (SSP1IMSC) ....................................393
SSP1 Raw interrupt status register (SSP1RIS) ..............................................394
SSP1 Masked interrupt status register, (SSP1MIS)..........................................394
SSP1 Interrupt clear register (SSP1ICR) .....................................................395
SSP1 DMA control register, (SSP1DMACR) ...................................................395
27.7 Register map ...............................................................................397
Document History Information....................................................................... 398

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2List of table
Table 1 W7500x interrupt vector table ....................................................... 29
Table 2 W7500x sleep mode summary ........................................................ 32
Table 3 operation of mode selection .......................................................... 36
Table 4 description of Flash memory.......................................................... 37
Table 5 CRG register map and reset values .................................................. 67
Table 6. Offset Address for Common Register ............................................... 70
Table 7. Offset Address in Socket n Register Block ......................................... 71
Table 8 RNG register map and reset values ............................................... 114
Table 9 functional description table .........................................................114
Table 10 AFC register map and reset values ................................................144
Table 11 EXTINT register map and reset values ............................................149
Table 12 PAD controller register map and reset values ...................................152
Table 13 GPIO register map and reset values ...............................................163
Table 14 Summary of the DMA requests for each channel ................................165
Table 15 DMA register map and reset values................................................179
Table 16 ADC register map and reset values ................................................187
Table 17 PWM channel 0 register map and reset values ..................................207
Table 18 PWM channel 1 register map and reset values ..................................216
Table 19 PWM channel 2 register map and reset values ..................................225
Table 20 PWM channel 3 register map and reset values ..................................234
Table 21 PWM channel 4 register map and reset values ..................................243
Table 22 PWM channel 5 register map and reset values ..................................252
Table 23 PWM channel 6 register map and reset values ..................................261
Table 24 PWM channel 7 register map and reset values ..................................270
Table 25 PWM common register map and reset values....................................274
Table 26 Dual timer 0_0 register map and reset values ..................................283
Table 27 Dual timer 0_1 register map and reset values ..................................288
Table 28 Dual timer 0 clock enable register map and reset values .....................290
Table 29 Dual timer 1_0 register map and reset values ..................................295
Table 30 Dual timer 1_1 register map and reset values ..................................300
Table 31 Dual timer 1 clock enable register map and reset values .....................302
Table 32 Watchdog Timer register map and reset values.................................307
Table 33 RTC register map and reset values ................................................ 321
Table 34 UART0 register map and reset values .............................................341
Table 35 UART1 register map and reset values .............................................354
Table 36 UART2 register map and reset values .............................................360
Table 37 DMA trigger points for the transmit and receive FIFOs. ....................... 364

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Table 38 SSP0 register map and reset values ...............................................388
Table 39 SSP1 register map and reset values ...............................................397