Wolfson WM8804 User manual

w WM8804
1:1 Digital Interface Transceiver with PLL
WOLFSON MICROELECTRONICS plc
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Production Data, September 2007, Rev 4.1
Copyright ©2007 Wolfson Microelectronics plc
DESCRIPTION
The WM8804 is a high performance consumer mode
S/PDIF transceiver with support for 1 received channel and
1 transmitted channel.
A crystal derived, or externally provided high quality master
clock is used to allow low jitter recovery of S/PDIF supplied
master clocks.
Generation of all typically used audio clocks is possible
using the high performance internal PLL. A dedicated
CLKOUT pin provides a high drive clock output.
A pass through option is provided which allows the device
simply to be used to clean up (de-jitter) the received digital
audio signals.
The device may be used under software control or stand
alone hardware control modes. In software control mode,
both 2-wire with read back and 3-wire interface modes are
supported.
Status and error monitoring is built-in and results can be
read back over the control interface, on the GPO pins or
streamed over the audio data interface in ‘With Flags’ mode
(audio data with status flags appended).
The audio data interface supports I2S, left justified, right
justified and DSP audio formats of 16-24 bit word length,
with sample rates from 32 to 192ks/s.
The device is supplied in a 20-lead Pb-free SSOP package.
FEATURES
•S/PDIF (IEC60958-3) compliant.
•Advanced jitter attenuating PLL with low intrinsic period
jitter of 50 ps RMS.
•S/PDIF recovered clock using PLL, or stand alone crystal
derived clock generation.
•Supports 10 – 27MHz crystal clock frequencies.
•2-wire / 3-Wire serial or hardware control interface.
•Programmable audio data interface modes:
- I2S, Left, Right Justified or DSP
- 16/20/24 bit word lengths
•1 channel receiver input and 1 channel transmit output.
•Auto frequency detection / synchronisation.
•Selectable output status data bits.
•Up to 3 configurable GPO pins.
•De-emphasis flag output.
•Non-audio detection including DOLBYTM and DTSTM.
•Channel status changed flag.
•Configurable clock distribution with selectable output
MCLK rate of 512fs, 256fs, 128fs and 64fs.
•2.7 to 3.6V digital and PLL supply voltages.
•20-lead SSOP package.
APPLICATIONS
•AV processors and Hi-Fi systems
•Music industry applications
•DVD-P/DVD-RW
•Digital TV
BLOCK DIAGRAM

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TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1
FEATURES.............................................................................................................1
APPLICATIONS .....................................................................................................1
BLOCK DIAGRAM .................................................................................................1
TABLE OF CONTENTS .........................................................................................2
PIN CONFIGURATION...........................................................................................3
ORDERING INFORMATION ..................................................................................3
PIN DESCRIPTION ................................................................................................4
ABSOLUTE MAXIMUM RATINGS.........................................................................5
RECOMMENDED OPERATING CONDITIONS .....................................................6
SUPPLY CURRENT ...................................................................................................... 6
ELECTRICAL CHARACTERISTICS ......................................................................6
MASTER CLOCK TIMING............................................................................................. 7
MASTER CLOCK TIMING............................................................................................. 7
DIGITAL AUDIO INTERFACE – MASTER MODE......................................................... 7
DIGITAL AUDIO INTERFACE – SLAVE MODE ............................................................ 8
CONTROL INTERFACE – 3-WIRE MODE.................................................................... 9
CONTROL INTERFACE – 2-WIRE MODE.................................................................. 10
DEVICE DESCRIPTION.......................................................................................11
INTRODUCTION......................................................................................................... 11
POWER UP CONFIGURATION .................................................................................. 12
CONTROL INTERFACE OPERATION........................................................................ 14
HARDWARE CONTROL MODE.................................................................................. 18
DIGITAL ROUTING CONTROL................................................................................... 20
MASTER CLOCK AND PHASE LOCKED LOOP......................................................... 21
SOFTWARE MODE INTERNAL CLOCKING .............................................................. 21
HARDWARE MODE INTERNAL CLOCKING.............................................................. 30
S/PDIF TRANSMITTER............................................................................................... 31
S/PDIF RECEIVER...................................................................................................... 34
GENERAL PURPOSE OUTPUT (GPO) CONFIGURATION ....................................... 43
DIGITAL AUDIO INTERFACE ..................................................................................... 44
AUDIO DATA FORMATS ............................................................................................ 45
REGISTER MAP ......................................................................................................... 52
APPLICATIONS INFORMATION .........................................................................63
RECOMMENDED EXTERNAL COMPONENTS.......................................................... 63
PACKAGE DIMENSIONS ....................................................................................65
IMPORTANT NOTICE ..........................................................................................66
ADDRESS: .................................................................................................................. 66

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PIN CONFIGURATION
( Top View )
ORDERING INFORMATION
DEVICE TEMPERATURE
RANGE PACKAGE MOISTURE SENSITIVITY LEVEL
PEAK SOLDERING
TEMPERATURE
WM8804GEDS -25 to +85oC 20-lead SSOP
(Pb-free) MSL1 260oC
WM8804GEDS/R -25 to +85oC 20-lead SSOP
(Pb-free, tape and reel) MSL1 260oC
Note:
Reel quantity = 2,000

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PIN DESCRIPTION
PIN NAME TYPE DESCRIPTION
1 SCLK Digital In/Out Control interface clock / GPO in hardware control mode. See note 2.
2 GPO0 / SWIFMODE Digital In/Out General purpose digital output or selected functionality at hardware reset.
See note 2.
3 SDIN / HWMODE Digital Input Control interface data input and hardware/software mode select at hardware
reset. See note 2.
4 SDOUT / GPO2 Digital In/Out Control interface data output in 3-wire software control mode/ GPO in
hardware control mode or 2-wire software control mode. See note 2.
5 CSB / GPO1 Digital In/Out Chip select / GPO in hardware control mode or 2-wire software control
Mode. See note 2
6 RESETB Digital Input System reset (active low)
7 PVDD Supply PLL core supply
8 PGND Supply PLL ground
9 CLKOUT Digital Out High drive clock output at 64fs, 128fs, 256fs and 512fs
10 XOP Digital Output Crystal output
11 XIN Digital Input Crystal input
12 DOUT Digital Out Audio interface data output
13 DIN Digital In Audio interface data input
14 BCLK Digital In/Out Audio interface bit clock
15 LRCLK Digital In/Out Audio interface left/right word clock
16 MCLK Digital In/Out Master clock input or output
17 TX0 Digital Out S/PDIF transmit channel
18 DGND Supply Digital ground
19 DVDD Supply Digital core supply
20 RX0 Digital In S/PDIF receive channel
Notes:
1. Digital input pins have Schmitt trigger input buffers.
2. Refer to Table 6 Device Configuration at Power up or Hardware Reset

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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION MIN MAX
Digital core and I/O buffer supply voltage -0.3V +5V
PLL supply voltage -0.3V +5V
Voltage range digital inputs DGND -0.3V DVDD +0.3V
Master Clock Frequency 37MHz
Operating temperature range, TA-25°C +85°C
Storage temperature -65°C +150°C
Note:
1. PLL and digital supplies must always be within 0.3V of each other.
2. PLL and digital grounds must always be within 0.3V of each other.

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RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Digital supply range DVDD 2.7 3.6 V
Ground DGND 0 V
PLL supply range PVDD 2.7 3.6 V
Ground PGND 0 V
Notes:
1. PLL and digital supplies must always be within 0.3V of each other.
2. PLL and digital grounds must always be within 0.3V of each other.
SUPPLY CURRENT
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Digital supply current IDVDD DVDD = 3.3V 14.9 mA
PLL supply current IPVDD PVDD = 3.3V 1.7 mA
Power Consumption DVDD/PVDD = 3.3V 54.8 mW
Standby Power
Consumption
DVDD/PVDD = 3.3V
Device powered down
0.11 mW
ELECTRICAL CHARACTERISTICS
Test Conditions
PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Jitter Characteristics
Intrinsic Period Jitter Ji50 ps
Digital Logic Levels (CMOS Levels)
Input LOW level VIL 0.3 x DVDD V
Input HIGH level VIH 0.7 x DVDD V
Output LOW VOL 0.1 x DVDD V
Output HIGH VOH 0.9 x DVDD V
Isource 25 mA
CLOCKOUT buffer drive
capability Isink
CMOS
20pF load 25 mA
S/PDIF Receiver Characteristics
Input Resistance 23 kΩ

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MASTER CLOCK TIMING
MCLK
t
MCLKL
t
MCLKH
t
MCLKY
Figure 1 Slave Mode MCLK Timing Requirements
Test Conditions
PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
System Clock Timing Information – Slave Mode
MCLK System clock cycle time tMCLKY 27 ns
MCLK System clock pulse width high tMCLKH 11 ns
MCLK System clock pulse width low tMLCKL 11 ns
MCLK Duty cycle 40:60 60:40 %
Table 1 Master Clock Timing Requirements
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
DOUT
LRCLK
t
DL
DIN
t
DDA
t
DHT
t
DST
Figure 2 Digital Audio Data Timing – Master Mode
Test Conditions
PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Audio Data Input Timing Information
LRCLK propagation delay from
BCLK falling edge
tDL 0 10 ns
DOUT propagation delay from
BCLK falling edge
tDDA 0 10 ns
DIN setup time to BCLK rising
edge
tDST 10 ns
DIN hold time from BCLK rising
edge
tDHT 10 ns
Table 2 Digital Audio Data Timing – Master Mode

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DIGITAL AUDIO INTERFACE – SLAVE MODE
BCLK
LRCLK
t
BCH
t
BCL
t
BCY
DIN
DOUT
t
LRSU
t
DS
t
LRH
t
DH
t
DD
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Audio Data Input Timing Information
BCLK cycle time tBCY 50 ns
BCLK pulse width high tBCH 20 ns
BCLK pulse width low tBCL 20 ns
LRCLK set-up time to BCLK
rising edge
tLRSU 10 ns
LRCLK hold time from
BCLK rising edge
tLRH 10 ns
DIN set-up time to BCLK
rising edge
tDS 10 ns
DIN hold time from BCLK
rising edge
tDH 10 ns
DOUT propagation delay
from BCLK falling edge
tDD 0 10 ns
Table 3 Digital Audio Data Timing – Slave Mode

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CONTROL INTERFACE – 3-WIRE MODE
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless stated.
PARAMETER SYMBOL MIN TYP MAX UNIT
Program Register Input Information
SCLK rising edge to CSB rising edge tSCS 60 ns
SCLK cycle time tSCY 80 ns
SCLK duty cycle 40/60 60/40 %
SDIN to SCLK set-up time tDSU 20 ns
SDIN hold time from SCLK rising edge tDHO 20 ns
SDOUT propagation delay from SCLK rising edge tDL 5 ns
CSB pulse width high tCSH 20 ns
CSB rising/falling to SCLK rising tCSS 20 ns
SCLK glitch suppression tps 2 8 ns
Table 4 Control Interface Timing – 3-Wire Serial Control Mode

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CONTROL INTERFACE – 2-WIRE MODE
SDIN
SCLK
t
STHO
t
SCY
t
DSU
t
STSU
t
STHO
t
STOP
t
DH
Figure 5 Control Interface Timing – 2-Wire Serial Control Mode
Test Conditions
PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless stated.
PARAMETER SYMBOL MIN TYP MAX UNIT
Program Register Input Information
SCLK cycle time tSCY 2500 ns
SCLK duty cycle 40/60 60/40 %
SCLK frequency 400 kHz
Hold Time (Start Condition) tSTHO 600 ns
Setup Time (Start Condition) tSTSU 600 ns
Data Setup Time tDSU 100 ns
SDIN, SCLK Rise Time 300 ns
SDIN, SCLK Fall Time 300 ns
Setup Time (Stop Condition) tSTOP 600 ns
Data Hold Time tDH 900 ns
SCLK glitch suppression tps 2 8 ns
Table 5 Control Interface Timing – 2-Wire Serial Control Mode