Xilinx Kria K26 SOM Guide
Table of Contents
Revision History...............................................................................................................2
Chapter 1: Introduction.............................................................................................. 5
Chapter 2: Electrical Design Considerations................................................... 7
SOM Connector Overview.......................................................................................................... 7
Signal Naming Conventions.......................................................................................................7
SOM240_1 Connector Pinout..................................................................................................... 8
SOM240_2 Connector Pinout................................................................................................... 17
Supported I/O Standards......................................................................................................... 25
Signal Routing Guidelines........................................................................................................ 25
SOM Configuration and Control Signals................................................................................ 28
SOM MIO Design Considerations............................................................................................32
SOM Power.................................................................................................................................34
Chapter 3: Mechanical Design Considerations............................................ 37
Mechanical Dimensions............................................................................................................37
PCB Fabrication and Assembly House Requirements.......................................................... 39
SOM to Carrier Card Samtec Connector Placement Guidelines..........................................40
Carrier Card Board to Board Connector Placement Guideline............................................41
Recommended Pb-free Reflow Soldering Profile..................................................................47
Carrier Card to SOM Standoff Press-fit Process.................................................................... 49
Board to Board Assembly Guidelines..................................................................................... 50
Mating: JSOM Standoff-nut Tighten Sequence and Torque Setup......................................52
De-mating: JSOM Standoff-nut and Jack Screw Untighten Sequence ............................... 53
SOM System B2B Connector Assembly Validation-DOE (To Ensure Time 0 No Crack).....54
Chapter 4: Hardware Configuration Using Vivado Tools........................55
Vivado Tools Board File.............................................................................................................55
Vivado Software SOM Connector Abstraction....................................................................... 56
SOM Vivado Tools XDC Files.....................................................................................................56
Appendix A: Additional Resources and Legal Notices............................. 57
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Xilinx Resources.........................................................................................................................57
Documentation Navigator and Design Hubs.........................................................................57
References..................................................................................................................................57
Please Read: Important Legal Notices................................................................................... 58
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Chapter 1
Introduction
The purpose of this design guide is to support hardware, system, and rmware engineers
implemenng a product using a Xilinx® Kria™ SOM. The guide outlines electrical, mechanical,
rmware, and power-on conguraon design consideraons that must be addressed as part of
designing a Xilinx SOM compable carrier card. The document is not intended to be self-
contained, meaning that there are references to other Xilinx product documentaon to help the
reader nd more detailed technical informaon available in corresponding technical reference
manuals, soware design guides, and thermal design guides. The Kria K26 SOM is used an
example throughout the guide and is shown in the following block diagram.
Chapter 1: Introduction
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Figure 1: K26 SOM Block Diagram
Block RAM
(slave)
2-way Cache
Coherent Master
APU
MPCore
M
To all output
ports
CCI
Coherency
And Bypass
RPU
GIC
TCMs OCM
Switch
USB0 w/DMA
USB1 w/DMA
LPD DMA
PS SysMon eFUSE
LPD SLCRs
IPI
LPD Units
RTC
IOP Inbound
IOP Outbound
OCM Memory
S0
DAP Controller
APB
APB SS1
CSU Processor
PMU Processor
AXI
Quad-SPI
GEM x4
NAND
SDIO x2
IOP with Masters
IOP Units
UART x2
SPI x2
CAN x2 I2C x2
IOP Slave-only
S
S
TBU2
Programmable
Logic
S2
FPD SLCRs
FPD configs
DDR Memory Controller
SMMU TCU
S4 S5S3
DisplayPort
FPD DMA
TBU5
CoreSight
S2
S3 S4
DVMM2 M1 M0
S0
S1
PCIe
SATA
AXI Stream
GPU PPs
LPD Outbound
LPD Inbound
S
M_AXI_HPM0_LPD
S_AXI_LPD
S_AXI_HP3_FPD
S_AXI_HP2_FPD
S_AXI_HP1_FPD
S_AXI_HP0_FPD
S_AXI_ACP_FPD
S_AXI_ACE_FPD
S_AXI_HPC0_FPD
S_AXI_HPC1_FPD
M_AXI_HPM0_FPD
M_AXI_HPM1_FPD
I/O Coherent
Master
GPU CFG
LPD Main
Switch
RPU
Switch
Full crossbar.
Each input to all
output ports.
Full crossbar.
To all output ports.
GPIO x78, x96
FPD
Main
Switch
AXI Stream
SIOU Outbound
APB
Non-Coherent
Master
RPU M
M
TTC x4 LPD SWDT
M M
TBU3 TBU4
TBU1 TBU0
VCU RF PCIe v3.1 100Gb
PL SysMon
IOP Outbound to FPD register:
IOU_INTERCONNECT_ROUTE
DDR4
(1 GB)
DDR4
(1 GB)
DDR4
(1 GB)
DDR4
(1 GB)
x16 x16
QSPI
(512 Mb)
TPM2.0
eMMC
(16 GB)
x4
x8
EEPROM
Connector 1 Connnector 2
I2C
x4 PS-GTR
x49 MIO
32.768 kHz
Oscillator
33.33 MHz
Oscillator
x4 GTH
x21 HDIO
x48 HDIO
x32 HPIO (x16 differential pairs)
x84 HPIO
(42 differential
pairs)
SPI
x16 x16
Xilinx MPSoC
APB
X24999-032421
Chapter 1: Introduction
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Chapter 2
Electrical Design Considerations
This chapter describes the electrical interface details needed to design your carrier card to mate
with the Kria™ K26 SOM. The electrical interface design guidelines include the SOM connector
details and signal names, signal roung guidelines, and power supply design.
SOM Connector Overview
The K26 SOM uses two 240-pin connectors to provide electrical connecvity between the SOM
and the carrier card. These two connectors are referred to as SOM240_1 and SOM240_2.
The SOM240_1 and SOM240_2 connectors use the Samtec 0.635 mm AcceleRate HD high-
density 4-row, 60 posion connector set. The part number for the socket (ADF6–60–03.5–L–4–
2–A) is used on the boom side of the SOM. The part number for the terminal (ADM6–60–
01.5–L–4–2–A) is for use on the carrier card. The SOM240_1 and SOM240_2 connectors
provide support for following interfaces.
• Control and status signals
•Mulplexed I/O (MIO) bank
• PS-GTR high-speed serial transceiver signals
• High-performance I/O (HPIO) bank signals
• High-density I/O (HDIO) bank signals
• GTH high-speed serial transceiver signals
• Power system
Signal Naming Conventions
The SOM240 connectors adopt the naming convenons outlined in the following table.
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Table 1: SOM240 Signal Naming Conventions
Signal Description
Module (M) The SOM, in this case the K26 SOM
Carrier card (C) The board that the SOM is plugged into is called the carrier card
C2M Signal names with C2M indicate that the signal is driven by the carrier card and received by
the SOM
M2C Signal names with M2C indicate that the signal is driven by the SOM and received by the
carrier card
_P The postfix _P on differential signal pairs indicates the positive component of a differential
signal
_N The postfix _N on differential signal pairs indicates the negative component of a differential
signal
_L The postfix _L on a single-ended signal indicates an active-Low signal. This is used for the
connector pinouts only. The postfix _B is also used to indicate an active-Low signal.
Table 2: Legend for Connector Pinouts
Example SOM240 Connector Function
GND Both SOM240_1 and SOM240_2 Ground pins
VCC_SOM Both SOM240_1 and SOM240_2 Power connection pins
MIO35 SOM240_1 MIO 501 bank pins
MIO58 SOM240_1 MIO 502 bank pins
JTAG_TMS_C2M SOM240_1 Configuration and control pins
GTR_DP1_M2C_P SOM240_1 PS-GTR transceiver pins
HPA04_P SOM240_1 HPA pins
HDA00_CC SOM240_1 HDA pins
HPB15_CC_P SOM240_2 HPB pins
HPC07_P SOM240_2 HPC pins
HDB12 SOM240_2 HDB pins
HDC00_CC SOM240_2 HDC pins
GTH_DP2_C2M_P SOM240_2 GTH transceiver pins
SOM240_1 Connector Pinout
The SOM240_1 connector provides access to two MIO banks (MIO501, MIO502), HPIO bank 66
(HPA), HDIO bank 45 (HDA), and the PS-GTR transceivers (MIO505). It also provides sideband
signals for conguraon and operaon of the board.
Chapter 2: Electrical Design Considerations
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Table 3: SOM240_1 Connector Pinout
Connector
Row/ Pin
Number
A B C D
1 VCC_BATT HPA05_CC_P GND VCCO_HPA
2 GND HPA05_CC_N GND VCCO_HPA
3 HPA06_P GND HPA00_CC_P GND
4 HPA06_N HPA04_P HPA00_CC_N HPA02_P
5 GND HPA04_N GND HPA02_N
6 HPA_CLK0_P GND HPA03_P GND
7 HPA_CLK0_N HPA07_P HPA03_N HPA01_P
8 GND HPA07_N GND HPA01_N
9 HPA12_P GND HPA08_P GND
10 HPA12_N HPA11_P HPA08_N HPA09_P
11 GND HPA11_N GND HPA09_N
12 HPA13_P GND HPA10_CC_P GND
13 HPA13_N VCCO_HDA HPA10_CC_N HPA14_P
14 GND VCCO_HDA GND HPA14_N
15 HDA09 GND PS_POR_L GND
16 HDA10 HDA03 PS_SRST_C2M_L HDA00_CC
17 HDA11 HDA04 GND HDA01
18 GND HDA05 HDA06 HDA02
19 VCCOEN_PS_M2C GND HDA07 GND
20 VCCOEN_PL_M2C HDA15 HDA08_CC HDA12
21 GND HDA16_CC GND HDA13
22 JTAG_TMS_C2M HDA17 HDA18 HDA14
23 JTAG_TDO_M2C GND HDA19 GND
24 JTAG_TDI_C2M PS_ERROR_OUT_M2C HDA20 PWRGD_FPD_M2C
25 JTAG_TCK_C2M PS_ERROR_STATUS_M2C GND PWRGD_LPD_M2C
26 GND PWROFF_C2M_L MIO24_I2C_SCK PWRGD_PL_M2C
27 MODE0_C2M GND MIO25_I2C_SDA GND
28 MODE1_C2M MIO35 MIO12_FWUEN_C2M_L MIO26_WD_IN
29 MODE2_C2M MIO36 GND MIO27
30 MODE3_C2M MIO37 MIO29 MIO28
31 Reserved GND MIO30 GND
32 Reserved MIO38 MIO31_SHUTDOWN MIO44
33 GND MIO39 GND MIO45
34 MIO41 MIO40 MIO47 MIO46
35 MIO42 GND MIO48 GND
36 MIO43 MIO50 MIO49 MIO52
37 GND MIO51 GND MIO53
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Table 3: SOM240_1 Connector Pinout (cont'd)
Connector
Row/ Pin
Number
A B C D
38 MIO61 Reserved MIO55 MIO54
39 MIO62 GND MIO56 GND
40 MIO63 MIO58 MIO57 MIO64
41 GND MIO59 GND MIO65
42 MIO73 MIO60 MIO67 MIO66
43 MIO74 GND MIO68 GND
44 MIO75 MIO70 MIO69 MIO76
45 GND MIO71 Reserved MIO77
46 GND MIO72 GND Reserved
47 GTR_DP1_M2C_P GND GTR_REFCLK0_C2M_P GND
48 GTR_DP1_M2C_N GND GTR_REFCLK0_C2M_N GND
49 GND GTR_REFCLK1_C2M_P GND GTR_DP3_C2M_P
50 GND GTR_REFCLK1_C2M_N GND GTR_DP3_C2M_N
51 GTR_REFCLK3_C2M_P GND GTR_DP3_M2C_P GND
52 GTR_REFCLK3_C2M_N GND GTR_DP3_M2C_N GND
53 GND GTR_DP2_C2M_P GND GTR_REFCLK2_C2M_P
54 GND GTR_DP2_C2M_N GND GTR_REFCLK2_C2M_N
55 GTR_DP0_C2M_P GND GTR_DP1_C2M_P GND
56 GTR_DP0_C2M_N GND GTR_DP1_C2M_N GND
57 GND GTR_DP0_M2C_P GND GTR_DP2_M2C_P
58 GND GTR_DP0_M2C_N GND GTR_DP2_M2C_N
59 VCC_SOM GND VCC_SOM GND
60 VCC_SOM VCC_SOM VCC_SOM VCC_SOM
SOM240_1 Signal Names and Descriptions
Table 4: SOM240_1 Signal Pins
Pin Number Signal Name Signal Description
Connector Row A
A1 VCC_BATT PS BBRAM and real-time clock (RTC) supply voltage, requires external battery.
Connect to GND when battery is not used.
A2 GND Ground
A3 HPA06_P HPIO on bank 66
A4 HPA06_N HPIO on bank 66
A5 GND Ground
A6 HPA_CLK0_P HPIO global clock pin on bank 66
A7 HPA_CLK0_N HPIO global clock pin on bank 66
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Table 4: SOM240_1 Signal Pins (cont'd)
Pin Number Signal Name Signal Description
A8 GND Ground
A9 HPA12_P HPIO on bank 66
A10 HPA12_N HPIO on bank 66
A11 GND Ground
A12 HPA13_P HPIO on bank 66
A13 HPA13_N HPIO on bank 66
A14 GND Ground
A15 HDA09 HDIO on bank 45
A16 HDA10 HDIO on bank 45
A17 HDA11 HDIO on bank 45
A18 GND Ground
A19 VCCOEN_PS_M2C Indication to turn on power for PS I/O peripherals on the carrier card
A20 VCCOEN_PL_M2C Indication to turn on power for PL /IO peripherals on the carrier card
A21 GND Ground
A22 JTAG_TMS_C2M JTAG mode select, pulled up at 1.8V on the SOM
A23 JTAG_TDO_M2C JTAG data out, pulled up at 1.8V on the SOM
A24 JTAG_TDI_C2M JTAG data in, pulled up at 1.8V on the SOM
A25 JTAG_TCK_C2M JTAG clock, pulled up at 1.8V on the SOM
A26 GND Ground
A27 MODE0_C2M PS mode bit 0, pulled up at 1.8V on the SOM
A28 MODE1_C2M PS mode bit 1, pulled up at 1.8V on the SOM
A29 MODE2_C2M PS mode bit 2, pulled up at 1.8V on the SOM
A30 MODE3_C2M PS mode bit 3, pulled up at 1.8V on the SOM
A31 Reserved No connect on the SOM
A32 Reserved No connect on the SOM
A33 GND Ground
A34 MIO41 PS MIO signal on bank 501
A35 MIO42 PS MIO signal on bank 501
A36 MIO43 PS MIO signal on bank 501
A37 GND Ground
A38 MIO61 PS MIO signal on bank 502
A39 MIO62 PS MIO signal on bank 502
A40 MIO63 PS MIO signal on bank 502
A41 GND Ground
A42 MIO73 PS MIO signal on bank 502
A43 MIO74 PS MIO signal on bank 502
A44 MIO75 PS MIO signal on bank 502
A45 GND Ground
A46 GND Ground
Chapter 2: Electrical Design Considerations
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Table 4: SOM240_1 Signal Pins (cont'd)
Pin Number Signal Name Signal Description
A47 GTR_DP1_M2C_P PS-GTR lane 1 TX
A48 GTR_DP1_M2C_N PS-GTR lane 1 TX
A49 GND Ground
A50 GND Ground
A51 GTR_REFCLK3_C2M_P PS-GTR REFCLK3 input
A52 GTR_REFCLK3_C2M_N PS-GTR REFCLK3 input
A53 GND Ground
A54 GND Ground
A55 GTR_DP0_C2M_P PS-GTR lane 0 RX
A56 GTR_DP0_C2M_N PS-GTR lane 0 RX
A57 GND Ground
A58 GND Ground
A59 VCC_SOM SOM main supply voltage, +5V
A60 VCC_SOM SOM main supply voltage, +5V
Connector Row B
B1 HPA05_CC_P HPIO clock-capable pin on bank 66
B2 HPA05_CC_N HPIO clock-capable pin on bank 66
B3 GND Ground
B4 HPA04_P HPIO on bank 66
B5 HPA04_N HPIO on bank 66
B6 GND Ground
B7 HPA07_P HPIO on bank 66
B8 HPA07_N HPIO on bank 66
B9 GND Ground
B10 HPA11_P HPIO on bank 66
B11 HPA11_N HPIO on bank 66
B12 GND Ground
B13 VCCO_HDA HDA I/O voltage rail, 1.2V to 3.3V
B14 VCCO_HDA HDA I/O voltage rail, 1.2V to 3.3V
B15 GND Ground
B16 HDA03 HDIO on bank 45
B17 HDA04 HDIO on bank 45
B18 HDA05 HDIO on bank 45
B19 GND Ground
B20 HDA15 HDIO on bank 45
B21 HDA16_CC HDIO clock-capable pin on bank 45
B22 HDA17 HDIO on bank 45
B23 GND Ground
B24 PS_ERROR_OUT_M2C PS error indication from SOM
Chapter 2: Electrical Design Considerations
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Table 4: SOM240_1 Signal Pins (cont'd)
Pin Number Signal Name Signal Description
B25 PS_ERROR_STATUS_M2C PS error status from SOM
B26 PWROFF_C2M_L Control signal to turn off all power rails on the SOM
B27 GND Ground
B28 MIO35 PS MIO signal on bank 501. Optional use as PMU output.
B29 MIO36 PS MIO signal on bank 501
B30 MIO37 PS MIO signal on bank 501
B31 GND Ground
B32 MIO38 PS MIO signal on bank 501
B33 MIO39 PS MIO signal on bank 501
B34 MIO40 PS MIO signal on bank 501
B35 GND Ground
B36 MIO50 PS MIO signal on bank 501
B37 MIO51 PS MIO signal on bank 501
B38 Reserved Not connected to SOM connector
B39 GND Ground
B40 MIO58 PS MIO signal on bank 502
B41 MIO59 PS MIO signal on bank 502
B42 MIO60 PS MIO signal on bank 502
B43 GND Ground
B44 MIO70 PS MIO signal on bank 502
B45 MIO71 PS MIO signal on bank 502
B46 MIO72 PS MIO signal on bank 502
B47 GND Ground
B48 GND Ground
B49 GTR_REFCLK1_C2M_P PS-GTR REFCLK1 input
B50 GTR_REFCLK1_C2M_N PS-GTR REFCLK1 input
B51 GND Ground
B52 GND Ground
B53 GTR_DP2_C2M_P PS-GTR lane 2 RX
B54 GTR_DP2_C2M_N PS-GTR lane 2 RX
B55 GND Ground
B56 GND Ground
B57 GTR_DP0_M2C_P PS-GTR lane 0 TX
B58 GTR_DP0_M2C_N PS-GTR lane 0 TX
B59 GND Ground
B60 VCC_SOM SOM main supply voltage, +5V
Connector Row C
C1 GND Ground
C2 GND Ground
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Table 4: SOM240_1 Signal Pins (cont'd)
Pin Number Signal Name Signal Description
C3 HPA00_CC_P HPIO clock-capable pin on bank 66
C4 HPA00_CC_N HPIO clock-capable pin on bank 66
C5 GND Ground
C6 HPA03_P HPIO on bank 66
C7 HPA03_N HPIO on bank 66
C8 GND Ground
C9 HPA08_P HPIO on bank 66
C10 HPA08_N HPIO on bank 66
C11 GND Ground
C12 HPA10_CC_P HPIO clock-capable pin on bank 66
C13 HPA10_CC_N HPIO clock-capable pin on bank 66
C14 GND Ground
C15 PS_POR_L PS power-on reset driven by the carrier card. When deasserted, the PS begins
the boot process
C16 PS_SRST_C2M_L PS system reset driven by the carrier card. When asserted, forces the PS to
enter the system reset sequence
C17 GND Ground
C18 HDA06 HDIO on bank 45
C19 HDA07 HDIO on bank 45
C20 HDA08_CC HDIO clock-capable pin on bank 45
C21 GND Ground
C22 HDA18 HDIO on bank 45
C23 HDA19 HDIO on bank 45
C24 HDA20 HDIO on bank 45
C25 GND Ground
C26 MIO24_I2C_SCK PS I2C clock output
C27 MIO25_I2C_SDA PS I2C serial data
C28 MIO12_FWUEN_C2M_L Firmware user enable indication
C29 GND Ground
C30 MIO29 PS MIO signal on bank 501. No connect on the SOM
C31 MIO30 PS MIO signal on bank 501. No connect on the SOM
C32 MIO31_SHUTDOWN PS MIO signal on bank 501. Optional use as PMU input. Optional PMU library
enabled input for hardware-initiated shutdown by the PMU.
C33 GND Ground
C34 MIO47 PS MIO signal on bank 501
C35 MIO48 PS MIO signal on bank 501
C36 MIO49 PS MIO signal on bank 501
C37 GND Ground
C38 MIO55 PS MIO signal on bank 502
C39 MIO56 PS MIO signal on bank 502
Chapter 2: Electrical Design Considerations
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Table 4: SOM240_1 Signal Pins (cont'd)
Pin Number Signal Name Signal Description
C40 MIO57 PS MIO signal on bank 502
C41 GND Ground
C42 MIO67 PS MIO signal on bank 502
C43 MIO68 PS MIO signal on bank 502
C44 MIO69 PS MIO signal on bank 502
C45 Reserved NC on the SOM
C46 GND Ground
C47 GTR_REFCLK0_C2M_P PS-GTR REFCLK0 input
C48 GTR_REFCLK0_C2M_N PS-GTR REFCLK0 input
C49 GND Ground
C50 GND Ground
C51 GTR_DP3_M2C_P PS-GTR lane 3 TX
C52 GTR_DP3_M2C_N PS-GTR lane 3 TX
C53 GND Ground
C54 GND Ground
C55 GTR_DP1_C2M_P PS-GTR lane 1 RX
C56 GTR_DP1_C2M_N PS-GTR lane 1 RX
C57 GND Ground
C58 GND Ground
C59 VCC_SOM SOM main supply voltage, +5V
C60 VCC_SOM SOM main supply voltage, +5V
Connector Row D
D1 VCCO_HPA HPA I/O voltage rail, 1.0V to 1.8V
D2 VCCO_HPA HPA I/O voltage rail, 1.0V to 1.8V
D3 GND Ground
D4 HPA02_P HPIO on bank 66
D5 HPA02_N HPIO on bank 66
D6 GND Ground
D7 HPA01_P HPIO on bank 66
D8 HPA01_N HPIO on bank 66
D9 GND Ground
D10 HPA09_P HPIO on bank 66
D11 HPA09_N HPIO on bank 66
D12 GND Ground
D13 HPA14_P HPIO on bank 66
D14 HPA14_N HPIO on bank 66
D15 GND Ground
D16 HDA00_CC HDIO clock-capable pin on bank 45
D17 HDA01 HDIO on bank 45
Chapter 2: Electrical Design Considerations
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Table 4: SOM240_1 Signal Pins (cont'd)
Pin Number Signal Name Signal Description
D18 HDA02 HDIO on bank 45
D19 GND Ground
D20 HDA12 HDIO on bank 45
D21 HDA13 HDIO on bank 45
D22 HDA14 HDIO on bank 45
D23 GND Ground
D24 PWRGD_FPD_M2C Power good indication for PS FPD power rails
D25 PWRGD_LPD_M2C Power good indication for PS LPD power rails
D26 PWRGD_PL_M2C Power good indication for all PL power rails
D27 GND Ground
D28 MIO26 PS MIO signal on bank 501. Optional use as PMU input.
D29 MIO27 PS MIO signal on bank 501. Optional use as PMU input.
D30 MIO28 PS MIO signal on bank 501. Optional use as PMU input.
D31 GND Ground
D32 MIO44 PS MIO signal on bank 501
D33 MIO45 PS MIO signal on bank 501
D34 MIO46 PS MIO signal on bank 501
D35 GND Ground
D36 MIO52 PS MIO signal on bank 502
D37 MIO53 PS MIO signal on bank 502
D38 MIO54 PS MIO signal on bank 502
D39 GND Ground
D40 MIO64 PS MIO signal on bank 502
D41 MIO65 PS MIO signal on bank 502
D42 MIO66 PS MIO signal on bank 502
D43 GND Ground
D44 MIO76 PS MIO signal on bank 502
D45 MIO77 PS MIO signal on bank 502
D46 Reserved No connect on the SOM
D47 GND Ground
D48 GND Ground
D49 GTR_DP3_C2M_P PS-GTR lane 3 RX
D50 GTR_DP3_C2M_N PS-GTR lane 3 RX
D51 GND Ground
D52 GND Ground
D53 GTR_REFCLK2_C2M_P PS-GTR REFCLK2 input
D54 GTR_REFCLK2_C2M_N PS-GTR REFCLK2 input
D55 GND Ground
D56 GND Ground
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Table 4: SOM240_1 Signal Pins (cont'd)
Pin Number Signal Name Signal Description
D57 GTR_DP2_M2C_P PS-GTR lane 2 TX
D58 GTR_DP2_M2C_N PS-GTR lane 2 TX
D59 GND Ground
D60 VCC_SOM SOM main supply voltage, +5V
SOM240_2 Connector Pinout
The SOM240_1 connector provides access to two HPIO bank 65 (HPB), HPIO bank 64 (HPC),
HDIO bank43 (HDB, HDIO bank 44 (HDC), and the PL GTH Quad.
Table 5: SOM240_2 Connector Pinout
Connector
Row/ Pin
Number
A B C D
1 GND GTH_DP2_C2M_P GND GTH_DP1_C2M_P
2 GND GTH_DP2_C2M_N GND GTH_DP1_C2M_N
3 GTH_DP3_C2M_P GND GTH_REFCLK0_C2M_P GND
4 GTH_DP3_C2M_N GND GTH_REFCLK0_C2M_N GND
5 GND GTH_DP2_M2C_P GND GTH_DP3_M2C_P
6 GND GTH_DP2_M2C_N GND GTH_DP3_M2C_N
7 GTH_REFCLK1_C2M_P GND GTH_DP1_M2C_P GND
8 GTH_REFCLK1_C2M_N GND GTH_DP1_M2C_N GND
9 GND GTH_DP0_C2M_P GND GTH_DP0_M2C_P
10 GND GTH_DP0_C2M_N GND GTH_DP0_M2C_N
11 HPB15_CC_P GND HPB09_P GND
12 HPB15_CC_N HPB10_CC_P HPB09_N HPB01_P
13 GND HPB10_CC_N GND HPB01_N
14 HPB08_P GND HPB14_P GND
15 HPB08_N HPB07_P HPB14_N HPB00_CC_P
16 GND HPB07_N GND HPB00_CC_N
17 HPB12_P GND HPB02_P GND
18 HPB12_N HPB05_CC_P HPB02_N HPB_CLK0_P
19 GND HPB05_CC_N GND HPB_CLK0_N
20 HPB06_P GND HPB13_P GND
21 HPB06_N HPB11_P HPB13_N HPB04_P
22 GND HPB11_N GND HPB04_N
23 HPB16_P GND HPB_18_P GND
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Table 5: SOM240_2 Connector Pinout (cont'd)
Connector
Row/ Pin
Number
A B C D
24 HPB16_N HPB03_P HPB_18_N HPB17_P
25 GND HPB03_N GND HPB17_N
26 HPB_19_P GND HPC07_P GND
27 HPB_19_N HPC06_P HPC07_N HPC09_P
28 GND HPC06_N GND HPC09_N
29 HPC17_P GND HPC05_CC_P GND
30 HPC17_N HPC13_P HPC05_CC_N HPC01_P
31 GND HPC13_N GND HPC01_N
32 HPC19_P GND HPC08_P GND
33 HPC19_N HPC16_P HPC08_N HPC00_CC_P
34 GND HPC16_N GND HPC00_CC_N
35 HPC14_P GND HPC11_P GND
36 HPC14_N HPC10_CC_P HPC11_N HPC02_P
37 GND HPC10_CC_N GND HPC02_N
38 HPC15_CC_P GND HPC12_P GND
39 HPC15_CC_N HPC18_P HPC12_N HPC04_P
40 GND HPC18_N GND HPC04_N
41 HPC03_P GND HPC_CLK0_P GND
42 HPC03_N VCCO_HPB HPC_CLK0_N VCCO_HPC
43 GND GND GND GND
44 VCCO_HPB HDB12 VCCO_HPC HDB00_CC
45 GND HDB13 GND HDB01
46 HDB18 HDB14 HDB06 HDB02
47 HDB19 GND HDB07 GND
48 HDB20 HDB15 HDB08_CC HDB03
49 GND HDB16_CC GND HDB04
50 HDB21 HDB17 HDB09 HDB05
51 HDB22 GND HDB10 GND
52 HDB23 HDC12 HDB11 HDC00_CC
53 GND HDC13 GND HDC01
54 HDC18 HDC14 HDC06 HDC02
55 HDC19 GND HDC07 GND
56 HDC20 HDC15 HDC08_CC HDC03
57 GND HDC16_CC GND HDC04
58 HDC21 HDC17 HDC09 HDC05
59 HDC22 VCCO_HDB HDC10 VCCO_HDC
60 HDC23 VCCO_HDB HDC11 VCCO_HDC
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SOM240_2 Signal Names and Descriptions
Table 6: SOM240_2 Signal Pins
Pin Number Signal Name Signal Description
Connector Row A
A1 GND Ground
A2 GND Ground
A3 GTH_DP3_C2M_P GTH Lane 3 RX
A4 GTH_DP3_C2M_N GTH Lane 3 RX
A5 GND Ground
A6 GND Ground
A7 GTH_REFCLK1_C2M_P GTH REFCLK1 input
A8 GTH_REFCLK1_C2M_N GTH REFCLK1 input
A9 GND Ground
A10 GND Ground
A11 HPB15_CC_P HPIO clock-capable pin on bank 65
A12 HPB15_CC_N HPIO clock-capable pin on bank 65
A13 GND Ground
A14 HPB08_P HPIO on bank 65
A15 HPB08_N HPIO on bank 65
A16 GND Ground
A17 HPB12_P HPIO on bank 65
A18 HPB12_N HPIO on bank 65
A19 GND Ground
A20 HPB06_P HPIO on bank 65
A21 HPB06_N HPIO on bank 65
A22 GND Ground
A23 HPB16_P HPIO on bank 65
A24 HPB16_N HPIO on bank 65
A25 GND Ground
A26 HPB_19_P HPIO on bank 65
A27 HPB_19_N HPIO on bank 65
A28 GND Ground
A29 HPC08_P HPIO on bank 64
A30 HPC08_N HPIO on bank 64
A31 GND Ground
A32 HPC19_P HPIO on bank 64
A33 HPC19_N HPIO on bank 64
A34 GND Ground
A35 HPC14_P HPIO on bank 64
A36 HPC14_N HPIO on bank 64
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Table 6: SOM240_2 Signal Pins (cont'd)
Pin Number Signal Name Signal Description
A37 GND Ground
A38 HPC15_CC_P HPIO clock-capable pin on bank 64
A39 HPC15_CC_N HPIO clock-capable pin on bank 64
A40 GND Ground
A41 HPC03_P HPIO on bank 64
A42 HPC03_N HPIO on bank 64
A43 GND Ground
A44 VCCO_HPB HPB I/O voltage rail, 1.0V to 1.8V
A45 GND Ground
A46 HDB18 HDIO on bank 43
A47 HDB19 HDIO on bank 43
A48 HDB20 HDIO on bank 43
A49 GND Ground
A50 HDB21 HDIO on bank 43
A51 HDB22 HDIO on bank 43
A52 HDB23 HDIO on bank 43
A53 GND Ground
A54 HDC18 HDIO on bank 44
A55 HDC19 HDIO on bank 44
A56 HDC20 HDIO on bank 44
A57 GND Ground
A58 HDC21 HDIO on bank 44
A59 HDC22 HDIO on bank 44
A60 HDC23 HDIO on bank 44
Connector Row B
B1 GTH_DP2_C2M_P GTH Lane 2 RX
B2 GTH_DP2_C2M_N GTH Lane 2 RX
B3 GND Ground
B4 GND Ground
B5 GTH_DP2_M2C_P GTH Lane 2 TX
B6 GTH_DP2_M2C_N GTH Lane 2 TX
B7 GND Ground
B8 GND Ground
B9 GTH_DP0_C2M_P GTH Lane 0 RX
B10 GTH_DP0_C2M_N GTH Lane 0 RX
B11 GND Ground
B12 HPB10_CC_P HPIO on bank 65
B13 HPB10_CC_N HPIO on bank 65
B14 GND Ground
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