Xilinx LogiCORE MicroBlaze User manual

LogiCORE IP
MicroBlaze Micro
Controller System v1.3
Product Guide
PG048 December 18, 2012

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PG048 December 18, 2012
Table of Contents
SECTION I: SUMMARY
IP Facts
Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Licensing and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 2: Product Specification
Standards Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 3: Designing with the Core
General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SECTION II: VIVADO DESIGN SUITE
Chapter 4: Customizing and Generating the Core
GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Parameter Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Parameter - Port Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Tool Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Chapter 5: Constraining the Core
Required Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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Device, Package, and Speed Grade Selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Clock Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Banking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Transceiver Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
I/O Standard and Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SECTION III: ISE DESIGN SUITE
Chapter 6: Customizing and Generating the Core
GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Parameter Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Parameter - Port Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Tool Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Chapter 7: Constraining the Core
Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SECTION IV: APPENDICES
Appendix A: Application Software Development
Xilinx Software Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Device Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Appendix B: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Troubleshooting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Simulation Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Appendix C: Additional Resources
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Notice of Disclaimer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Automotive Applications Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

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SECTION I: SUMMARY
IP Facts
Overview
Product Specification
Designing with the Core

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Introduction
The LogiCORE™ MicroBlaze™ Micro Controller
System (MCS) is a complete standalone
processor system intended for controller
applications. It is highly integrated and includes
the MicroBlaze processor, local memory for
program and data storage as well as a tightly
coupled I/O module implementing a standard
set of peripherals.
The MicroBlaze processor included in the MCS
has a fixed configuration, optimized for
minimal area. The full-featured MicroBlaze
processor is available in the ISE® Design Suite
Embedded Edition and the Vivado™ IP
integrator.
Features
• MicroBlaze processor
•LocalMemory
• MicroBlaze Debug Module (MDM)
• Tightly Coupled I/O Module including
°I/O Bus
°Interrupt Controller using fast interrupt
mode
°UART
°Fixed Interval Timers
°Programmable Interval Timers
°General Purpose Inputs
°General Purpose Outputs
IP Facts
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family(1)
Zynq™-7000(2), Virtex®-7, Kintex™-7, Artix™-7,
Virtex-6, Virtex-5, Spartan®-6, Virtex-4,
Spartan-3
Supported User
Interfaces
Local Memory Bus (LMB), Dynamic
Reconfiguration Port (DRP)
Resources See Table 2 - 2 .
Provided with Core
Design Files ISE: VHDL
Vivado: RTL
Example
Design Not Provided
Test Bench Not Provided
Constraints File Not Provided
Simulation
Model Verilog and/or VHDL Structural
Supported
S/W Driver(3) Standalone
Tested Design Flows(4)
Design Entry ISE Design Suite 14.4
Vivado Design Suite 2012.4(5)
Simulation Mentor Graphics ModelSim
Vivado Simulator
Synthesis Xilinx Synthesis Technology (XST)
Vivado Synthesis
Support
Provided by Xilinx @ www.xilinx.com/support
Notes:
1. For a complete listing of supported devices, see the release
notes for this core.
2. Supported in ISE Design Suite implementations only.
3. Standalone driver details can be found in the EDK or SDK
directory (<install_directory>/doc/usenglish/
xilinx_drivers.htm). Linux OS and driver support information is
available from //wiki.xilinx.com.
4. For the supported versions of the tools, see the Xilinx Design
Tools: Release Notes Guide.
5. Supports only 7 series devices.

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Chapter 1
Overview
The MicroBlaze™ Micro Controller System (MCS) is highly integrated standalone processor
system intended for controller applications. Data and program is stored in a local memory,
debug is facilitated by the MicroBlaze Debug Module, MDM. A standard set of peripherals
is also included, providing basic functionality like interrupt controller, UART, timers and
general purpose input and outputs.
Feature Summary
MicroBlaze
The MicroBlaze embedded processor soft core is a reduced instruction set computer (RISC)
optimized for implementation in Xilinx® Field Programmable Gate Arrays (FPGAs). Detailed
information on the MicroBlaze processor can be found in the MicroBlaze Processor
Reference Guide [Ref 5].
The MicroBlaze parameters in MicroBlaze MCS are fixed except for the possibility to enable/
disable the debug functionality. The values of all MicroBlaze parameters in MicroBlaze MCS
can be found in Table 4-2. These values correspond to the MicroBlaze Configuration Wizard
Minimum Area configuration.
X-Ref Target - Figure 1-1
Figure 1-1: MicroBlaze Micro Controller System (MCS)
ILMB
MicroBlaze
Local
Memory Bus
LMB BRAM
Interface Controller
Block RAM
(Dual Port)
DLMB
Local
Memory Bus
LMB BRAM
Interface Controller
I/O Module
MicroBlaze
Debug
Optional Feature

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Chapter 1: Overview
Local Memory
Local memory is used for data and program storage and is implemented using block RAM.
The size of the local memory is parameterized and can be between 4kB and 64kB. The local
memory is connected to MicroBlaze through the Local Memory Bus, LMB, and the LMB
BRAM Interface Controllers. Detailed information on LMB can be found in the Local Memory
Bus (LMB) V10 data sheet [Ref 1] and detailed information on the LMB BRAM Interface
Controller can be found in the LMB BRAM Interface Controller data sheet [Ref 2].
The LMB Bus and the LMB BRAM Interface Controller parameters are fixed except for the
memory size. The value of the parameters can be found in Table 4 -4 , Tab le 4 -5, Table 4-6
and Tab le 4-7.
Debug
The MicroBlaze Debug Module, MDM, connects MicroBlaze debug logic to the XMD low
level debugger. XMD can be used for downloading software, to set break points, view
register and memory contents. Detailed information about MDM can be found in the
MicroBlaze Debug Module (MDM) data sheet [Ref 3].
The MDM parameters, except the JTAG user-defined register, are fixed and their values can
be found in Table 4- 8.
When more than one MicroBlaze MCS instance with debug enabled is included in the same
design, a unique JTAG register must be used for each instance. When a single instance is
used, the default value USER2 should be kept unchanged.
I/O Module
The I/O Module is a light-weight implementation of a set of standard I/O functions
commonly used in a MicroBlaze processor sub-system. Detailed information about the I/O
Module can be found in the I/O Module product guide [Ref 4].
The I/O Module registers are mapped at address 0x4000000, and the I/O Bus is mapped at
address 0xC0000000-0xFFFFFFFF in the MicroBlaze memory space. The fixed I/O Module
parameter values can be found in Table 4-3.
Licensing and Ordering Information
This Xilinx LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado™
Design Suite and ISE® Design Suite tools under the terms of the Xilinx End User License.
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx
Intellectual Property page. For information about pricing and availability of other Xilinx
LogiCORE IP modules and tools, contact your local Xilinx sales representative.

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Chapter 2
Product Specification
Standards Compliance
The I/O Bus interface provided by the I/O Module is fully compatible with the Xilinx®
Dynamic Reconfiguration Port (DRP). For a detailed description of the DRP, see the 7 Series
FPGAs Configuration User Guide [Ref 10].
Performance
The frequency and latency of the modules in the MicroBlaze™ MCS are optimized for use
together with MicroBlaze. This means that the frequency targets are aligned to MicroBlaze
targets as well as the access latency optimized for MicroBlaze data access.
Maximum Frequencies
The following are clock frequencies for the target families. The maximum achievable clock
frequency can vary. The maximum achievable clock frequency and all resource counts can
be affected by the used tool flow, other tool options, additional logic in the FPGA, using
different versions of Xilinx tools, and other factors.
Latency
Data read from I/O Module registers is available two clock cycles after the MicroBlaze load
instruction is executed.
Table 2-1: Maximum Frequencies
Architecture Speed grade Max Frequency
Spartan®-6 -4 195
Virtex®-6 -3 300
Artix™-7 -3 225
Kintex™-7 -3 320
Virtex-7 -3 320

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Chapter 2: Product Specification
Data write to I/O Module registers is performed the clock cycle after the MicroBlaze store
instruction is executed.
Data accesses to peripherals connected on the I/O Bus take three clock cycles plus the
number of wait states introduced by the accessed peripheral.
Throughput
The maximum throughput when using the I/O Bus is one read or write access every three
clock cycles.
Resource Utilization
Because the MicroBlaze MCS is a module that is used together with other parts of the
design in the FPGA, the utilization and timing numbers reported in this section are just
estimates, and the actual utilization of FPGA resources and timing of the MicroBlaze MCS
design will vary from the results reported here. All parameters not given in Table 2 -2 have
their default values.
Table 2-2:
Performance and Resource Utilization Benchmarks on Virtex-6 (xc6vlx240t-1-ff1156)
Parameter Values (other parameters at default value) Device Resources
C_USE_UART_RX
C_USE_UART_TX
C_INTC_USE_EXT_INTR
C_INTC_INTR_SIZE
C_USE_FIT1
C_FIT1_No_CLOCKS
C_USE_PIT1
C_PIT1_SIZE
C_USE_GPI1
C_GPI1_SIZE
C_USE_GPO1
C_GPO1_SIZE
C_USE_IO_BUS
C_DEBUG_ENABLE
LUTs Flip-Flops
11000 0 00000000 546 276
11150 0 00000000 606 340
1115165000 00000000 620 353
1115165000 1 32 000000 656 441
1115165000 1 32 1 32 0 0 0 0 658 473
1115165000 1 32 1 32 1 32 0 0 659 505
1115165000 1 32 1 32 1 32 1 0 675 610
1115165000 1 32 1 32 1 32 1 1 882 946

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Chapter 2: Product Specification
Port Descriptions
The I/O ports and signals for MicroBlaze MCS are listed and described in Table 2 -3 .
Table 2-3: MicroBlaze MCS Signals
Port Name MSB:LSB I/O Description
System Signals
Clk I System clock
Reset I System reset
MicroBlaze Signals
Trace_Valid_Instr O Valid instruction on trace port
Trace_Instruction 0:31 O Instruction code
Trace_PC 0:31 O Program counter
Trace_Reg_Write O Instruction writes to the register file
Trace_Reg_Addr 0:4 O Destination register address
Trace_MSR_Reg 0:14 O Machine status register
Trace_New_Reg_Value 0:31 O Destination register update value
Trace_Jump_Taken O Branch instruction evaluated TRUE (taken)
Trace_Delay_Slot O Instruction is in delay slot of a taken branch
Trace_Data_AccessT O Valid D-side memory access
Trace_Data_Address 0:31 O Address for D-side memory access
Trace_Data_Write_Value 0:31 O Value for D-side memory write access
Trace_Data_Byte_Enable 0:3 O Byte enables for D-side memory access
Trace_Data_Read O D-side memory access is a read
Trace_Data_Write O D-side memory access is a write
I/O Bus Signals
IO_Addr_Strobe O Address strobe signals valid I/O Bus output
signals
IO_Read_Strobe O I/O Bus access is a read
IO_Write_Strobe O I/O Bus access is a write
IO_Address 31:0 O Address for access
IO_Byte_Enable 3:0 O Byte enables for access
IO_Write_Data 31:0 O Data to write for I/O Bus write access
IO_Read_Data 31:0 I Read data for I/O Bus read access
IO_Ready I Ready handshake to end I/O Bus access