Xilinx KC705 User manual

KC705 Evaluation
Board for the
Kintex-7 FPGA
User Guide
UG810 (v1.3) May 10, 2013

KC705 Evaluation Board www.xilinx.com UG810 (v1.3) May 10, 2013
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Revision History
The following table shows the revision history for this document.
Date Version Revision
01/23/12 1.0 Initial Xilinx release.
04/05/12 1.1 Updated links from Table 1-1, page 8. Revised the JTAG configuration mode USB cable
description under FPGA Configuration, page 9. Added Encryption Key Backup Circuit,
page 10 and Table 1-4, page 11. Added links to User SMA Clock Input in Table 1-8,
page 23. Added link to Si570 device vendor on page 25. Added Ethernet PHY Status
LEDs, page 47 and Figure 1-24, page 47. Updated Power On/Off Slide Switch SW15,
page 52 and added Figure 1-32, page 53. Revised FPGA Mezzanine Card Interface,
page 54 and Table 1-28, page 55 and Table 1-29, page 60. Added description of power
module cooling requirement to Power Management, page 61. Added Cooling Fan
Control, page 64. Updated Table 1-35, page 69. Added references to Documents, page 85.
Added Appendix E, Compliance with European Union Directives and Standards,
Appendix D, Board Setup, and Appendix E, Board Specifications.
12/10/12 1.2 Replaced direct, inline links to external references in the body text with indirect
references to the links in a numbered list in Appendix F, Additional Resources. Revised
the value for frequency jitter for the System Clock Source, page 24. Revised jumper
information for SFP_RS1, page 36 in Table 1-15. Revised contents and organization of
Appendix F, Additional Resources.
05/10/2013 1.3 Updated Figure 1-1 to show v 1.1 board. Updated Table 1-1, page 8: callout 1to identify
Fansink, callouts 25 and 26 pointing to User I/O. Added Table 1-9, page 24 Source to
FPGA Connections. Updated Programmable User Clock Source, page 25 to include I2C
address. Updated Table 1-17, page 35 for naming pins 18 and 19. Added Note to
Table 1-14, page 35. Updated I2C Bus Switch, page 45 to show TI device instead of NXP
Semiconductor, deleted; updated [Ref 9]. Added Figure 1-28, page 50 Rotary Switch, and
Figure 1-29, page 50 GPIO SMAs J13 and J14. Added Note to Appendix C, Master UCF
Listing. Updated Appendix D, Board Setup, step 1 of installation procedure. Updated
Appendix G, Regulatory and Compliance Information to include CE PC Test reference.

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UG810 (v1.3) May 10, 2013
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: KC705 Evaluation Board Features
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
KC705 Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Feature Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Kintex-7 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DDR3 Memory Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Linear BPI Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Quad-SPI Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SD Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
USB JTAG Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
GTX Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PCI Express Edge Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SFP/SFP+ Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10/100/1000 Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
USB-to-UART Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
HDMI Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
LCD Character Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
I2C Bus Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Ethernet PHY Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
FPGA Mezzanine Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
XADC Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Appendix A: Default Switch and Jumper Settings
DIP Switch SW11 User GPIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
DIP Switch SW13 Mode and Flash Address Settings . . . . . . . . . . . . . . . . . . . . . . . . . 71
Default Jumper Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Appendix B: VITA 57.1 FMC Connector Pinouts
Appendix C: Master UCF Listing
KC705 Board UCF Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Appendix D: Board Setup
Installing KC705 Board in a PC Chassis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table of Contents

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UG810 (v1.3) May 10, 2013
Appendix E: Board Specifications
Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Humidity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Operating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Appendix F: Additional Resources
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Solution Centers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Further Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Appendix G: Regulatory and Compliance Information
Declaration of Conformity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

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UG810 (v1.3) May 10, 2013
Chapter 1
KC705 Evaluation Board Features
Overview
The KC705 evaluation board for the Kintex™-7 FPGA provides a hardware environment
for developing and evaluating designs targeting the Kintex-7 XC7K325T-2FFG900C FPGA.
The KC705 board provides features common to many embedded processing systems,
including a DDR3 SODIMM memory, an 8-lane PCI Express® interface, a tri-mode
Ethernet PHY, general purpose I/O, and a UART interface. Other features can be added by
using mezzanine cards attached to either of two VITA-57 FPGA mezzanine connectors
(FMC) provided on the board. High pin count (HPC) and low pin count (LPC) FMCs are
provided. See KC705 Board Features for a complete list of features. The details for each
feature are described in Feature Descriptions, page 7.
Additional Information
See Appendix F, Additional Resources for references to documents, files and resources
relevant to the KC705 board.
KC705 Board Features
• Kintex-7 XC7K325T-2FFG900C FPGA
•1GB DDR3 memory SODIMM
• 128 MB Linear BPI Flash memory
• 128 Mb Quad-SPI Flash memory
• Secure Digital (SD) connector
• USB JTAG via Digilent module
•ClockGeneration
• Fixed 200 MHz LVDS oscillator (differential)
•I
2C programmable LVDS oscillator (differential)
• SMA connectors (differential)
• SMA connectors for GTX transceiver clocking
•GTXtransceivers
• FMC HPC connector (four GTX transceivers)
• FMC LPC connector (one GTX transceiver)
• SMA connectors (one pair each for TX, RX and REFCLK)
• PCI Express (eight lanes)
• Small form-factor pluggable plus (SFP+) connector

6www.xilinx.com KC705 Evaluation Board
UG810 (v1.3) May 10, 2013
Chapter 1: KC705 Evaluation Board Features
• Ethernet PHY SGMII interface (RJ-45 connector)
• PCI Express endpoint connectivity
• Gen1 8-lane (x8)
• Gen2 8-lane (x8)
• SFP+ Connector
• 10/100/1000 tri-speed Ethernet PHY
• USB-to-UART bridge
•HDMIcodec
•I
2C bus
•I
2C MUX
•I
2C EEPROM (1 KB)
•USERI
2C programmable LVDS oscillator
• DDR3 SODIMM socket
•HDMIcodec
• FMC HPC connector
• FMC LPC connector
• SFP+ connector
•I
2C programmable jitter-attenuating precision clock multiplier
• Status LEDs
•Ethernetstatus
• Power good
•FPGAINIT
•FPGADONE
•UserI/O
•USERLEDs(eightGPIO)
• User pushbuttons (five directional)
• CPU reset pushbutton
•UserDIPswitch(4-poleGPIO)
• User edge drive rotary encoder switch
• User SMA GPIO connectors (one pair)
• LCD character display (16 characters x 2 lines)
•Switches
• Power on/off slide switch
•FPGA_PROG_Bpushbuttonswitch
• VITA 57.1 FMC HPC Connector
• VITA 57.1 FMC LPC Connector
• Power management
• PMBus voltage and current monitoring via TI power controller
•XADCheader
• Configuration options

KC705 Evaluation Board www.xilinx.com 7
UG810 (v1.3) May 10, 2013
Feature Descriptions
• Linear BPI Flash memory
•QuadSPI
• USB JTAG configuration port
• Platform cable header JTAG configuration port
The KC705 board block diagram is shown in Figure 1-1. The KC705 board schematics are
available for download from The KC705 Evaluation Kit Product Page:
www.xilinx.com/kc705
Caution! The KC705 board can be damaged by electrostatic discharge (ESD). Follow standard
ESD prevention measures when handling the board
Feature Descriptions
Figure 1-2 shows the KC705 board. Each numbered feature that is referenced in Figure 1-2
is described in the sections that follow.
Note: The image in Figure 1-2 is for reference only and might not reflect the current revision of the
board.
X-Ref Target - Figure 1-1
Figure 1-1: KC705 Board Block Diagram
UG810_c1_01_011812
Kintex-7 FPGA
XC7K325T-2FFG900C
128 MB Linear BPI
Flash memory
128 Mb Quad-SPI
Flash Memory
8-lane PCI Express
Edge Connector
LCD Display
(2 line x 16 characters)
1 KB EEPROM (I2C)
I2C Bus Switch
XADC Header
User Switches,
Buttons, and LEDs
HDMI Video
Interface
Differential Clock
GTX SMA Clock
1 GB DDR3 Memory
(SODIMM)
FMC Connectors
(HPC/LPC)
10/100/1000 Ethernet
Interface
DIP Switch SW13
Config and Flash Addr USB-to-UART Bridge JTAG Interface
mini-B USB Connector SFP+ Single Cage

8www.xilinx.com KC705 Evaluation Board
UG810 (v1.3) May 10, 2013
Chapter 1: KC705 Evaluation Board Features
X-Ref Target - Figure 1-2
Figure 1-2: KC705 Board Components
UG841_c1_02_042313
3
3031
33
14
17
21
429
1
8
7
12
15 10
11
18
6
13
16
2
26
9
00 Square callout referencesacomponent
on the back side of the board
Round callout referencesacomponent
on the front side of the board
00
5
27
19
28
22
24
23
User rotary switch
located under LCD
25
20
35
36
3437
Table 1-1: KC705 Board Component Descriptions
Callout Reference
Designator Component Description Notes Schematic 0381397 Page Number
1U1 Kintex-7 FPGA (Located under fansink) XC7K325T-2FFG900C, Radian
INC3001-7_1.5BU_LI98
2J1 DDR3 Memory Module, under EMI shield Micron MT8JTF12864HZ-1G6G1 15
3U58 Linear BPI Flash Memory Micron/Numonyx PC28F00AP30TF 26
4U7 Quad-SPI Flash Memory Micron/Numonyx N25Q128A13BSF40F 26
5U9 SD Card Interface Molex 67840-8001 28
6USB JTAG Module Digilent USB JTAG Module (with micro-B
receptacle)
14
7U6 System Clock Source (back side of board) SiTime SIT9102-243N25E200.0000 23
8U45 Programmable User Clock Source (back side of
board)
Silicon Labs SI570BAB0000544DG 23
9J11, J12 User SMA Clock Input Rosenberger 32K10K-400L5 23
10 J15, J16 GTX SMA Clock Input Rosenberger 32K10K-400L5 23
11 U70 Jitter Attenuated Clock Silicon Labs SI5324C-C-GM 24
12 GTX Transceivers Embedded within FPGA U1 9
13 P1 PCI Express Edge Connector 8-lane card edge connector 21
14 P5 SFP/SFP+ Connector Molex 74441-0010 22
15 U37 10/100/1000 Tri-Speed Ethernet PHY Marvell M88E1111-BAB1C000 25
16 U2 SGMII GTX Transceiver Clock Generator ICS ICS84402IAGI-01LF 23

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UG810 (v1.3) May 10, 2013
Feature Descriptions
Kintex-7 FPGA
[Figure 1-2, callout 1]
The KC705 board is populated with the Kintex-7 XC7K325T-2FFG900C FPGA.
For further information on Kintex-7 FPGAs, see DS180, 7 Series FPGAs Overview.
FPGA Configuration
The KC705 board supports three of the five 7 Series FPGA configuration modes:
• Master SPI using the onboard Quad SPI Flash memory
• Master BPI using the on-board Linear BPI Flash memory
• JTAG using a standard-A to micro-B USB cable for connecting the host PC to the
KC705 board configuration port
Each configuration interface corresponds to one or more configuration modes and bus
widths as listed in Table 1-2. The mode switches M2, M1, and M0 are on SW13 positions 3,
4, and 5 respectively as shown in Figure 1-3.
17 J6, U12 USB-to-UART Bridge Silicon Labs CP2103GM bridge (back side of board)
and min-B receptacle (front side of board)
27
18 P6, U65 HDMI Video Output Molex 500254-1927, Analog Devices
ADV7511KSTZ-P
34, 33
19 J31 LCD Character Display 2 x 7 0.1 in male pin header 30
20 U49 I2C Bus Switch, page 45 TI PCA9548ARGER 32
21 DS11 - DS13 Ethernet PHY Status LEDs EPHY status LED, dual green 25
34 DS14, DS20 - DS24 Status LEDs Status LEDs, green 29
22 DS1 - DS4, Ds10,
DS25 - DS27
User GPIO LEDs GPIO LEDs, green 29
23 SW2 – SW6 User Pushbuttons E-Switch TL3301EP100QG 29
24 SW11 GPIO DIP Switch C and K 4-pole, SDA05H1SBD 29
25 SW8 Rotary Switch Panasonic EVQ-WK4001 29
26 J13, J14 GPIO SMA Connectors Rosenberger 32K10K-400L5 23
27 SW15 Power On/Off Slide Switch SW15 C and K 1201M2S3AQE2 35
28 SW14 FPGA_PROG_B Pushbutton SW14 (Active-Low) E-Switch TL3301EP100QG 29
29 SW13 Configuration Mode and Upper Linear Flash
Address Switch (SW13)
5-pole C and K SDA05H1IBD 27
30 J22 HPC Connector J22 Samtec ASP_134486_01 16-19
31 J2 LPC Connector J2 Samtec ASP_134603_01 20
32 U55, U21, U103, U17,
U56, U104, U105, U89,
U106, U99, U71, U62,
U17, U18, U33
Power Management (voltage regulators front
side of board, controllers back side of board)
TI UCD9248PFC controllers in conjunction with
various regulators
35-46
33 J46 XADC Header 2X10 0.1" male header 31
34 J60 2 x 7 2 mm shrouded JTAG cable connector Molex 87832-1420 16
35 J39 2 x 5 shrouded PMBus connector Assman HW10G-0202 35
36 J49 12V power input 2 x 3 connector Molex 39-30-1060 35
37 SW7 CPU Reset Pushbutton E-Switch TL3301EP100QG 35
Table 1-1: KC705 Board Component Descriptions (Cont’d)
Callout Reference
Designator Component Description Notes Schematic 0381397
Page Number

10 www.xilinx.com KC705 Evaluation Board
UG810 (v1.3) May 10, 2013
Chapter 1: KC705 Evaluation Board Features
The default mode setting is M[2:0] = 010, which selects Master BPI at board power-on.
Refer to the Configuration Options, page 69 for detailed information about the mode
switch SW13.
For full details on configuring the FPGA, see UG470, 7 Series FPGAs Configuration User
Guide
Encryption Key Backup Circuit
FPGA U1 implements bitstream encryption key technology. The KC705 board provides the
encryption key backup battery circuit shown in Figure 1-4. The rechargeable 1.5V lithium
button-type battery B1 is soldered to the board with the positive output connected to
FPGA U1 VCCBATT pin C10. The battery supply current IBATT specification is 150 nA max
when board power is off. B1 is charged from the VCCAUX_IO 2.0V rail through a series
diode with a typical forward voltage drop of 0.38V. and 4.7 KΩ current limit resistor. The
nominal charging voltage is 1.62V.
X-Ref Target - Figure 1-3
Figure 1-3: SW13 Default Settings
Table 1-2: KC705 board FPGA Configuration Modes
Configuration
Mode
SW13 DIP switch
Settings (M[2:0])
Bus
Width
CCLK
Direction
Master SPI 001 x1, x2, x4 Output
Master BPI 010 x8, x16 Output
JTAG 101 x1 Not Applicable
UG810_c1_03_011112
1
SW13
OFF Position = 0
ON Position = 1
2345
A25
A24 M2
M1 M0

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UG810 (v1.3) May 10, 2013
Feature Descriptions
I/O Voltage Rails
There are 10 I/O banks available on the Kintex-7 device. The voltages applied to the FPGA
I/O banks used by the KC705 board are listed in Table 1-3.
X-Ref Target - Figure 1-4
Figure 1-4: Encryption Key Backup Circuit
UG810_c1_100_030812
GND
2
1
B1
Lithium Battery
Seiko
TS518SE_FL35E
2
1
3
BAS40-04
D11
40V
200 mW
NC
FPGA_VBATT
+
VCCAUX_IO (2.0V
R406
4.70K 1%
1/16W
To FPGA U1 Pin C10
(VCCBATT)
Table 1-3: I/O Voltage Rails
U1 FPGA
Bank
Power Supply Rail
Net Name Voltage
Bank 0 VCC2V5_FPGA 2.5V
Bank 12(1) VADJ_FPGA 2.5V (default)
Bank 13(1) VADJ_FPGA 2.5V (default)
Bank 14 VCC2V5_FPGA 2.5V
Bank 15 VCC2V5_FPGA 2.5V
Bank 16(1) VADJ_FPGA 2.5V (default)
Bank 17(1) VADJ_FPGA 2.5V (default)
Bank 18(1) VADJ_FPGA 2.5V (default)
Bank 32 VCC1V5_FPGA 1.5V
Bank 33 VCC1V5_FPGA 1.5V
Bank 34 VCC1V5_FPGA 1.5V
Notes:
1. The VADJ_FPGA rail can support 1.8V, 2.5V, or 3.3V. For more
information on VADJ_FPGA see Power Management,
page 61.

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Chapter 1: KC705 Evaluation Board Features
DDR3 Memory Module
[Figure 1-2, callout 2]
The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module
(SODIMM). It provides volatile synchronous dynamic random access memory (SDRAM)
for storing user code and data.
• Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)
• Supply voltage: 1.5V
• Datapath width: 64 bits
• Data rate: Up to 1,600 MT/s
The DDR3 interface is implemented across I/O banks 32, 33, and 34. Each bank is a 1.5V
high-performance (HP) bank having a dedicated DCI VRP/N resistor connection. An
external 0.75V reference VTTREF is provided for data interface banks 32 and 34. Any
interface connected to these banks that requires a reference voltage must use this FPGA
voltage reference. The connections between the DDR 3 memory and the FPGA are listed in
Table 1-4.
Table 1-4: DDR3 Memory Connections to the FPGA
U1 FPGA Pin Net Name
J1 DDR3 Memory
Pin Number Pin Name
AH12 DDR3_A0 98 A0
AG13 DDR3_A1 97 A1
AG12 DDR3_A2 96 A2
AF12 DDR3_A3 95 A3
AJ12 DDR3_A4 92 A4
AJ13 DDR3_A5 91 A5
AJ14 DDR3_A6 90 A6
AH14 DDR3_A7 86 A7
AK13 DDR3_A8 89 A8
AK14 DDR3_A9 85 A9
AF13 DDR3_A10 107 A10/AP
AE13 DDR3_A11 84 A11
AJ11 DDR3_A12 83 A12_BC_N
AH11 DDR3_A13 119 A13
AK10 DDR3_A14 80 A14
AK11 DDR3_A15 78 A15
AH9 DDR3_BA0 109 BA0
AG9 DDR3_BA1 108 BA1
AK9 DDR3_BA2 79 BA2
AA15 DDR3_D0 5DQ0

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Feature Descriptions
AA16 DDR3_D1 7DQ1
AC14 DDR3_D2 15 DQ2
AD14 DDR3_D3 17 DQ3
AA17 DDR3_D4 4DQ4
AB15 DDR3_D5 6DQ5
AE15 DDR3_D6 16 DQ6
Y15 DDR3_D7 18 DQ7
AB19 DDR3_D8 21 DQ8
AD16 DDR3_D9 23 DQ9
AC19 DDR3_D10 33 DQ10
AD17 DDR3_D11 35 DQ11
AA18 DDR3_D12 22 DQ12
AB18 DDR3_D13 24 DQ13
AE18 DDR3_D14 34 DQ14
AD18 DDR3_D15 36 DQ15
AG19 DDR3_D16 39 DQ16
AK19 DDR3_D17 41 DQ17
AG18 DDR3_D18 51 DQ18
AF18 DDR3_D19 53 DQ19
AH19 DDR3_D20 40 DQ20
AJ19 DDR3_D21 42 DQ21
AE19 DDR3_D22 50 DQ22
AD19 DDR3_D23 52 DQ23
AK16 DDR3_D24 57 DQ24
AJ17 DDR3_D25 59 DQ25
AG15 DDR3_D26 67 DQ26
AF15 DDR3_D27 69 DQ27
AH17 DDR3_D28 56 DQ28
AG14 DDR3_D29 58 DQ29
AH15 DDR3_D30 68 DQ30
AK15 DDR3_D31 70 DQ31
AK8 DDR3_D32 129 DQ32
Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)
U1 FPGA Pin Net Name
J1 DDR3 Memory
Pin Number Pin Name

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Chapter 1: KC705 Evaluation Board Features
AK6 DDR3_D33 131 DQ33
AG7 DDR3_D34 141 DQ34
AF7 DDR3_D35 143 DQ35
AF8 DDR3_D36 130 DQ36
AK4 DDR3_D37 132 DQ37
AJ8 DDR3_D38 140 DQ38
AJ6 DDR3_D39 142 DQ39
AH5 DDR3_D40 147 DQ40
AH6 DDR3_D41 149 DQ41
AJ2 DDR3_D42 157 DQ42
AH2 DDR3_D43 159 DQ43
AH4 DDR3_D44 146 DQ44
AJ4 DDR3_D45 148 DQ45
AK1 DDR3_D46 158 DQ46
AJ1 DDR3_D47 160 DQ47
AF1 DDR3_D48 163 DQ48
AF2 DDR3_D49 165 DQ49
AE4 DDR3_D50 175 DQ50
AE3 DDR3_D51 177 DQ51
AF3 DDR3_D52 164 DQ52
AF5 DDR3_D53 166 DQ53
AE1 DDR3_D54 174 DQ54
AE5 DDR3_D55 176 DQ55
AC1 DDR3_D56 181 DQ56
AD3 DDR3_D57 183 DQ57
AC4 DDR3_D58 191 DQ58
AC5 DDR3_D59 193 DQ59
AE6 DDR3_D60 180 DQ60
AD6 DDR3_D61 182 DQ61
AC2 DDR3_D62 192 DQ62
AD4 DDR3_D63 194 DQ63
Y16 DDR3_DM0 11 DM0
Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)
U1 FPGA Pin Net Name
J1 DDR3 Memory
Pin Number Pin Name

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Feature Descriptions
AB17 DDR3_DM1 28 DM1
AF17 DDR3_DM2 46 DM2
AE16 DDR3_DM3 63 DM3
AK5 DDR3_DM4 136 DM4
AJ3 DDR3_DM5 153 DM5
AF6 DDR3_DM6 170 DM6
AC7 DDR3_DM7 187 DM7
AC15 DDR3_DQS0_N 10 DQS0_N
AC16 DDR3_DQS0_P 12 DQS0_P
Y18 DDR3_DQS1_N 27 DQS1_N
Y19 DDR3_DQS1_P 29 DQS1_P
AK18 DDR3_DQS2_N 45 DQS2_N
AJ18 DDR3_DQS2_P 47 DQS2_P
AJ16 DDR3_DQS3_N 62 DQS3_N
AH16 DDR3_DQS3_P 64 DQS3_P
AJ7 DDR3_DQS4_N 135 DQS4_N
AH7 DDR3_DQS4_P 137 DQS4_P
AH1 DDR3_DQS5_N 152 DQS5_N
AG2 DDR3_DQS5_P 154 DQS5_P
AG3 DDR3_DQS6_N 169 DQS6_N
AG4 DDR3_DQS6_P 171 DQS6_P
AD1 DDR3_DQS7_N 186 DQS7_N
AD2 DDR3_DQS7_P 188 DQS7_P
AD8 DDR3_ODT0 116 ODT0
AC10 DDR3_ODT1 120 ODT1
AK3 DDR3_RESET_B 30 RESET_B
AC12 DDR3_S0_B 114 S0_B
AE8 DDR3_S1_B 121 S1_B
AJ9 DDR3_TEMP_EVENT 198 EVENT_B
AE9 DDR3_WE_B 113 WE_B
AC11 DDR3_CAS_B 115 CAS_B
AD9 DDR3_RAS_B 110 RAS_B
Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)
U1 FPGA Pin Net Name
J1 DDR3 Memory
Pin Number Pin Name

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Chapter 1: KC705 Evaluation Board Features
The KC705 DDR3 SODIMM interface adheres to the constraints guidelines documented in
the DDR3 Design Guidelines section of UG586, 7 Series FPGAs Memory Interface Solutions
User Guide. The KC705 DDR3 SODIMM interface is a 40Ω impedance implementation.
Other memory interface details are available in UG586 and UG473, 7 Series FPGAs Memory
Resources User Guide. For more information about the Micron MT8JTF12864HZ-1G6G1 see
[Ref 5].
Linear BPI Flash Memory
[Figure 1-2, callout 3]
The Linear BPI Flash memory located at U58 provides 128 MB of nonvolatile storage that
can be used for configuration or software storage. The data, address, and control signals
are connected to the FPGA. The BPI Flash memory device is packaged in a 64-pin BGA.
• Part number: PC28F00AP30TF (Numonyx)
• Supply voltage: 2.5V
• Datapath width: 16 bits (26 address lines and 7 control signals)
• Data rate: Up to 33 MHz
The Linear BPI Flash memory can synchronously configure the FPGA in Master BPI mode
at the 33 MHz data rate supported by the PC28F00AP30TF Flash memory by using a
configuration bitstream generated with bitgen options for synchronous configuration and
for configuration clock division. The fastest configuration method uses the external
66 MHz oscillator connected to the FPGA EMCCLK pin with a bitstream that has been
built to divide the configuration clock by two. The division is necessary to remain within
the synchronous read timing specifications of the Flash memory.
Multiple bitstreams can be stored in the Linear BPI Flash. The two most significant address
bits (A25, A24) of the Flash memory are connected to DIP switch SW13 positions 1 and 2
respectively, and to the RS1 and RS0 pins of the FPGA. By placing valid XC7K325T
bitstreams at four different offset addresses in the Flash memory, 1 of the 4 bitstreams can
be selected to configure the FPGA by appropriately setting the DIP switch SW13. The
connections between the BPI Flash memory and the FPGA are listed in Table 1-5.
AF10 DDR3_CKE0 73 CKE0
AE10 DDR3_CKE1 74 CKE1
AH10 DDR3_CLK0_N 103 CK0_N
AG10 DDR3_CLK0_P 101 CK0_P
AF11 DDR3_CLK1_N 104 CK1_N
AE11 DDR3_CLK1_P 102 CK1_P
Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)
U1 FPGA Pin Net Name
J1 DDR3 Memory
Pin Number Pin Name

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UG810 (v1.3) May 10, 2013
Feature Descriptions
Table 1-5: BPI Flash Memory Connections to the FPGA
U1 FPGA Pin Net Name
U58 BPI Flash Memory
Pin Number Pin Name
W22 FLASH_A0 A1 A1
W21 FLASH_A1 B1 A2
V24 FLASH_A2 C1 A3
U24 FLASH_A3 D1 A4
V22 FLASH_A4 D2 A5
V21 FLASH_A5 A2 A6
U23 FLASH_A6 C2 A7
W24 FLASH_A7 A3 A8
W23 FLASH_A8 B3 A9
V20 FLASH_A9 C3 A10
V19 FLASH_A10 D3 A11
W26 FLASH_A11 C4 A12
V25 FLASH_A12 A5 A13
V30 FLASH_A13 B5 A14
V29 FLASH_A14 C5 A15
V27 FLASH_A15 D7 A16
P22 FLASH_A16 D8 A17
P21 FLASH_A17 A7 A18
N24 FLASH_A18 B7 A19
N22 FLASH_A19 C7 A20
N21 FLASH_A20 C8 A21
N20 FLASH_A21 A8 A22
N19 FLASH_A22 G1 A23
N26 FLASH_A23 H8 A24
M23 FLASH_A24 B6 A25
M22 FLASH_A25 B8 A26
P24 FLASH_D0 F2 DQ0
R25 FLASH_D1 E2 DQ1
R20 FLASH_D2 G3 DQ2
R21 FLASH_D3 E4 DQ3
T20 FLASH_D4 E5 DQ4
T21 FLASH_D5 G5 DQ5

18 www.xilinx.com KC705 Evaluation Board
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Chapter 1: KC705 Evaluation Board Features
Additional FPGA bitstreams can be stored and used for configuration by setting the Warm
Boot Start Address (WBSTAR) register contained in 7 series FPGAs. More information is
available in the reconfiguration and multiboot section in UG470, 7 Series FPGAs
Configuration User Guide. The configuration section in this document provides details on
the Master BPI configuration mode.
Figure 1-5 shows the connections of the linear BPI Flash memory on the KC705 board.
For more information about the Numonyx PC28F00AP30TF see [Ref 5].
T22 FLASH_D6 G6 DQ6
T23 FLASH_D7 H7 DQ7
U20 FLASH_D8 E1 DQ8
P29 FLASH_D9 E3 DQ9
R29 FLASH_D10 F3 DQ10
P27 FLASH_D11 F4 DQ11
P28 FLASH_D12 F5 DQ12
T30 FLASH_D13 H5 DQ13
P26 FLASH_D14 G7 DQ14
R26 FLASH_D15 E7 DQ15
U29 FLASH_WAIT F7 WAIT
M25 FPGA_FWE_B G8 WE_B
M24 FLASH_OE_B F8 OE_B
B10 FPGA_CCLK E6 CLK
U63.6 FLASH_CE_B B4 CE_B
M30 FLASH_ADV_B F6 ADV_B
A10 FPGA_INIT_B D4 RST_B
Table 1-5: BPI Flash Memory Connections to the FPGA (Cont’d)
U1 FPGA Pin Net Name
U58 BPI Flash Memory
Pin Number Pin Name

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Feature Descriptions
Quad-SPI Flash Memory
[Figure 1-2, callout 4]
The Quad-SPI Flash memory located at U7 on the back side of the board provides 128 Mb
of nonvolatile storage that can be used for configuration and data storage.
• Part number: N25Q128A13BSF40F (Numonyx)
• Supply voltage: 2.8V
• Datapath width: 4 bits
• Data rate: Various depending on Single/Dual/Quad mode and CCLK rate
X-Ref Target - Figure 1-5
Figure 1-5: 128 MB Linear Flash Memory (U58)
PC28F00AP30TF
64-Pin BGA (8 x 10 mm)
U58
FLASH_A0
A1
FLASH_A1
A2
FLASH_A2
A3
FLASH_A3
A4
FLASH_A4
A5
FLASH_A5
A6
FLASH_A6
A7
FLASH_A7
A8
FLASH_A8
A9
FLASH_A9
A10
FLASH_A10
A11
FLASH_A11
A12
FLASH_A12
A13
FLASH_A13
A14
FLASH_A14
A15
FLASH_A15
A16
FLASH_A16
A17
FLASH_A17
A18
FLASH_A18
A19
FLASH_A19
A20
FLASH_A20
A21
FLASH_A21
A22
FLASH_A22
A23
FLASH_A23
A24
FLASH_A24
A25
FLASH_A25
A26
NC
A27
VCC2
VCCQ1
VCCQ2
VCCQ3
VPP
VCC1
FLASH_D0_R DQ0
FLASH_D1_R DQ1
FLASH_D2_R DQ2
FLASH_D3_R DQ3
FLASH_D4_R DQ4
FLASH_D5_R DQ5
FLASH_D6_R DQ6
FLASH_D7_R DQ7
FLASH_D8_R DQ8
FLASH_D9_R DQ9
FLASH_D10_R DQ10
FLASH_D11_R DQ11
FLASH_D12_R DQ12
FLASH_D13_R DQ13
FLASH_D14_R DQ14
FLASH_D15_R DQ15
WE_B
FLASH_WP_B WP_B
ADV_B
RST_B
OE_B
CE_B
FLASH_WAIT_R WAIT
GND
VSS0
VSS1
VSS2
VSS3
NC RFU1
NC RFU2
NC RFU3
2.5V
1.8V
CLK
UG810_c1_04_011212
A1
B1
C1
D1
D2
A2
C2
A3
B3
C3
D3
C4
A5
B5
C5
H1
D7
D8
A7
B7
C7
C8
A8
G1
H8
B6
B8
D5
D6
G4
A4
A6
H3
F2
E2
G3
E4
E5
G5
G6
H7
E1
E3
F3
F4
F5
H5
G7
E7
G8
C6
F6
D4
F8
B4
F7
E6
H6
E8
F1
G2
B2
H2
H4
FLASH_ADV_B
FPGA_INIT_B
FLASH_OE_B
FLASH_CE_B
FLASH_PWE_B
FPGA_CCLK

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Chapter 1: KC705 Evaluation Board Features
Four data lines and the FPGA CCLK pin are wired to the Quad-SPI Flash memory. A
common chip select (FPGA_FCS) shared between the Linear BPI Flash and the Quad-SPI
Flash is controlled by the configuration mode settings on DIP switch SW13 position 5 (M0)
and a one-of-two demultiplexer device U64. If mode pin M0 = 1, the SPI device is selected.
If mode pin M0 = 0, the Linear BPI Flash device is selected. The connections between the
SPI Flash memory and the FPGA are listed in Table 1-6.
The configuration section of UG470, 7 Series FPGAs Configuration User Guide provides
details on using the Quad-SPI Flash memory. Figure 1-6 shows the connections of the
Quad-SPI Flash memory on the KC705 board.
For more information about the Numonyx N25Q128A13BSF40F see [Ref 5].
SD Card Interface
[Figure 1-2, callout 5]
Table 1-6: Quad-SPI Flash Memory Connections to the FPGA
U1 FPGA Pin Net Name
U7 Quad-SPI Flash Memory
Pin Number Pin Name
P24 FLASH_D0 15 DQ0
R25 FLASH_D1 8DQ1
R20 FLASH_D2 9DQ2
R21 FLASH_D3 1DQ3
B10 FPGA_CCLK 16 C
U19 QSPI_IC_CS_B(1) 7S_B
Notes:
1. FPGA_FCS connected to FPGA U1 pin U19 becomes QSPI_IC_CS_B through U64 and J3.
X-Ref Target - Figure 1-6
Figure 1-6: 128 Mb Quad-SPI Flash memory
UG810_c1_05_011912
VCC2V5
N25Q128
128 Mb Serial
Flash Memory
GND
1
2
3
5
7
6
U7
4
8
VCC_SPI
C18
0.1μF 25V
X5R
FLASH_D2
DQ1
16
15
14
12
10
11
13
9
SB
NC3
NC2
NC1
NC0
VCC
HOLD_B/DQ3
WB/VPP/DQ2
VSS
NC4
NC5
NC6
NC7
DQ0
C
R17
DNP
R18
4.7kΩ5%
R431
15Ω1%
R432
15Ω1%
FLASH_D0
FPGA_CCLK
FLASH_D2_R
FLASH_D0_R
GND
VCC2V5
R20
DNP
R19
4.7kΩ5%
R21
4.7kΩ5%
R430
15Ω1%
R429
15Ω1%
FLASH_D2_R
FLASH_D3_R
FLASH_D3
FLASH_D1
QSPI_IC_CS_B