Xilinx Zynq-7000 User manual

Zynq-7000
All Programmable SoC ZC702
Base Targeted Reference Design
(Vivado Design Suite 2013.3)
User Guide
UG925 (v6.0) February 21, 2014
This document applies to the following software versions: Vivado Design Suite 2013.3 and 2013.4This document applies to the following software versions: Vivado Design Suite 2013.3 and 2013.4This document applies to the following software versions: Vivado Design Suite 2013.3 and 2013.4This document applies to the following software versions: Vivado Design Suite 2013.3 and 2013.4

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Revision History
The following table shows the revision history for this document.
Date Version Revision
06/21/2012 1.0 Initial Xilinx release.
10/08/2012 2.0 Updated for ISE® Design Suite 14.2.
Replaced AXI VTC with VTC throughout. Changed Sobel engine to Sobel filter.
Chapter 1, Introduction: Added R, RW, COR, SoC, and SC to Tabl e 1-1. Expanded
descriptions of the TRD. Updated the block diagram in Figure 1-1.
Chapter 2, Functional Description: In Figure 2-1, replaced the continuous line
with a dotted line for Monitor and between VIDEO_MUX0 and Clk_detect and
revised AXI Interconnect inputs. Added slice registers to Tabl e 2 -1. In Table 2- 2 ,
changed SOBEL_ENGINE to FILTER_VDMA and FILTER_ENGINE. Added
FILTER_0_interrupt row in Ta b l e 2 - 3 , and SOBEL_VDMA changed to
FILTER_VDMA. In Ta b le 2-4, GPIO bit number 7 became N/A. In PL Clocks,
page 19, (FCLKCLK[3:0]) became (FCLK_CLK). In PL Reset, page 19,
(FCLKRESETN[3:0]) became FCLK_RESET[3:0]_N and FCLKRESETN[0] changed to
FCLK_RESET0_N. In Clocking, page 19, PS FCLKCLK[0] changed to PS FCLK_CLK0.
In Table 2- 5, clock signal sources and uses were updated. In Tabl e 2-9, added
xFilter, changed frequency and connection of s_axi_CONTROL_BUS_ACLK and
deleted s_axi_SOBEL_CONTROL_ACLK. Changed frequency of
INTERCONNECT_ACLK bus. Changed SOBEL_ENGINE to FILTER_ENGINE and
SOBEL_VDMA to FILTER_VDMA. Added information to the end of the table for
DVI2AXI_0, CRESAMPLE_0, and YUV2RGB_0 components. In Processor System
Reset Module, page 22, input to the proc_sys_reset core is generated by PS
Proc_sys_reset_1_N. In Clock Detect, page 23, FMC changed to FMC-IMAGEON.
The v_cresample, v_ycrcb2rgb, vsrc_sel, sobel_filter_top, and dvi2axi sections
were added. Starting in fmc imageon hdmi in, page 25, YCbCr was changed to
YCrCb. In Figure 2-4, added xFilter to the Device Drivers. In the Boot Loader
section, removed "HDMI in" chip. In xFilter, page 30, updated the introductory
text for clarity and reformatted the IOTCL arguments. Modified the description
of Figure 2-6 for clarity. Modified the descriptions of Figure 2-8 and Figure 2-9
for clarity and added description of cases 4, 5, and 6. Modified Software Sobel
Filter Processing, page 45 for clarity. Added xFilter sections to Xilinx Linux Kernel,
page 33. Figure 2-4, GUI for TRD Application was replaced and notes about the
GUI were added. AXI was added to the Plot Graph descriptions. DDR3 was
removed from Figure 2-8 and Figure 2-9. The Software Sobel Filter Processing,
page 45 description and API changed.
Appendix A, Register Description: New sections were added from Sobel Filter
Registers, page 46 to the end of the appendix. Removed redundant instances of
TPG.
Appendix C, Directory Structure: Figure C-1, Directory Structure, was updated.
Appendix F, Additional Resources: PG012, LogiCORE IP Chroma Resampler
Product Guide and PG014, LogiCORE IP YCrCb to RGB Color-Space Converter
Product Guide were added to references.
Appendix G, Regulatory and Compliance Information was added.
Appendix H, Warranty was added.

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11/12/2012 2.1 Updated for ISE® Design Suite 14.3.
Chapter 1, Introduction: Document and web site references changed throughout
the book. In Base TRD Key Features, page 11, 1 GB DDR3 running at 533 MHz was
removed.
Chapter 2, Functional Description: Figure 2-1 line colors changed. Table 2 -1 cell
values changed. Tab l e 2-2 Peripheral names changed. Under Clocking, page 19,
RGB2YUV block was removed. In Ta ble 2-6, the processor is ps7_0, and
PERF_MON_HP0, PERF_MON_HP2, VTC_0, and DVI2AXI_0 sections changed. The
dvi2axi Converter heading changed to dvi2axi on page 25. Figure 2-6 was
replaced and a GUI explanation added. Figure 2-7 was added to show minimized
GUI mode. In section Graphical User Interface, page 41, the File Browser and
Command Line Shell paragraphs were removed. The directory structure changed
in Figure C-1.
Appendix F, Additional Resources: Appendix was reorganized. A link was added
for the Master Answer Record for the ZC702 board.
Appendix G, Regulatory and Compliance Information: A Declaration of
Conformity link was added.
11/19/2012 2.1.1 Made typographical edits.
01/31/2013 3.0 Updated for ISE® Design Suite 14.4.
Chapter 2, Functional Description: Figure 2-1 was changed in the Performance
Monitor and TPG_0 areas. Table 2-1 changed Used 19,052 to 19,805, 42 to 43,
23,881 to 24,094, and % of Used 35 to 37. Table 2- 2, deleted PERF_MON_HP2 row
and renamed next row to PERF_MON_HP2_HP0_HP2. APU, page 17, end of
Cortex-A9 Core section added “For this TRD, both ARM cores run at 667 MHz.”
Table 2- 6, PERF_MON_HP0 changed to PERF_MON_HP0_HP2. In that same
section added new row SLOT_1_AXI_ACLK 150 0 Yes clk_150mhz and removed
PERF_MON_HP2 section. In TPG_0 section, changed clk to aclk, 148 to 150,
video_clk_int to clk_150mhz, S_AXI_ACLK to s_axi_aclk, and DVI2AXI_0 section to
VID_IN_AXI4S. Reset Module changed to Processor System Reset Module,
page 22. AXI VDMA Video Direct Memory Access, page 21 changed to AXI Video
Direct Memory Access. Heading VTC on page 22 changed to Video Timing
Controller. In the same section, VTC IP in last paragraph changed to “Video
Timing Controller IP.” Added final sentence in that section “For detailed
information on ...”. The TPG section changed to Test Pattern Generator, page 24.
Section logiCVC-ML, page 25 was added. In AXI Performance Monitor, page 25
added the final sentence, “For more information...” In Chroma Resampler,
page 26 edited the last sentence and added “and licensing information ...” AXI
Performance Monitor, page 25 changed Instance: PERF_MON_HP0_HP2 and
dropped ‘s’ at Instance. The last sentence in the same section changed from “Two
AXI Performance Monitors are instantiated” to “Two slots of AXI Performance
Monitors are used.” Video Multiplexer, page 26 added the final sentence “For
detailed information ...” The dvi2axi section on page 25 was removed. Figure 2-4
changed “Xilinx DMA” block to “Xilinx AXI VDMA.” Tabl e 2-9 changed “core DMA”
to “Xilinx AXI VDMA.” XVDMA Driver, page 35 changed “Xilinx DMA” to “Xilinx
AXI VDMA.” XFILTER_STOP, page 31 bullet switched “On demand mode” with
“Continuous mode” in both sentences. Application, page 40 added a new
sentence at end “The Linux kernel is in SMP mode and both ...” Figure 2-6 and
Figure 2-7 were replaced. In Control and Decision Making, page 43 the bullet
“Sobel Filter (using the xFilter driver)” was added. In User Space Device Control,
page 44 deleted “Sobel filter” bullet.
Date Version Revision

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01/31/2013,
continued
3.0 Appendix A, Register Description: Removed the AXI TPG Registers section.
Modified Table A-1 and added a row for Bit Position 7.
Appendix C, Directory Structure: The directory structure in Figure C-1 changed.
Appendix F, Additional Resources: Added references for PG043 and PG103.
06/07/2013 4.0 Updated ISE Design Suite version 14.3 to version 14.5 throughout document.
Added chroma resampler and YCrCb to RGB color space converter IP, and
clarified third bullet under The Base Targeted AP SoC Reference Design, page 8.
Changed “Two AXI Performance Monitors” to “AXI Performance Monitor” under
Base TRD Key Features, page 11. Updated Figure 2-1, page 15, Clocking,
page 19, Table 2-6, page 20, Programmable Logic, page 19, to delete Clk_detect
references. Updated values in Table 2-1 , page 16. Tab l e 2 -4, page 1 8 with
VID_IN_AXI4s information. Added Video Color Space Formats, page 27. and I2C
Sub-system, page 27. Added Linux Boot, page 31 to replace earlier Boot loader
contents. Updated Tab l e 2-7, page 2 7 to add UIO, Imageon, ADV7511, and
ADV7611 information. Added ADV7511 V4L2 Driver, page 36 and Xylon Frame
Buffer Driver, page 37. Updated Figure 2-6, page 39 and Figure 2-7, page 40.
Updated User Space Device Control, page 44 with sobel_lib information, and
deleted reference to udriver.h file. Added Appendix B, Extended Display
Identification Data. Updated Figure C-1, page 56. Deleted “Set Up Linux System
Software Development tools” from Appendix E.
10/14/2013 5.0 Updated ISE Design Suite version 14.5 to Vivado Design Suite version 2013.2
throughout document. Changes quantiy of Axi Performance Monitors from two
to one under Base TRD Key Features, page 11. Updated Table 2-1 , page 16.
Deleted AXI TPG from Clocking, page 19. Updated the names of the instances in
Processor System Reset Module, page 22, AXI Interconnect, page 22, AXI Video
Direct Memory Access, page 23, Video Timing Controller, page 24, Test Pattern
Gene r ator, page 2 4, logiCVC-ML, page 25, AXI Performance Monitor, page 25,
fmc imageon hdmi in, page 25, Chroma Resampler, page 26, YCrCb to RGB
Color-Space Converter, page 26, Video Multiplexer, page 26, Sobel Filter,
page 26, and Video In to AXI4-Stream, page 27. Added Sobel Edge Detection,
page 30. Updated Software Architecture, page 31. Updated Appendix C,
Directory Structure to reflect new updated directory structure. Added
Appendix D, PetaLinux Software Development Kit.
02/21/2014 6.0 Updated references to Vivado Design Suite version 2013.2 to version 2013.3
throughout document. Revised block description in Figure 2-1 from DMAS
channel to DMA 8 Channel. Revised the Instance description in the first column,
first row of Table 2-2. Corrected cross-reference to Figure 2-7 at the top of
page 42. Added autostart.sh to the directory structure shown in Figure C-1.
Revised the description in column two, row four in Tab l e C-1. Added Appendix D,
PetaLinux Software Development Kit. Revised Appendix F, Additional Resources
to conform to the board and kit document reference and style format du jour.
Date Version Revision

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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Chapter 1: Introduction
The Base Targeted AP SoC Reference Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Base TRD Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 2: Functional Description
Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Appendix A: Register Description
Sobel Filter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Appendix B: Extended Display Identification Data
Storing and Programming EDID data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Appendix C: Directory Structure
Included Files and Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Appendix D: PetaLinux Software Development Kit
Getting Started with the PetaLinux SDK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Appendix E: Install the Zynq-7000 AP SoC Design and Development Environment
Install the Xilinx Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Set Up Git Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Appendix F: Additional Resources
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Appendix G: Regulatory and Compliance Information
Declaration of Conformity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Appendix H: Warranty
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Chapter 1
Introduction
This user guide describes the Base Targeted Reference Design (TRD) based on Zynq®-7000
All Programmable SoC (AP SoC) architecture. The TRD is included with the ZC702 evaluation
kit. To learn more about the ZC702 evaluation kit and how to evaluate different
demonstrations based on Zynq-7000 AP SoC architecture, see the Zynq-7000
All Programmable SoC: ZC702 Evaluation Kit and Video and Imaging Kit Getting Started
Guide Zynq-7000 All Programmable SoC: ZC702 Evaluation Kit and Video and Imaging Kit
Getting Started Guide (UG926) [Ref 1].
This document explains the functional architecture of the hardware and software
components of the TRD. Also provided are register descriptions for IP/logic implemented in
programmable logic (PL), Base TRD package directory structure, and pointers to enable the
user to further develop embedded platforms based on Zynq-7000 AP SoC architecture.
To build hardware and software for the Base TRD, refer to the Xilinx Zynq-7000 Base
Targeted Reference Design webpage wiki.xilinx.com/zc702-base-trd.
The Base Targeted AP SoC Reference Design
The Base TRD showcases various features and capabilities of the Zynq-7000 AP SoC Z-7020
device for the embedded domain in a single package using a Xilinx standard Zynq platform
Linux-based video pipeline design.
The Base TRD consists of two processing elements: the Zynq-7000 AP SoC processing
system (PS) and a video accelerator based on PL. The AP SoC allows the user to implement
a specific functionality either as a software program running on the Zynq-7000 AP SoC PS
or as a hardware design inside the PL. The Base TRD demonstrates an optimization of how
the user can seamlessly switch between a software or a hardware implementation,
contributing to ease of use. The TRD also demonstrates the value of offloading
computation-intensive tasks onto PL, thereby freeing the CPU resources available for
user-specific applications.
Software developers can leverage the Base TRD and start programming immediately using
the widely known Eclipse-based integrated development environment (IDE), GNU compiler
tool chain, Linux operating system (OS), and libraries. Embedded hardware designers now
have immediate access to the industry standard ARM® Cortex™-A9 core processor system
and video IPs running on PL out of the box. In addition, the TRD also provides customers
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The Base Targeted AP SoC Reference Design
with access to the various PL-based video components such as video direct memory access
(VDMA), video timing controller (VTC), video test pattern generator (TPG), Sobel filter and
the Xylon logiCVC-ML display controller (www.logicbricks.com/Products/logiCVC-ML.aspx).
These IPs are part of the video pipeline implemented in the PL.
The Base TRD consists of a PS based on the embedded ARM Cortex-A9 core processor, a
video processing pipeline implemented in PL, and a Linux-based software application that
includes a Qt-based graphical user interface (GUI) (doc.qt.nokia.com) to provide user
control and monitoring. The Linux-based software platform and software application run on
the ARM Cortex-A9 cores. The software application works in tandem with hardware and
provides the user the choice of offloading computation-intensive processing to the
PL-based hardware subsystem.
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The Base Targeted AP SoC Reference Design
The Zynq-7000 AP SoC Base TRD reference design (Figure 1-1) consists of these
components:
• A dual ARM Cortex-A9 core processor-based embedded Linux OS, board support
package (BSP), and U-Boot boot loader
• PL-based hardware IPs that enable acceleration of computation-intensive video
processing tasks
• Linux application to configure and control the video IPs in the PL and the PS
The TRD deliverables include source code for RTL design and software packages such as the
Linux OS, device drivers, the application, and the GUI.
Note: The camera supplied with the video kit is not supported with the TRD.
X-Ref Target - Figure 1-1
Figure 1-1: Zynq-7000 AP SoC Base TRD System Block Diagram
Linux User Space
Linux Kernel
Processing
System
Qt-Based Multithreaded Application
Kernel Libraries and Utilities Device Drivers
DDR Memory Controller
Programmable
Logic
Display Controller
Video Test Pattern
Generator
Video
Output
UG925_c1_01_061913
S_AXI3_HP 64 bit
M_AXI3_GP 32 bit
Video Processing
(Sobel Filter)
APU
AMBA Switches
AMBA Switches
(Optional)
Video Input
with
Zynq-7000
Video and
Imaging Kit
Command Line Application
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Base TRD Key Features
Base TRD Key Features
Components in the Base TRD are further described in this section.
The Base TRD processing system (PS) includes:
•AdualARMCortex-A9core
• ARM AMBA® AXI interconnect
• Multi-protocol, 32-bit DDR DRAM controller
• Standard peripheral interfaces including USB, Ethernet, UART, I2C, SD MMC, and GPIO
Base TRD programmable logic includes:
• AXI interconnects, 64-bit wide at 150 MHz
• One AXI interconnect, 32-bit wide at 75 MHz
•AXIVDMA(s)
• A full HD video input and output interface
• A Sobel accelerator
• AXI Performance Monitor
Base TRD software includes:
• Xilinx Zynq-7000 standard Linux kernel (based on Open Source Linux 3.x)
• Linux device drivers for TRD-specific IPs
• Qt-based Linux application demonstrating the video processing pipeline
List of Acronyms
Tabl e 1-1 lists acronyms used in this document.
Table 1-1: Acronyms
Acronym Definition
AFI AXI FIFO interface
APU Application processor unit
BSP Board support package
COR Clear on read
DTB Device tree binary
DTS Device tree source
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Base TRD Key Features
EDK Embedded Development Kit
AP SoC All Programmable SoC
FMC FPGA mezzanine card
FPS Frames per second
FSBL First-stage boot loader
GIC General interrupt controller
GUI Graphical user interface
HD High definition
IDE Integrated development environment
IOP Input/output peripherals
IP Intellectual property
JTAG Joint Test Action Group
KFLOPS Kilo floating-point operations per second
NVM Nonvolatile memory
OCM On-chip memory
OS Operating system
PL Programmable logic (inside the Zynq-7000 AP SoC)
PS Processing system
RReadonly
RTL Register transfer level
RW Read/write
SC Self clear
SD Secure Digital
SD MMC Secure Digital Multimedia Card
SDK Software Development Kit
SoC System on Chip
TDP Targeted Design Platform
TPG (Video) Test Pattern Generator
TRD Targeted Reference Design
TTC Triple-timer counter
VDMA Video direct memory access
VTC Video timing controller
Table 1-1: Acronyms (Cont’d)
Acronym Definition
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Base TRD Key Features
XPS Xilinx Platform Studio
ZC702 Platform development board based on the Zynq AP SoC Z-7020 device
Zynq Z-7020 An implementation of the Zynq-7000 AP SoC with a fixed feature set and
PL capabilities
Table 1-1: Acronyms (Cont’d)
Acronym Definition
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Chapter 2
Functional Description
This chapter describes the Zynq-7000 AP SoC ZC702 Base Targeted Reference Design
(TRD) hardware design, software system, and video demonstration application components.
It also describes how data flows through the various connected IPs and includes
information about the flow of application control.
To build hardware and software for the Base TRD, refer to the Xilinx Zynq-7000 Base
Targeted Reference Design wiki page wiki.xilinx.com/zc702-base-trd.
Hardware Architecture
The block diagram for the Base TRD is shown in Figure 2-1. This design has two parts:
• Processing system (PS)
• Video IPs and custom logic implemented in programmable logic (PL)
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Hardware Architecture
X-Ref Target - Figu re 2-1
Figure 2-1: Zynq-7000 AP SoC Base TRD Hardware Block Diagram
UG925_c2_01_020514
Bank0
MIO
(15:0)
I/O Peripherals
FLASH Memory
Interfaces
Clock
Generation
SPI 0
SPI 1
I2C 0
I2C 1
CAN 0
CAN 1
UART 0
UART 1
GPIO
SD 0
SD 1
USB 0
USB 1
Enet 0
Enet 1
SRAM/NOR
NAND
Quad SPI
Bank1
MIO
(53:16)
Input Clock
and Freq
Extended
MIO (EMIO) PS to PL
Clock Ports
PS I2C-1
(EMIO)
I/O
MUX
(MIO)
Reset
Processing System (PS)
DAP
DEVC
IRQ
Programmable
Logic to Memory
Interconnect
High Performance
AXI 32b/64b
Slave Ports
Memory Interfaces
DDR2/3, LPDDR2
Controller
SWDT
TTC
DMA 8
Channel
GIC Snoop Control Unit
MMU
NEON/FPU Engine
Application Processor Unit (APU)
32 KB I
Cache
32 KB D
Cache
Cortex-A9
MPCore
CPU
MMU
NEON/FPU Engine
32 KB I
Cache
32 KB D
Cache
Cortex-A9
MPCore
CPU
CoreSight
Components
System
Level
Control
Regs
Central
Interconnect
AXI Interconnect AXI Interconnect
64b
AXI ACP
Slave
Port
OCM
Interconnect
255 KB OCM
512 KB L2 Cache and Controller
BootROM
32b GP
AXI
Master
Ports
32b GP
AXI
Slave
Ports
12 13 14 15
8 9 10 11
4 5 6 7
0 1 2 3
0 1 2 3
0 1 2 3
S
M M M M M M M M Slave Slave
AXI Interconnect
Slave Slave
MasterMaster
Perf
Mon
DMA Sync
LOGICVC_0
TPG VDMA MM2S S2MM
Sobel VDMA
Sobel Filter
CRESAMPLE_0HDMI_IN
Video
In
1080p Video
Out
1080p
Local Pcore
EDK IP
Third Party IP
CORE Generator EDK IP
AXI Interface
Video Interface
AXI Streaming
Interface
S2MM
M
YUV2RGB_0
VTC_0
VIDEO_MUX_0
Video Sync Signals
Monitor
TPG_0
VID_IN_AXI4S
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Hardware Architecture
This system is implemented in a Zynq-7000 AP SoC device (XC7Z020-CLG484-1) using
Vivado® Design Suite, version 2013.3 tools.
The PL hardware utilization for the implemented design is shown in Table 2 -1.
The PL-implemented video IP and custom logic address map is shown in Table 2-2.
System Configuration
Processing System
This design makes full use of these four major components in the PS:
• Application processor unit (APU)
• Interconnect
• Input/output peripherals (IOP)
•Memoryinterfaces
Table 2-1: PL Hardware Utilization for Device XC7Z020-CLG484-1(1)
FPGA Components Total Available Used % Used
LUTs 53,200 20,992 39
I/Os 200 43 21
Slice registers 106,400 28,212 26
FPGA Logic Memory
RAMB36/FIFO 140 45 32
RAMB18 280 14 5
Notes:
1. The figures provided here are only indicative of nature and can vary between different tool chain versions.
Table 2-2: FPGA Logic Address Map for the Zynq-7000 AP SoC ZC702 Base TRD
Instance Peripheral Base Address High Address
system_top_i/VTC_0 axi_vtc 0x40070000 0x4007FFFF
TPG_0 axi_tpg 0x40080000 0x4008FFFF
TPG_VDMA axi_vdma 0x40090000 0x4009FFFF
FILTER_VDMA axi_vdma 0x400B0000 0x400BFFFF
LOGICVC_0 LogiCVC 0x40030000 0x4003FFFF
PERF_MON_HP0_HP2 axi_perf_mon 0x400F0000 0x400FFFFF
CRESAMPLE_0 v_cresample 0x40040000 0x4004FFFF
YUV2RGB_0 v_ycrcb2rgb 0x40050000 0x4005FFFF
FILTER_ENGINE sobel_filter_top 0x400D0000 0x400DFFFF
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Hardware Architecture
This section describes some of the features of the PS used in this design. For detailed
information about the complete feature set including a functional description, see the
Zynq-7000 All Programmable SoC Technical Reference Manual (UG585) [Ref 2].
APU
The APU includes the dual ARM Cortex-A9 core processor, snoop control unit (SCU), L2
cache controller, on-chip memory (OCM), 8-channel DMA, system watchdog timer (SWDT),
and triple-timer controller (TTC) blocks.
Cortex-A9 Core - The ARM Cortex-A9 core processor implements the ARMv7 architecture
and runs 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions, and 8-bit Java byte
codes in the Jazelle state. The media processing engine implements ARM NEON
coprocessor technology, a single instruction multiple data (SIMD) architecture that adds
instructions targeted at audio, video, 3D graphics, image, and speech processing. For this
TRD, both ARM cores run at 667 MHz.
General Interrupt Controller - The GIC collects interrupts from various sources and
distributes these interrupts to each of the ARM cores. The interrupt distributor holds the list
of pending interrupts for each ARM Cortex-A9 core processor and then selects the highest
priority interrupt before issuing it to the Cortex-A9 processor interface. Interrupts of equal
priority are resolved by selecting the lowest ID. A total of 64 shared peripheral interrupts (PL
interrupts + PS I/O peripheral interrupts) are supported, starting from ID 32. Table 2-3 lists
interrupt IDs for interrupts coming from PL.
Interconnect
The interconnect unit connects all PS and PL master and slave devices. There are a total of
six Advanced eXtensible Interface (AXI) slave ports dedicated for AXI masters residing in the
PL, and four of these ports contain deep FIFOs to improve data throughput. Two AXI master
ports provide access to AXI slaves in the PL. In this design, masters in PL are connected
through two AXI slave ports with deep FIFOs. One AXI master port is used to access
registers in AXI slave IPs in PL.
An advanced peripheral bus (APB) master port is provided for accessing software
programmable registers of all PS modules. The top level switch is AXI3-compliant, the soft
Table 2-3: Interrupt IDs for PL-Generated Interrupts
Interrupt line ID Type Instance
CVC_DISPLAY_interrupt 91 Level CVC_DISPLAY
TPG_VDMA_s2mm_introut 90 Level TPG_VDMA
FIILTER_VDMA_s2mm_introut 89 Level FIILTER_VDMA
FIILTER_VDMA_mm2s_introut 88 Level FIILTER_VDMA
FILTER_0_interrupt 87 Level FILTER_ENGINE
ADV7511 HPD interrupt 86 Level HDMI_O_INT
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Hardware Architecture
IPs provided by Xilinx are AXI4-compliant, and the soft AXI interconnect IP provides
protocol bridging as needed.
S_AXI_HP - The high performance slave AXI interfaces (S_AXI_HP) connect the PL to AFI
blocks in the PS. The PL has four AXI masters out of which two are connected to the
S_AXI_HP0 port and two are connected to the S_AXI_HP2 port. The HP port enables a high
throughput data path between AXI masters in the programmable logic and the processing
system's DDR3 memory. The main aim of the AXI FIFO interface (AFI) units is to smooth out
this variable latency, allowing the ability to stream data continuously from DDR to the PL
masters and from the PL masters to DDR. The PL-side interface of AFI runs on the clock
coming from the PL. In this design, a 150 MHz clock is connected from the PL side. The
DDR-side clock is running on 2/3 of the DDR_CLK (533 MHz). The high performance AXI
interface module provides several hooks to assist in bandwidth management of masters
connected to different PL ports. Controlling issuance capability available from the PL port is
one of the hooks exercised in this design to obtain a fair share of bandwidth between two
masters, SOBEL VDMA, and the display controller.
M_AXI_GP - This AXI master port interfaces with AXI slave IPs in PL through an AXI Lite
interconnect. The CPU manages initializing and controlling the video pipeline through this
port.
IOP - The IOP unit includes communication peripherals. GPIO, Ethernet, USB, I2C, and SD
controllers from the PS are used extensively in this design.
GPIO - The 64-bit general purpose input/outputs (GPIOs) are connected to the PL through
the extendable multiplexed I/O (EMIO) interface. Sixty-four bits are divided into two banks,
each of 32 bits. Because each GPIO bit can be dynamically configured as input or output,
GPIO bits are used in this design for a variety of functions. Table 2-4 lists the GPIO bit and
purpose in design.
Memory Interfaces
The memory interfaces unit includes the DDR memory controller and nonvolatile memory
(NVM) controllers. The DDR memory controller includes a 4-port arbiter. One AXI port is
dedicated for ARM CPU access and two ports are dedicated for high performance AXI
interface master devices in the programmable logic. The remaining port is shared by all
Table 2-4: GPIO Bits Functional Description
GPIO Bit
Number Net Name Purpose
0 ps7_0_GPIO_O[0] Resets video receiving block VID_IN_AXI4s
1 ps7_0_GPIO_O[1] Resets Sobel filter block
3 ps7_0_GPIO_O[3] Selects a line for the video multiplexer—either the external video
source or the internally generated test pattern
6 ps7_0_GPIO_O[6] FMC-IMAGEON I2C multiplexer reset
2, 4, 5, 7 N/A N/A
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Hardware Architecture
other AXI masters. In this design, DDR3 is configured to run at 533 MHz, and the AXI
interface is running at 355 MHz.
PL Clocks
The PS provides four fully programmable clocks (FCLK_CLK) to the PL. These clocks are
routed directly to PL clock buffers to serve as a frequency source for the PL. The clock
generator module in PL gets a 100 MHz clock from FCLK_CLK0.
PL Reset
The PS provides four FCLK_RESET[3:0]_N fully programmable reset signals to the PL. These
signals are asynchronous to PS clocks. The PL logic reset block in this design receives input
from FCLK_RESET0_N and generates necessary reset signals for the design implemented in
PL.
Programmable Logic
Clocking
The FPGA logic design has three clock domains: AXI MM (memory-mapped) interconnect,
AXI register interface, and video clock. These domains run at 150 MHz, 75 MHz, and
148.5 MHz, respectively.
The clock generator module receives a 100 MHz input clock from the PS FCLK_CLK0 and
generates 75 MHz and 150 MHz. The AXI Lite interconnect works on 75 MHz. Apart from
the AXI Lite interconnect, the register interface of AXI VDMA, AXI TPG, logiCVC-ML, VTC,
and perf_monitor are driven by the 75 MHz clock.
Two instances of the AXI_MM interconnect connected to the HP port of the PS run on
150 MHz. The S2MM (stream to memory map) and MM2S (memory map to stream)
channels of VDMAs are running at 150 MHz. The 150 MHz clock drives the logiCVC-ML
memory read interface and also the AXI slave interface of the Sobel filter.
The video clock comes from the onboard clock synthesizer or the FMC-IMAGEON card.
BUFGMUX dynamically selects which video clock source drives logic running on the video
clock domain. The VTC, VID_IN_AXI4S, and logiCVC-ML blocks run on the video clock.
Tabl e 2-5 lists system clocks.
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Hardware Architecture
Based on user clock configuration inputs, the clock generator determines the correct
configuration of the PLLs.
Tabl e 2-6 shows clock requirements of master and slave peripherals connected in system
and their connection.
Table 2-5: System Clocks
Clock Signal Source Frequency Use
FPGA_CLK PS - FCLK_CLK0 100 MHz Input clock to clock
generator
clk_75mhz Internal mixed-mode clock
manager (MMCM)
75 MHz Clock for AXI Lite
interconnect, generated
by clock generator
clk_150mhz Internal MMCM 150 MHz Clock for AXI MM
interconnect, generated
by clock generator
VIDEO_CLK_P, VIDEO_CLK_N External differential video
clock coming from clock
synthesizer on board
148.5 MHz Clock for display
controller and video
receiving blocks
fmc_imageon_in_0_clk_pin External video clock coming
from Imageon FMC
148.5 MHz Clock for video receiving
modules
Table 2-6: PL Clock Configuration
Component Frequency (MHz) Phase Buffered Connection
clock_generator_0
•CLKIN 100 Yes FPGA_CLK
•CLKOUT0 75 Yes clk_75mhz
•CLKOUT1 150 Yes clk_150mhz
VIDEO_MUX_0
• video_clk_1 148.5 0 Yes VIDEO_CLK
• video_clk_2 148.5 0 Yes fmc_imageon_hdmi_in_0_clk_pin
• video_clk 148.5 0 Yes video_clk_int
Processor
ps7_0
• FCLK_CLK0 100 0 Yes FPGA_CLK
• M_AXI_GP0_ACLK 75 0 Yes clk_75mhz
• S_AXI_HP0_ACLK 150 0 Yes clk_150mhz
• S_AXI_HP2_ACLK 150 0 Yes clk_150mhz
Buses
axi4_0
• INTERCONNECT_ACLK 150 0 Yes clk_150mhz
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