Xilinx ZC702 User manual

ZC702 Evaluation Board
for the Zynq-7000 XC7Z020
All Programmable SoC
User Guide
UG850 (v1.3) June 4, 2014

ZC702 Board User Guide www.xilinx.com 2
UG850 (v1.3) June 4, 2014
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Revision History
The following table shows the revision history for this document.
Date Version Revision
05/24/2012 1.0 Initial Xilinx release.
10/08/2012 1.1 The board photo in Figure 1-2 was updated. Table 1 - 2, Switch SW16 Configuration
Option Settings was added. The part number in Quad-SPI Flash Memory, page 20
changed to N25Q128A13ESF40F. In Ta b l e 1-6, the J35 shunt controls OTG and
Device mode. The frequency jitter in System Clock, page 28 changed from 20 ppm
to 50 ppm. The action description under Program_B Pushbutton, page 49 changed.
The 34 differential user-defined signals are defined as 34 LA pairs, LA00–LA33, in
LPC Connectors J3 and J4, page 51. In the same section, 34 differential user-defined
pairs changed to 68 single-ended or 34 differential user-defined signals.
Appendix F, Regulatory and Compliance Information now includes a link to the
Declaration of Conformity and markings for waste electrical and electronic
equipment (WEEE), restriction of hazardous substances (RoHS), and CE compliance.

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UG850 (v1.3) June 4, 2014
04/04/2013 1.2 Chapter 1, ZC702 Evaluation Board Features: Marvell 88E1111 was changed to
Marvell 88E1116R throughout the document. The bullet just before Block Diagram,
page 9 changed from PL JTAG header to PS JTAG header. In Ta b l e 1-1, page 11,
callout 3, PC28F00AG18FE StrataFlash memory changed to 128 Mb,
N25Q128A11ESF40G. In callout 9, Marvell M88E1116R-BAB1C000 changed to
88E1116RA0-NNC1C000. Callout 30 for J59 and 31 for J60 were added. The
Zynq-7000 XC7Z020 AP SoC, page 12 description for callout 1 changed. Callout 29
added a link to Tab le 1-2. Table 1-2 was removed because it is a duplicate of
Table 1-10. Above Ta ble 1-2 , pa ge 15 , “configuration option” was changed to “JTAG
configuration option.” In Ta ble 1- 2, the PLL Used mode row was removed and the
default setting changed. Section Encryption Key Backup Circuit, page 16 was added.
In I/O Voltage Rails, page 17, “There are four I/O banks available on the XC7Z020
AP SoC” was changed to “There are four PL I/O banks available on the XC7Z020 AP
SoC.” A note about DDR3 memory was added after Table 1-4, pa ge 17. In Quad-SPI
Flash Memory, page 20 and Figure 1-6, N25Q128A13ESF40F (Micron/Numonyx)
changed to N25Q128A11ESF40G. In Quad-SPI Flash Memory, page 20, “The
configuration section of UG585...” was changed to add “The configuration and QSPI
section of UG585...” JTAG information in Figure 1-10 and Table 1-1 0 was updated.
In Figure 1-10 pin numbers 5 and 6 are swapped and in U76, IN2 and IN1 switched
places. In Tabl e 1 -10 , SW10 became SW10[1:2] in the table column heading and the
default setting was added. In Processing System Clock Source, page 29, frequency
jitter changed from 20 ppm to 50 ppm. In I2C Bus, page 36, NXP semiconductor
changed to TI. Figure 1-15 is updated. R249 was added to Figure 1-17. In
Table 1-22, reference designator DS12 changed to DS14. U3 level shifter was
changed to TXS0104E in Figure 1-19 and Ta b l e 1 -21. The User I/O, page 42 section
was updated. Figure 1-21 added two LEDs. Table 1-23 added Net Name PS_LED1
and PS_MIO8_LED0 and removed pin info. Section User PS Switches, page 47 was
added. The Figure 1-26 title changed. A paragraph about design criteria was added
to Power Management, page 55. A paragraph about the TI Fusion Digital Power
graphical user interface precedes Table 1- 3 0 . Voltages were added to the
description of U19 in Tab le 1-30. The TI link on page 58 was updated.
Appendix A, Default Switch and Jumper Settings: In Table A-1, SW16 position 4
changed from right to left.
Appendix C, Master Constraints File Listing: A reminder was added to use the latest
UCF listing. Minor changes were made to the list, and power and ground pin
constraints were removed.
Appendix D, Board Specifications: This appendix was added to the book.
Appendix F, Regulatory and Compliance Information: A link to the ZC702 board
master answer record was added.
06/04/2014 1.3 Table 1-6 USB Jumper Settings was updated to highlight default shunt positions.
GND changed to GA0 = 0 = GND in Tab l e 1-2 8 and Ta b l e 1 -28. The Appendix C
Master UCF Listing was replaced with the Xilinx Design Constraints (XDC) file listing.
The link in Declaration of Conformity was updated.
Date Version Revision

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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: ZC702 Evaluation Board Features
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ZC702 Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Feature Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Zynq-7000 XC7Z020 AP SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Encryption Key Backup Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
I/O Voltage Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
DDR3 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Quad-SPI Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
USB 2.0 ULPI Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
SD Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Programmable Logic JTAG Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Programmable Logic JTAG Select Switch, JTAG Cable Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
FMC Connector JTAG Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Programmable User Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Processing System Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
10/100/1,000 MHz Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Ethernet PHY Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
USB-to-UART Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
HDMI Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
I/O Expansion Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
High Speed CAN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Ethernet PHY User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
User Pushbuttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
GPIO DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
User PS Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
User PMOD GPIO Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Power On/Off Slide Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Program_B Pushbutton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
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PS Power-On and System Reset Pushbuttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
FPGA Mezzanine (FMC) Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
LPC Connectors J3 and J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
VADJ Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Monitoring Voltage and Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Cooling Fan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
XADC Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Appendix A: Default Switch and Jumper Settings
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Appendix B: VITA 57.1 FMC Connector Pinouts
Appendix C: Master Constraints File Listing
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
ZC702 Board Constraints File Listing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Appendix D: Board Specifications
Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Humidity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Operating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Appendix E: Additional Resources
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Appendix F: Regulatory and Compliance Information
Declaration of Conformity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
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Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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Chapter 1
ZC702 Evaluation Board Features
Overview
The ZC702 evaluation board for the XC7Z020 All Programmable SoC (AP SoC) provides a
hardware environment for developing and evaluating designs targeting the Zynq®
XC7Z020-1CLG484C device. The ZC702 board provides features common to many
embedded processing systems, including DDR3 component memory, a tri-mode Ethernet
PHY, general purpose I/O, and two UART interfaces. Other features can be supported using
VITA-57 FPGA mezzanine cards (FMC) attached to either of two low pin count (LPC) FMC
connectors.
ZC702 Board Features
The ZC702 board features are listed in here. Detailed information for each feature is
provided in Feature Descriptions starting on page 12.
• Zynq XC7Z020-1CLG484C device
• 1 GB DDR3 component memory (four 256 Mb x 8 devices)
• 128 Mb Quad SPI flash memory
• USB 2.0 ULPI (UTMI+ low pin interface) transceiver
• Secure Digital (SD) connector
• USB JTAG interface via Digilent module
• Clock sources:
°Fixed 200 MHz LVDS oscillator (differential)
°I2C programmable LVDS oscillator (differential)
°Fixed 33.33 MHz LVCMOS oscillator (single-ended)
• Ethernet PHY RGMII interface with RJ-45 connector
• USB-to-UART bridge
•HDMIcodec
•I
2C bus
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Overview
•I
2C bus multiplexed to:
°Si570 user clock
°ADV7511 HDMI codec
°M24C08 EEPROM (1 kB)
°1-To-16 TCA6416APWR port expander
°RTC-8564JE real time clock
°FMC1 LPC connector
°FMC2 LPC connector
°PMBUS data/clock
•StatusLEDs:
°Ethernet status
°Power good
°FPGA INIT
°FPGA DONE
•UserI/O:
°Two programmable logic (PL) user pushbuttons
°PL user DIP switch (2-pole)
°Eight PL user LEDs
°Two processing system (PS) pushbuttons shared with PS 2-pole DIP switch
°Two PS user LEDs
°Dual row Pmod GPIO header
°Single row Pmod GPIO header
• AP SoC PS Reset Pushbuttons:
°SRST_B PS reset button
°POR_B PS reset button
• Two VITA 57.1 FMC LPC connectors
• Power on/off slide switch
• Power management with PMBus voltage and current monitoring via TI power
controllers
• Dual 12-bit 1 MSPS XADC analog-to-digital front end
• Configuration options:
Send Feedback

ZC702 Board User Guide www.xilinx.com 9
UG850 (v1.3) June 4, 2014
Overview
°Quad SPI flash memory
°USB JTAG configuration port (Digilent module)
°Platform cable header JTAG configuration port
°20-pin PL PJTAG header
°20-pin PS JTAG header
Block Diagram
The ZC702 board block diagram is shown in Figure 1-1.
X-Ref Target - Figu re 1-1
Figure 1-1: ZC702 Board Block Diagram
U1
Zync-7000 AP SoC
XC7Z020-1CLG484C
Processing
System
Programmable Logic
UG850_c1_01_081612
JTAG Module
and
Connector
Page 15
Quad SPI
Flash Memory
Page 20
CAN Bus
Page 21
SD Card
Connector
Page 22
FMC1 LPC
Connector
Page 23
10/100/1,000
Ethernet PHY
(RGMII only)
Page 26
USB 2.0 ULPI
Transceiver
and Connector
Page 27
JTAG Header
Page 15
USB UART
Page 36
ARM PJTAG
Header
Page 35
Switches
LEDs and
Pushbuttons
Page 34
Mechanicals
Page 38
I2C
Real Time
Clock
Page 33
Clock and
Reset/POR
Pushbuttons
Page 14
DDR3 Memory
4 x 256 Mb x 8
SDRAM
Pages 16-19
HDMI Codec
and
Connector
Page 28, 29
I2C Multiplexer
and
I2C EEPROM
Page 32
XADC
Header
Page 31
Configurable
Clocks
Page 30
FMC2 LPC
Connector
Page 24
Note: Page numbers reference the page number of schematic 0381449.
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ZC702 Board User Guide www.xilinx.com 10
UG850 (v1.3) June 4, 2014
Overview
Board Layout
Figure 1-2 shows the ZC702 board. Each numbered feature that is referenced in Figure 1-2
is described in Tab le 1 -1 with a link to detailed information provided under Feature
Descriptions starting on page 12. Note that the image in Figure 1-2 is for reference only
and might not reflect the current revision of the board.
CAUTION! The ZC702 board can be damaged by electrostatic discharge (ESD). Follow ESD prevention
measures when handling the board.
X-Ref Target - Figu re 1-2
Figure 1-2: ZC702 Board Component Locations
15
25
14
1
3
5
20
21
26
19
24 24
16
2
18
8
7
23
22
10
4
6
9
11
12
13
25
28
27
29
18
17
30
31
00 Square callout references a component
on the back side of the board
Round callout references a component
on the front side of the board
00
UG850_c1_02_032013
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ZC702 Board User Guide www.xilinx.com 11
UG850 (v1.3) June 4, 2014
Overview
Table 1-1: ZC702 Board Component Descriptions
Callout Reference
Designator Component Description Notes
Schematic(1)
0381449
Page
Number
1U1 Zynq-7000 XC7Z020 AP SoC Xilinx part number:
XC7Z020-1CLG484C
2U66–U69 DDR3 Component Memory, 1 GB 4 each 256Mb X 8 SDRAM Micron
Technology Inc, MT41J256M8DA-107 16–19
3U41 Quad-SPI Flash Memory, 128 Mb Micron/Numonyx
N25Q128A11ESF40G 20
4U9, J1 USB 2.0 ULPI Transceiver, USB
Mini-B connector
SMSC USB3320-EZK High-Speed USB
transceiver 27
5J64 SD Card Interface connector Molex 67840-8001 SDIO Memory
card connector 22
6
U23
Programmable Logic JTAG
Programming Options with
integrated Micro-B connector
Digilent USB JTAG Module 15
7U43 System Clock, 200 MHz, 2.5V
LVDS oscillator SiTime SIT9102-243N25E200.0000 30
8
U28, U65 Programmable User Clock and
Processing System Clock Source
Silicon Labs SI570BAB0000544DG,
default 156.250MHz, PS fixed 33 MHz
clock
30
9U35, P2 10/100/1,000 MHz Tri-Speed
Ethernet PHY, RJ45 w/magnetics
Marvell 88E1116RA0-NNC1C000,
Halo HFJ11-1G01ERL 25–26
10 X1 Ethernet PHY Clock Source,
25.000 MHz Epson MA-506-25.000m-CO:ROHS 25
11 DS6–DS8 Ethernet PHY User LEDs Ethernet PHY User LEDs, GREEN 25
12 U36, J17 USB-to-UART Bridge, USB Mini-B
connector
Silicon Labs CP2103GM, Molex
54819-0589 36
13
U40, P1 HDMI Video Output
Analog Devices ADV7511KSTZ-P
HDMI transmitter, Molex
500254-1927 HDMI receptacle
28–29
14 U44 I2C Bus TI PCA9548ARGER 32
15 U16 Real Time Clock Epson RTC-8564JE:3:ROHS 33
16 J54 I/O Expansion Header driven
from I2C Expander U80 2-row pin header 33
17 DS15–DS22 User LEDs GPIO LEDs, GREEN 0603 34
18 SW5, SW7 User Pushbuttons SW5 = Left,
SW7 = Right E-Switch TL3301EP100QG 34
19 SW12 GPIO DIP Switch 2-pole C&K SDA02H1SBD 34
20 SW11 Power On/Off Slide Switch C and K 1201M2S3AQE2 47
21 U14 High Speed CAN Transceiver NXP TJA1040T/VM 21
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ZC702 Board User Guide www.xilinx.com 12
UG850 (v1.3) June 4, 2014
Feature Descriptions
Feature Descriptions
Detailed information for each feature shown in Figure 1-2 and listed in Tab le 1 -1 is
provided in this section.
Zynq-7000 XC7Z020 AP SoC
[Figure 1-2, callout 1]
The ZC702 board is populated with the Zynq-7000 XC7Z020-1CLG484C AP SoC. The
XC7Z020 AP SoC consists of an SoC-style integrated processing system (PS) and
programmable logic (PL) on a single die.
22 SW4 Program_B Pushbutton E-Switch TL3301EP100QG 34
23 SW10, J2 Programmable Logic JTAG Select
Switch, JTAG Cable Connector
2-pole C and K SDA02H1SBD
MOLEX 87832-1420 15
24 J3, J4 FPGA Mezzanine (FMC) Card
Interface Samtec ASP_134486_01 23, 24
25 U32, U33, U34 Power Management (bottom
and top of board)
TI UCD9248PFC in conjunction with
various regulators 39–47
26 J40 XADC Analog-to-Digital
Converter 2X10 0.-inch male header 31
27 SW1, SW2 PS Power-On and System Reset
Pushbuttons Panasonic EVQ-11L07K 14 35, 36
28 J62, J63 User PMOD GPIO Headers J63 2 x 6 0.1 inch J63 1 x 6 0.1 inch
male headers 34, 35
29 SW16 5-pole SPDT MIO DIP switch CTS 206-125. See Table 1- 2 for switch
settings. 14
30 J59 2x5 shrouded PMBus connector
(bottom of board) ASSMAN HW10G-0202 47
31 J60 12V power input 2x6 connector MOLEX 39-30-1060 47
Notes:
1. The ZC702 board schematics are available for download. See ZC702 Evaluation Kit.
Table 1-1: ZC702 Board Component Descriptions (Cont’d)
Callout Reference
Designator Component Description Notes
Schematic(1)
0381449
Page
Number
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ZC702 Board User Guide www.xilinx.com 13
UG850 (v1.3) June 4, 2014
Feature Descriptions
The high-level block diagram is shown in Figure 1-3.
The PS integrates two ARM® Cortex™-A9 MPCore™ application processors, AMBA®
interconnect, internal memories, external memory interfaces, and peripherals including
USB, Ethernet, SPI, SD/SDIO, I2C, CAN, UART, and GPIO. The PS runs independently of the PL
and boots at power-up or reset.
X-Ref Target - Figure 1-3
Figure 1-3: High-Level Block Diagram
Application
Processor Unit (APU) Common
Peripherals
Custom
Peripherals
Common Accelerators
Custom Accelerators
Memory
Interfaces
Processing
System
(PS)
Programmable
Logic
(PL)
Input Output
Peripherals
(IOP)
High-Bandwidth
AMBA®AXI Interfaces
UG850_c1_03_081612
Interconnect
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ZC702 Board User Guide www.xilinx.com 14
UG850 (v1.3) June 4, 2014
Feature Descriptions
A system level block diagram is shown in Figure 1-4.
For additional information on Zynq-7000 AP SoC devices, see the Zynq-7000 All
Programmable SoC Overview (DS190) [Ref 1], and the Zynq-7000 All Programmable SoC
Technical Reference Manual (UG585) [Ref 9] for more information about Zynq-7000 AP SoC
configuration options.
Device Configuration
Zynq-7000 XC7Z020 AP SoC uses a multi-stage boot process that supports both a
non-secure and a secure boot. The PS is the master of the boot and configuration process.
For a secure boot, the PL must be powered on to enable the use of the security block
located within the PL, which provides 256-bit AES and SHA decryption/authentication.
X-Ref Target - Figu re 1-4
Figure 1-4: Zynq-7000 AP SoC Block Diagram
2x USB
2x GigE
2x SD
Zynq-7000 AP SoC
I/O
Peripherals
IRQ
IRQ
EMIO
SelectIO
Resources
DMA 8
Channel
CoreSight
Components
Programmable Logic
DAP
DevC
SWDT
DMA
Sync
Notes:
1) Arrow direction shows control (master to slave)
2) Data flows in both directions: AXI 32-Bit/64-Bit, AXI 64-Bit, AXI 32-Bit, AHB 32-Bit, APB 32-Bit, Custom
ACP
256K
SRAM
Application Processor Unit
TTC
System-
Level
Control
Regs
GigE
CAN
SD
SDIO
UART
GPIO
UART
CAN
I2C
SRAM/
NOR
ONFI 1.0
NAND
Processing System
Memory
Interfaces
Q-SPI
CTRL
USB
GigE
I2C
USB
SD
SDIO
SPI
SPI
Programmable Logic to
Memory Interconnect
MMU
FPU and NEON Engine
Snoop Controller, AWDT, Timer
GIC
32 KB
I-Cache
ARM Cortex-A9
CPU
ARM Cortex-A9
CPU MMU
FPU and NEON Engine
Config
AES/
SHA
XADC
12-Bit ADC
Memory
Interfaces
512 KB L2 Cache and Controller
OCM
Interconnect
DDR2/3,
LPDDR2
Controller
UG850_c1_04_101712
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
MIO
Clock
Generation Reset
Central
Interconnect
General-Purpose
Ports
High-Performance Ports
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ZC702 Board User Guide www.xilinx.com 15
UG850 (v1.3) June 4, 2014
Feature Descriptions
The ZC702 board supports these configuration options:
• PS Configuration: Quad SPI flash memory
• PS Configuration: Processor System Boot from SD Card (J64)
• PL Configuration: USB JTAG configuration port (Digilent module)
• PL Configuration: Platform cable header J2 and flying lead header J58 JTAG
configuration ports
TIP: Designs using serial configuration based on Quad-SPI flash memory can take advantage of
low-cost commodity SPI flash memory.
The JTAG configuration option is selected by setting SW16 as shown in Table 1-2 and SW10
as described in Programmable Logic JTAG Programming Options, page 25 for PL
configuration details. SW10 is callout 23 in Figure 1-2.
Note: For more information about Zynq-7000 AP SoC configuration settings, see the Zynq-7000 All
Programmable SoC Technical Reference Manual (UG585) [Ref 9].
Table 1-2: Switch SW16 Configuration Option Settings
Boot Mode SW16.1 SW16.2 SW16.3 SW16.4 SW16.5
JTAG mode(1) 00000
Independent JTAG mode 10000
QSPI mode 00010
SD mode 00110
MIO configuration pin MIO2 MIO3 MIO4 MIO5 MIO6
Notes:
1. Default switch setting
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UG850 (v1.3) June 4, 2014
Feature Descriptions
Encryption Key Backup Circuit
The XC7Z020 AP SoC U1 implements bitstream encryption key technology. The ZC702
board provides the encryption key backup battery circuit shown in Figure 1-5.
The Seiko TS518FE rechargeable 1.5V lithium button-type battery B1 is soldered to the
board with the positive output connected to the XC7Z020 AP SoC U1 VCCBATT pin G9. The
battery supply current IBATT specification is 150 nA maximum when board power is off. B1
is charged from the VCCAUX 1.8V rail through a series diode with a typical forward voltage
drop of 0.38V and 4.7 KΩcurrent limit resistor. The nominal charging voltage is 1.42V.
X-Ref Target - Figure 1-5
Figure 1-5: Encryption Key Backup Circuit
UG850_c1_05_030513
GND
2
1
B1
Lithium Battery
Seiko
TS518SE_FL35E
1.5V
2
1
3
BAS40-04
D8
40V
200 mW
NC
FPGA_VBATT
+
VCCAUX
R2
4.70K 1%
1/16W
To AP SoC
U1 Pin G9
(VCCBATT)
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ZC702 Board User Guide www.xilinx.com 17
UG850 (v1.3) June 4, 2014
Feature Descriptions
I/O Voltage Rails
There are four PL I/O banks available on the XC7Z020 AP SoC. The voltages applied to the
XC7Z020 AP SoC I/O banks used by the ZC702 board are listed in Tab le 1-3.
DDR3 Component Memory
[Figure 1-2, callout 2]
The 1 GB, 32-bit wide DDR3 memory system is comprised of four 256 Mb x 8 SDRAMs
(Micron MT41J256M8HX-15E) at U66–U69. This memory system is connected to the
XC7Z020 AP SoC processing system (PS) memory interface bank 502. The DDR3 0.75V VTT
termination voltage is sourced from linear regulator U22. The connections between the
DDR3 memory and XC7Z020 AP SoC bank 502 are listed in Ta ble 1-4 .
Table 1-3: I/O Voltage Rails
XC7Z020 (U1)
Bank Net Name Voltage Connected To
PL Bank 0 VCC2V5_PL 2.5V AP SoC Configuration Bank 0
PL Bank 13
VADJ(1) 2.5V
FMC2, GPIO, PL_PJTAG, IIC_MAIN
PL Bank 33 FMC2, HDMI Codec
PL Bank 34 FMC1, HDMI Codec
PL Bank 35 FMC1, HDMI Codec, XADC_GPIO, GPIO
PS Bank 500 VCCMIO_PS 1.8V Quad-SPI flash memory, misc
PS Bank 501 Ethernet PHY, USB ULPI Transceiver, SDIO, CAN
PS Bank 502 VCC1V5_PS 1.5V PS_DDR3 MEM
Notes:
1. The ZC702 board is shipped with VADJ set to 2.5V.
Table 1-4: DDR3 Component Memory Connections to the XC7Z020 AP SoC
XC7Z020 (U1) Pin Net Name
Component Memory
Pin Number Pin Name Reference
Designator
E3 PS_DDR3_DQ0 B3 DQ0 U66
C3 PS_DDR3_DQ1 C7 DQ1 U66
F2 PS_DDR3_DQ2 C2 DQ2 U66
D1 PS_DDR3_DQ3 C8 DQ3 U66
F1 PS_DDR3_DQ4 E3 DQ4 U66
E1 PS_DDR3_DQ5 E8 DQ5 U66
B2 PS_DDR3_DQ6 D2 DQ6 U66
D3 PS_DDR3_DQ7 E7 DQ7 U66
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UG850 (v1.3) June 4, 2014
Feature Descriptions
G2 PS_DDR3_DQ8 B3 DQ8 U67
L1 PS_DDR3_DQ9 C7 DQ9 U67
G1 PS_DDR3_DQ10 C2 DQ10 U67
K1 PS_DDR3_DQ11 C8 DQ11 U67
L3 PS_DDR3_DQ12 E3 DQ12 U67
L2 PS_DDR3_DQ13 E8 DQ13 U67
J1 PS_DDR3_DQ14 D2 DQ14 U67
K3 PS_DDR3_DQ15 E7 DQ15 U67
M1 PS_DDR3_DQ16 B3 DQ16 U68
T3 PS_DDR3_DQ17 C7 DQ17 U68
N3 PS_DDR3_DQ18 C2 DQ18 U68
T1 PS_DDR3_DQ19 C8 DQ19 U68
R3 PS_DDR3_DQ20 E3 DQ20 U68
T2 PS_DDR3_DQ21 E8 DQ21 U68
M2 PS_DDR3_DQ22 D2 DQ22 U68
R1 PS_DDR3_DQ23 E7 DQ23 U68
U1 PS_DDR3_DQ24 B3 DQ24 U69
AA1 PS_DDR3_DQ25 C7 DQ25 U69
U2 PS_DDR3_DQ26 C2 DQ26 U69
AA3 PS_DDR3_DQ27 C8 DQ27 U69
W1 PS_DDR3_DQ28 E3 DQ28 U69
Y3 PS_DDR3_DQ29 E8 DQ29 U69
W3 PS_DDR3_DQ30 D2 DQ30 U69
Y1 PS_DDR3_DQ31 E7 DQ31 U69
B1 PS_DDR3_DM0 B7 DM0 U66
C2 PS_DDR3_DQS0_P C3 DQS0_P U66
D2 PS_DDR3_DQS0_N D3 DQS0_N U66
H3 PS_DDR3_DM1 B7 DM1 U67
H2 PS_DDR3_DQS1_P C3 DQS1_P U67
J2 PS_DDR3_DQS1_N D3 DQS1_N U67
P1 PS_DDR3_DM2 B7 DM2 U68
N2 PS_DDR3_DQS2_P C3 DQS2_P U68
P2 PS_DDR3_DQS2_N D3 DQS2_N U68
Table 1-4: DDR3 Component Memory Connections to the XC7Z020 AP SoC (Cont’d)
XC7Z020 (U1) Pin Net Name
Component Memory
Pin Number Pin Name Reference
Designator
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ZC702 Board User Guide www.xilinx.com 19
UG850 (v1.3) June 4, 2014
Feature Descriptions
AA2 PS_DDR3_DM3 B7 DM3 U69
V2 PS_DDR3_DQS3_P C3 DQS3_P U69
W2 PS_DDR3_DQS3_N D3 DQS3_N U69
M4 PS_DDR3_A0 K3 A0 U66, U67, U68, U69
M5 PS_DDR3_A1 L7 A1 U66, U67, U68, U69
K4 PS_DDR3_A2 L3 A2 U66, U67, U68, U69
L4 PS_DDR3_A3 K2 A3 U66, U67, U68, U69
K6 PS_DDR3_A4 L8 A4 U66, U67, U68, U69
K5 PS_DDR3_A5 L2 A5 U66, U67, U68, U69
J7 PS_DDR3_A6 M8 A6 U66, U67, U68, U69
J6 PS_DDR3_A7 M2 A7 U66, U67, U68, U69
J5 PS_DDR3_A8 N8 A8 U66, U67, U68, U69
H5 PS_DDR3_A9 M3 A9 U66, U67, U68, U69
J3 PS_DDR3_A10 H7 A10 U66, U67, U68, U69
G5 PS_DDR3_A11 M7 A11 U66, U67, U68, U69
H4 PS_DDR3_A12 K7 A12 U66, U67, U68, U69
F4 PS_DDR3_A13 N3 A13 U66, U67, U68, U69
G4 PS_DDR3_A14 N7 A14 U66, U67, U68, U69
L7 PS_DDR3_BA0 J2 BA0 U66, U67, U68, U69
L6 PS_DDR3_BA1 K8 BA1 U66, U67, U68, U69
M6 PS_DDR3_BA2 J3 BA2 U66, U67, U68, U69
N4 PS_DDR3_CLK_P F7 CK U66, U67, U68, U69
N5 PS_DDR3_CLK_N G7 CK_B U66, U67, U68, U69
V3 PS_DDR3_CKE G9 CKE U66, U67, U68, U69
R4 PS_DDR3_WE_B H3 WE_B U66, U67, U68, U69
P3 PS_DDR3_CAS_B G3 CAS_B U66, U67, U68, U69
R5 PS_DDR3_RAS_B F3 RAS_B U66, U67, U68, U69
F3 PS_DDR3_RESET_B N2 RESET_B U66, U67, U68, U69
P6 PS_DDR3_CS_B H2 CS_B U66, U67, U68, U69
P5 PS_DDR3_ODT G1 ODT U66, U67, U68, U69
M7 PS_VRN
N7 PS_VRP
Table 1-4: DDR3 Component Memory Connections to the XC7Z020 AP SoC (Cont’d)
XC7Z020 (U1) Pin Net Name
Component Memory
Pin Number Pin Name Reference
Designator
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ZC702 Board User Guide www.xilinx.com 20
UG850 (v1.3) June 4, 2014
Feature Descriptions
Note: The ZC702 DDR3 4x 8-bit component memory interface adheres to the constraints guidelines
documented in the DDR3 Design Guidelines section of the 7 Series FPGAs Memory Interface Solutions
v1.8 User Guide (UG586) [Ref 10]. The ZC702 DDR3 memory interface is a 40Ωimpedance
implementation. Other memory interface details are available in UG586 and the 7SeriesFPGAs
Memory Resources User Guide (UG473) [Ref 5].
Quad-SPI Flash Memory
[Figure 1-2, callout 3]
The Quad-SPI flash memory located at U41 provides 128 Mb of non-volatile storage that
can be used for configuration and data storage.
• Part number: N25Q128A11ESF40G (Micron/Numonyx)
•Supplyvoltage:1.8V
• Data path width: 4 bits
• Data rate: Various depending on Single/Dual/Quad mode
The connections between the SPI flash memory and the XC7Z020 AP SoC are listed in
Tab le 1-5.
The configuration and QSPI section of the Zynq-7000 All Programmable SoC Technical
Reference Manual (UG585) [Ref 9] provides details on using the Quad-SPI flash memory.
H7 VTTVREF_PS
P7 VTTVREF_PS
Table 1-5: Quad SPI Flash Memory Connections to the XC7Z020 AP SoC
XC7Z020 (U1) Schematic
Net Name
Quad-SPI Flash Memory (U41) MIO Select
Header
Pin Name Bank Pin Number Pin Number Pin Name
PS_MIO6 500 A4 QSPI_CLK 16 C J26.2
PS_MIO5 500 A3 QSPI_IO3 1 DQ3_HOLD_B J25.2
PS_MIO4 500 E4 QSPI_IO2 9 WP_B J22.2
PS_MIO3 500 F6 QSPI_IO1 8 DQ1 J20.2
PS_MIO2 500 A2 QSPI_IO0 15 DQ0 J21.2
PS_MIO1 500 A1 QSPI_CS_B 7S_BNA
Notes:
Each three-pin MIO select header has pin 1 wired to VCCMIO and pin 3 wired to GND.
Table 1-4: DDR3 Component Memory Connections to the XC7Z020 AP SoC (Cont’d)
XC7Z020 (U1) Pin Net Name
Component Memory
Pin Number Pin Name Reference
Designator
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