Xilinx Virtex-7 FPGA VC7222 IBERT User manual

Virtex-7 FPGA VC7222
Characterization Kit IBERT
Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015

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UG971 (Vivado Design Suite v2015.1) April 27, 2015
Revision History
The following table shows the revision history for this document.
Date Version Revision
09/20/2013 1.0 Initial Xilinx release.
09/24/2013 1.0.1 Updated the Notice of Disclaimer, page 2..
11/07/2013 2.0 Updated for Vivado® Design Suite 2013.3. Updated most figures in Chapter 1,
VC7222 IBERT Getting Started Guide. Figure 1-31 and Figure 2-11 were renamed
Design Sources File Hierarchy.Deleted Figures 2-12 and Figure 3-9, Synthesize
Out-Of-Context Module. The name of the project ZIP file changed to
rdf0297-vc7222-ibert-2013-3.zip. Replaced Figure 3-8, Set As Out Of Context
Module with Design Sources File Hierarchy screen. Deleted Figure 3-12, Edit the
Implementation Setting. Updated Appendix A, Additional Resources and Legal Notices
links.
01/22/2014 3.0 Updated for Vivado Design Suite 2013.4. Updated Figure 1-11, Figure 1-13,
Figure 1-14, Figure 1-15, Figure 1-27, Figure 1-28, Figure 1-29, Figure 1-33,
Figure 2-1, and Figure 3-5.
04/16/2014 4.0 Updated for Vivado Design Suite 2014.1. Updated 30 graphics in Chapters 1, 2, and 3.
File lists changed under Extracting the Project Files. The ZIP project file name changed
to rdf0297-vc7222-ibert-2014-1.zip. Launching the Vivado Design Suite
Software was changed to Setting Up the Vivado Design Suite in the Running the GTH
IBERT Demonstration, page 9 and Running the GTZ IBERT Demonstration, page 28
sections, and In Case of RX Bit Errors was added to both sections.
06/12/2014 5.0 Updated for Vivado Design Suite 2014.2. Updated Figure 1-10, Figure 1-11,
Figure 1-19, Figure 1-20, Figure 1-23, Figure 1-27, Figure 1-30, Figure 1-33,
Figure 2-1, Figure 2-4, Figure 2-8, Figure 2-11, Figure 2-14, Figure 2-16, Figure 3-2,
through Figure 3-5, Figure 3-8, Figure 3-11. and Figure 3-13. Added device
programming information in Starting the SuperClock-2 Module, page 20 and Starting
the SuperClock-2 Module, page 36. Updated Viewing GTH Transceiver Operation and
Viewing GTZ Transceiver Operation.
09/17/2014 5.1 Changed cable quantity from two to one under Requirements. Added a note about
cable quantity in Running the GTZ IBERT Demonstration. Updated clock connection
information in GTZ Transceiver Clock Connection. Added a Caution regarding BullsEye
cable use in Attach the GTZ Quad Connector. Added a note about the cable
connection in Figure 1-24 and before Figure 1-33. Replaced Figure 3-3.
10/09/2014 6.0 Updated for Vivado Design Suite 2014.3. Added BullsEye cable instructions to Viewing
GTH Transceiver Operation. Updated Figure 1-10, Figure 1-11, Figure 1-14,
Figure 1-19, Figure 2-2, Figure 2-4, Figure 2-8, Figure 2-9, Figure 2-14, Figure 3-5,
and Figure 3-11.
11/24/2014 7.0 Updated for Vivado Design Suite 2014.4. The ZIP project file name changed to
rdf0297-vc7222-ibert-2014-4.zip. The board revision changed from Rev B to
Rev 1 (Figure 1-1). Updated Figure 1-10, Figure 1-19, Figure 1-20, Figure 2-4, and
Figure 2-8.

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04/27/2015 2015.1 Updated for Vivado Design Suite 2015.1. The ZIP project file name changed to
rdf0297-vc7222-ibert-2015-1.zip. Updated Figure 1-4, Figure 1-10,
Figure 1-15, Figure 1-18, Figure 1-29, Figure 1-31, Figure 1-32, Figure 2-1,
Figure 2-4, Figure 2-8, Figure 3-1, and Figure 3-5. Version changed to match the
software release.
Date Version Revision
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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: VC7222 IBERT Getting Started Guide
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Setting Up the VC7222 Board for GTH and GTZ IBERT Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Extracting the Project Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Running the GTH IBERT Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Running the GTZ IBERT Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SuperClock-2 Frequency Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Chapter 2: Creating the GTH IBERT Core
Chapter 3: Creating the GTZ IBERT Core
Appendix A: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Appendix B: Warranty
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Chapter 1
VC7222 IBERT Getting Started Guide
Overview
This document provides a procedure for setting up the Virtex®-7 FPGA VC7222 GTH and
GTZ Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT)
demonstration using the Vivado® Design Suite. The designs required to run the IBERT
demonstration are stored in the Secure Digital (SD) memory card provided with the VC7222
board. A copy of the designs can also be found at the Virtex-7 FPGA VC7222
Characterization Kit documentation website.
The VC7222 board is described in detail in Virtex-7 FPGA VC7222 GTH and GTZ Transceiver
Characterization Board User Guide (UG965) [Ref 1].
The IBERT GTH demonstration operates one GTH Quad at a time. The procedure consists of:
1. Setting Up the VC7222 Board for GTH and GTZ IBERT Testing, page 7
2. Extracting the Project Files, page 7
3. Connecting the GTH Transceivers and Reference Clocks, page 9
4. Configuring the FPGA, page 15
5. Setting Up the Vivado Design Suite, page 17
6. Starting the SuperClock-2 Module, page 20
7. Viewing GTH Transceiver Operation, page 26
8. Closing the IBERT Demonstration, page 27
The IBERT GTZ demonstration operates 8 GTZ lanes using both Q300A and Q300B. The
procedure consists of:
1. Connecting the GTZ Transceiver and Reference Clocks, page 28
2. Configuring the FPGA, page 33
3. Setting up the Vivado Design Suite, page 35
4. Starting the SuperClock-2 Module, page 20
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Chapter 1: VC7222 IBERT Getting Started Guide
5. Viewing GTZ Transceiver Operation, page 41
6. Closing the IBERT Demonstration, page 43
Requirements
The hardware and software required to run the GTH and GTZ IBERT demonstration are listed
here:
• Virtex-7 FPGA VC7222 GTH and GTZ Transceiver Characterization Board. The kit
includes:
°One SD card containing the IBERT demonstration designs
°One Samtec BullsEye™ cable
°One skew-matched reference clock cable set
°Eight SMA female-to-female (F-F) adapters
°Six 50ΩSMA terminators
°GTH transceiver power supply module (installed on board)
°GTZ transceiver power supply module (installed on board)
°SuperClock-2 module, Rev 1.0 (installed on board)
°12V DC power adapter
°USB cable, standard-A plug to Micro-B plug
•HostPCwith:
°SD card reader
°USB ports
°Vivado Design Suite 2015.1
The hardware and software required to rebuild the IBERT demonstration designs are:
• Vivado Design Suite 2015.1
• Host PC with a version of the Windows operating system supported by the Vivado
Design Suite
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Chapter 1: VC7222 IBERT Getting Started Guide
Setting Up the VC7222 Board for GTH and GTZ
IBERT Testing
CAUTION! The VC7222 board can be damaged by electrostatic discharge (ESD). Follow standard ESD
prevention measures when handling the board.
When the VC7222 board ships from the factory, it is already configured for the GTH IBERT
demonstration described in this chapter. If the board has been re-configured, it must be
returned to the default setup before running the IBERT demonstrations.
1. Move all jumpers and switches to their default positions. The default jumper and switch
positions are listed in Virtex-7 FPGA VC7222 GTH and GTZ Transceiver Characterization
Board User Guide (UG965) [Ref 1].
2. Install the GTH and GTZ transceiver power modules into connectors J29 – J102, and J5
and J71, respectively.
3. Install the SuperClock-2 module:
a. Align the three metal standoffs on the bottom side of the module with the three
mounting holes in the SuperClock-2 module interface of the VC7222 board.
b. Using three 4-40 x 0.25 inch screws, firmly screw down the module from the bottom
of the VC7222 board.
c. On the SuperClock-2 module, place a jumper across pins 2 - 3 (2V5) of the CONTROL
VOLTAGE header, J18, and place another jumper across Si570 INH header J11.
d. Screw down a 50ΩSMA terminator onto each of the six unused Si5368 clock output
SMA connectors: J7, J8, J12, J15, J16, and J17.
Extracting the Project Files
The Vivado project files required to run the IBERT demonstration are located in
rdf0297-vc7222-ibert-2015-1.zip on the SD card provided with the VC7222 board.
These files are also available online at the Virtex-7 FPGA VC7222 Characterization Kit
documentation website.
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Chapter 1: VC7222 IBERT Getting Started Guide
The ZIP file contains these files:
•BITfiles
vc7222_ibert_q113_325.bit
vc7222_ibert_q114_325.bit
vc7222_ibert_q115_325.bit
vc7222_ibert_q213_325.bit
vc7222_ibert_q214_325.bit
vc7222_ibert_q215_325.bit
vc7222_ibert_q300_225.bit
vc7222_uarttest.bit
•Probefiles
vc7222_ibert_q113_debug_nets.ltx
vc7222_ibert_q114_debug_nets.ltx
vc7222_ibert_q115_debug_nets.ltx
vc7222_ibert_q213_debug_nets.ltx
vc7222_ibert_q214_debug_nets.ltx
vc7222_ibert_q215_debug_nets.ltx
vc7222_ibert_q300_debug_nets.ltx
•Tclscripts
add_scm2.tcl
setup_scm2_325_00_GTH.tcl
setup_scm2_225_00_GTZ.tcl
The Tcl scripts are used to help merge the IBERT and SuperClock-2 source code (described
in Chapter 2, Creating the GTH IBERT Core and in Chapter 3, Creating the GTZ IBERT Core)
and to set up the SuperClock-2 module (described in Starting the SuperClock-2 Module,
page 20 in the GTH section and Starting the SuperClock-2 Module, page 36 in the GTZ
section).
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Chapter 1: VC7222 IBERT Getting Started Guide
To copy the files from the SD memory card:
1. Connect the SD card to the host computer.
2. Locate the file rdf0297-vc7222-ibert-2015-1.zip on the SD memory card.
3. Unzip the files to a working directory on the host computer.
Running the GTH IBERT Demonstration
The GTH IBERT demonstration operates one GTH Quad at a time. This section describes how
to test GTH Quad 115, while the remaining GTH Quads are tested following similar steps.
Connecting the GTH Transceivers and Reference Clocks
Figure 1-1 shows the locations for all the GTH transceiver Quads on the Rev. 1 VC7222
board.
X-Ref Target - Figu re 1-1
Figure 1-1: GTH Quad Location
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Chapter 1: VC7222 IBERT Getting Started Guide
Note: Figure 1-1 is for reference only and might not reflect the current revision of the board.
All GTH transceiver pins and reference clock pins are routed from the FPGA to a connector
pad which interfaces with the Samtec BullsEye connector. Figure 1-2 Ashows the connector
pad, and Figure 1-2 Bshows the connector pinout.
X-Ref Target - Figure 1-2
Figure 1-2: A – GTH Connector Pad. B – GTH Connector Pinout
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Chapter 1: VC7222 IBERT Getting Started Guide
The SuperClock-2 module provides LVDS clock outputs for the GTH transceiver reference
clock in the IBERT demonstration. Figure 1-3 shows the location of the differential clock
SMA connections on the clock module which can be connected to the reference clock
cables.
Note: The image in Figure 1-3 is for reference only and might not reflect the current revision of the
board.
The four SMA pairs labeled CLKOUT provide LVDS clock outputs from the Si5368 clock
multiplier/jitter attenuator device on the clock module. The SMA pair labeled Si570_CLK
provides LVDS clock output from the Si570 programmable oscillator on the clock module.
Note: The Si570 oscillator does not support LVDS output on Rev. B and earlier revisions of the
SuperClock-2 module.
For the GTH IBERT demonstration, the output clock frequencies are preset to 325.00 MHz.
For more information regarding the SuperClock-2 module, see the HW-CLK-101-SCLK2
SuperClock-2 Module User Guide (UG770) [Ref 2].
X-Ref Target - Figure 1-3
Figure 1-3: SuperClock-2 Module Output Clock SMA Locations
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Chapter 1: VC7222 IBERT Getting Started Guide
Attach the GTH Quad Connector
Before connecting the BullsEye cable assembly to the board, firmly secure the blue
elastomer seal provided with the cable assembly to the bottom of the connector housing, if
it is not already inserted (see Figure 1-4).
Note: Figure 1-4 is for reference only and might not reflect the current version of the connector.
X-Ref Target - Figure 1-4
Figure 1-4: BullsEye Connector with Elastomer Seal
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Chapter 1: VC7222 IBERT Getting Started Guide
Attach the Samtec BullsEye connector to the GTH Quad 115 (Figure 1-5), aligning the two
indexing pins on the bottom of the connector with the guide holes on the board. Hold the
connector flush with the board and fasten it by tightening the two captive screws.
GTH Transceiver Clock Connections
See Figure 1-2 to identify the P and N coax cables connected to the CLK0 reference clock
inputs. Connect these cables to the SuperClock-2 module as follows:
• CLK0_P coax cable → SMA connector J5 (CLKOUT1_P) on the SuperClock-2 module
• CLK0_N coax cable → SMA connector J6 (CLKOUT1_N) on the SuperClock-2 module
Note: Any one of the five differential outputs from the SuperClock-2 module can be used to source
the GTH reference clock. CLKOUT1_P and CLKOUT1_N are used here as an example.
X-Ref Target - Figu re 1-5
Figure 1-5: BullsEye Connector Attached to GTH Quad 115
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Chapter 1: VC7222 IBERT Getting Started Guide
GTH TX/RX Loopback Connections
See Figure 1-2 to identify the P and N coax cables that are connected to the four receivers
(RX0, RX1, RX2, and RX3) and the four transmitters (TX0, TX1, TX2, and TX3). Use eight SMA
female-to-female (F-F) adapters (Figure 1-6) to connect the transmit and receive cables as
shown in Figure 1-7 and detailed in the following list:
•TX0_P→ SMA F-F Adapter → RX0_P
•TX0_N→ SMA F-F Adapter → RX0_N
•TX1_P→ SMA F-F Adapter → RX1_P
•TX1_N→ SMA F-F Adapter → RX1_N
•TX2_P→ SMA F-F Adapter → RX2_P
•TX2_N→ SMA F-F Adapter → RX2_N
•TX3_P→ SMA F-F Adapter → RX3_P
•TX3_N→ SMA F-F Adapter → RX3_N
Note: To ensure good connectivity, it is recommended that the adapters be secured with a wrench,
however do not over-tighten the SMAs.
X-Ref Target - Figure 1-6
Figure 1-6: SMA F-F Adapter
X-Ref Target - Figure 1-7
Figure 1-7: TX-To-RX Loopback Connection Example
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Chapter 1: VC7222 IBERT Getting Started Guide
Figure 1-8 shows the VC7222 board with the cable connections required for the Quad 115
GTH IBERT demonstration.
Configuring the FPGA
This section describes how to configure the FPGA using the SD card included with the
board. The FPGA can also be configured through Vivado Design Suite using the .bit files
available on the SD card, or online (as collection rdf0297-vc7222-ibert-2015-1.zip)
at the Virtex-7 FPGA VC7222 Characterization Kit documentation website.
X-Ref Target - Figu re 1-8
Figure 1-8: Cable Connections for Quad 115 GTH IBERT Demonstration
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Chapter 1: VC7222 IBERT Getting Started Guide
To configure the FPGA using the SD card:
1. Insert the SD card provided with the VC7222 board into the SD card reader slot located
on the bottom-side (upper-right corner) of the VC7222 board.
2. Plug the 12V output from the power adapter into connector J2 on the VC7222 board.
3. Connect the host computer to the VC7222 board using a standard-A plug to Micro-B
plug USB cable. The standard-A plug connects to a USB port on the host computer and
the Micro-B plug connects to U57, the Digilent USB JTAG configuration port on the
VC7222 board.
4. Select the GTH IBERT demonstration with the System ACE™ SD Controller SYSACE-2 CFG
switch, SW8. The setting on this 4-bit DIP switch (Figure 1-9) selects the file used to
configure the FPGA. A switch is in the ON position if set to the far right and in the OFF
position if set to the far left. For the Quad 115 GTH IBERT demonstration, set ADR2 =
ON, ADR1 = OFF, and ADR0 = ON. The MODE bit (switch position 4) is not used and can
be set either ON or OFF.
There is one IBERT demonstration design for each GTH Quad on the VC7222 board, for a
total of six IBERT designs. Additional designs are provided to demonstrate the GTZ and the
USB/UART interface (details of this demonstration are described in the README file on the
SD card). All eight designs are organized and stored on the SD card as shown in Table 1-1.
5. Place the main power switch SW1 to the ON position.
X-Ref Target - Figure 1-9
Figure 1-9: Configuration Address DIP Switch (SW8)
Table 1-1: SD Card Contents and Configuration Addresses
Demonstration Design ADR2 ADR1 ADR0
GTH Quad 113 ON ON ON
GTH Quad 114 ON ON OFF
GTH Quad 115 ON OFF ON
GTH Quad 213 ON OFF OFF
GTH Quad 214 OFF ON ON
GTH Quad 215 OFF ON OFF
GTZ Quad 300A and 300B OFF OFF ON
USB/UART OFF OFF OFF
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Chapter 1: VC7222 IBERT Getting Started Guide
Setting Up the Vivado Design Suite
1. Start Vivado Design Suite on the host computer and click Flow > Open Hardware
Manager (highlighted in Figure 1-10).
X-Ref Target - Figure 1-10
Figure 1-10: Vivado Design Suite, Open Hardware Manager
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Chapter 1: VC7222 IBERT Getting Started Guide
2. In the Hardware Manager window, click Open New Target (highlighted in Figure 1-11).
3. An Open Hardware Target wizard starts. Click Next to run the wizard.
4. In the Hardware Server Settings window, select Local server (target is on local
machine). Click Next to open the server and connect to the Xilinx TCF JTAG cable.
X-Ref Target - Figure 1-11
Figure 1-11: Open a New Target
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Chapter 1: VC7222 IBERT Getting Started Guide
5. In the Select Hardware Target window, the xilinx_tcf cable appears under
Hardware Targets, and the JTAG chain contents of the selected cable appear under
Hardware Devices (Figure 1-12). Select the xilinx_tcf target and keep the JTAG Clock
Frequency at the default value (15 MHz). Click Next.
6. In the Open Hardware Target Summary window, click Finish. The wizard closes and the
Vivado Design Suite opens the hardware target.
X-Ref Target - Figure 1-12
Figure 1-12: Select Hardware Target
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Chapter 1: VC7222 IBERT Getting Started Guide
Starting the SuperClock-2 Module
The IBERT demonstration designs use an integrated VIO core to control the clocks on the
SuperClock-2 module. The SuperClock-2 module features two clock-source components:
• Always-on Si570 crystal oscillator
• Si5368 jitter-attenuating clock multiplier
Outputs from either source can be used to drive the transceiver reference clocks.
To start the SuperClock-2 module:
1. The Vivado Design Suite Hardware window shows the System ACE tool and the
XC7VH580T devices. The XC7VH580T device is reported as programmed. In the
Hardware Device Properties window, enter the file path to the Q115 Probes file
(vc7222_ibert_q115_debug_nets.ltx) in the extracted IBERT files from the SD
card (Figure 1-13).
X-Ref Target - Figure 1-13
Figure 1-13: Adding the Probes File
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