Xilinx T1 User manual

T1 Telco Accelerator Card
User Guide
UG1495 (v1.0) December 17, 2021
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Table of Contents
Chapter 1: Introduction.............................................................................................. 4
Features........................................................................................................................................5
Overview.......................................................................................................................................6
Chapter 2: Pin Mapping...............................................................................................9
Zynq UltraScale+ MPSoC ZU19 Pin Map................................................................................... 9
Zynq UltraScale+ RFSoC ZU21 Pin Map...................................................................................19
Satellite Controller Pin Map..................................................................................................... 28
Chapter 3: Ports............................................................................................................. 31
SFP28 Ports.................................................................................................................................31
Maintenance Port for UART and JTAG Access........................................................................ 31
IEEE 1588 Support..................................................................................................................... 32
PCI Express.................................................................................................................................33
Chapter 4: Clocking......................................................................................................34
IEEE 1588 Clocking.................................................................................................................... 34
PCIe Reference Clock................................................................................................................ 35
SFP28 Clocks...............................................................................................................................35
DDR4 SDRAM Reference Clocks...............................................................................................36
MAC to MAC Interface Reference Clock..................................................................................36
User Clocks.................................................................................................................................36
Chapter 5: LEDs.............................................................................................................. 38
Chapter 6: Xilinx Design Constraints (XDC) File.......................................... 39
Appendix A: Programming the Devices Using JTAG.................................. 40
Flashing the Images to ZU19 Zynq UltraScale+ MPSoC QSPI Using SDK........................... 43
Flashing the Images to ZU21 Zynq UltraScale+ RFSoC QSPI Using SDK............................ 45
Programming the Bitstreams Directly ...................................................................................46
Flashing the Images Using the Program Flash Application.................................................47
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Appendix B: Regulatory Compliance Statements...................................... 49
FCC Class A Products.................................................................................................................49
Safety.......................................................................................................................................... 49
EMC Compliance........................................................................................................................50
FCC Class A User Information..................................................................................................50
VCCI Class A Statement............................................................................................................ 51
Appendix C: Additional Resources and Legal Notices............................. 52
Xilinx Resources.........................................................................................................................52
Documentation Navigator and Design Hubs.........................................................................52
References..................................................................................................................................53
Revision History.........................................................................................................................53
Please Read: Important Legal Notices................................................................................... 53
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T1 Telco Accelerator Card User Guide 3
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Chapter 1
Introduction
The Xilinx® T1 Telco accelerator card is a PCI Express® (PCIe) Gen3 x16 compliant card featuring
the 16 nm Zynq® UltraScale+™ MPSoC and Zynq UltraScale+ RFSoC devices. The T1 form factor
is full height, half length (FHHL) and single slot, with a PCIe Gen 3 x16 interface that is x8x8
bifurcated providing x8 links from the host to each MPSoC and RFSoC device. Target applicaons
for the T1 card include:
• O-RAN fronthaul terminaon
• 4G LTE and 5G NR high-PHY lookaside acceleraon (supporng 3GPP split opon 7-2x)
• 5G layer 1 (L1) high-PHY lookaside acceleraon
•Oponal use of fronthaul ports for a midhaul (F1) interface between distributed and
centralized units (DU and CU)
• 4G LTE and 5G NR inline acceleraon of L1 funcons (supporng 3GPP split opon 7-2x) for
up to 4TRX
Figure 1: T1 Telco Accelerator Card
Chapter 1: Introduction
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Features
A high-level block diagram of the T1 card card is shown in the following gure.
Figure 2: T1 card High-Level Block Diagram
X25153-030821
ZU21DR
L1 Channel Coding
· Hardened LDPC / TURBO
Codec
· Polar Codec
· HARQ Buffer Management
· Channel Coding Wrapper
Logic
ZU19EG
Network Interface
Fronthaul/Midhaul
4GB DDR4
(PL)
2GB DDR4
(PS)
4GB DDR4
(PL)
2GB DDR4
(PS)
Timing Circuit
TCXO/OCXO
Board Management
Controller
SFP28 Optics
SFP28 Optics
25G
25G
25G
25G
PPS IN
PPS OUT
Gen3 x16 with Bifurcation
Gen3 x8 Gen3 x8
100G
The main features and components of the T1 card are as follows:
• Xilinx ZU19EG MPSoC device targeng 5G fronthaul terminaon
• Xilinx ZU21DR RFSoC device targeng L1 channel coding
• Dual NOR ash of 2x 256 MB in QSPI mode for Zynq UltraScale+ MPSoC
• Dual NOR ash of 2x 256 MB in QSPI mode for Zynq UltraScale+ RFSoC
• 4 GB of DDR4 programmable logic (PL) memory to each Zynq UltraScale+ MPSoC and Zynq
UltraScale+ RFSoC device
• 2 GB of DDR4 processor system (PS) memory to each Zynq UltraScale+ MPSoC and Zynq
UltraScale+ RFSoC device
• 100G (MAC-to-MAC) communicaon link between Zynq UltraScale+ MPSoC and Zynq
UltraScale+ RFSoC devices
• Two SFP28 cages supporng up to 25G signaling and pluggable opcs
• IEEE 1588 Network Synchronizer ming circuit with PPS in/out connectors
• Satellite controller for IPMI compliant monitoring and telemetry
• Bifurcated x8x8 PCIe Gen 3 x16 link to the host from each FPGA
• FHHL form factor with a 75W power envelope
Chapter 1: Introduction
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• x16 standard card form factor (FHHL), single slot (111.15 mm x 167.65 mm)
• Maintenance port for card maintenance and developer access using the DMB II Interface
(proprietary, requires Xilinx® DMB II kit)
Overview
The system hardware contains a single PCB assembly. The MNC2 card is built with a XCZU21DR
Zynq UltraScale+ RFSoC and a XCZU19EG Zynq UltraScale+ MPSoC. The connecvity includes
two 25G interfaces and one x16 Gen 3.0 PCIe interface. Each SoC acts as a Gen3.0 x8 endpoint
with respect to root complex. One DDR4 Memory controller is implemented inside the PL
secon of both SoCs. A second set of DDR4 memory is interfaced to PS secon of both SoCs.
One 100G transceiver is implemented on both SoCs for inter-SoC communicaon. A detailed
block diagram of the T1 card card is shown in the following gure.
Figure 3: Detailed T1 card Block Diagram
Zync UltraScale+
RFSoC
XCZU21DR
-L2FSVD1156E
Zync UltraScale+
MPSoC
XCZU19EG
-L2FFVD1760E
QSPI Flash
Memory
Configuration
Block
IO[0:7]
SCK
CS
DDR4
DDR4_1_A[0:16]
DDR4_1_BA[0:1]
DDR4_1_DM[0:4]
DDR4_1_DQ[0:39]
DDR4_1_A\DQS_T/C[0:4]
DDR4_1_CLK_T/C
DDR4_1_RST
DDR4
DDR4_0_A[0:16]
DDR4_0_BA[0:1]
DDR4_0_DM[0:8]
DDR4_0_DQ[0:71]
DDR4_0_A\DQS_T/C[0:8]
DDR4_0_CLK_T/C
DDR4_0_RST
I2C_0
25G MAC0
GT_RX_P/N
GT_RX_P/N
SFP0_REFCLK_RST
I2C_1
25G MAC1
GT_RX_P/N
GT_RX_P/N
SFP1_REFCLK_RST
JTAG
TCK
TMS
TDI
TDO
UART
100G MAC0
MAC0_CLK_P/N
MAC0_TX_P/N[0:3]
MAC0_RX_P/N[0:3]
MAC0_RST
I2C_0
Clock
Reset
PCIe Hard
Block Gen3 x8
PCIE_MGT_TX_P/N[0:7] PCIE_MGT_RX_P/N[0:7] PCIE_RST PCIE_REFCLK_P/N
Clock
Buffer
MPSOC
RFSOC
Clock
Synchronizer
Level
Translator
Level
Translator
DDR4, x16
8GB + ECC
DDR4, x16
4GB + ECC
SFP28
SFP28
FTDI
Chip
Mini-USB
Conn
JTAG
TCK
TMS
TDI
TDO
UART
100G MAC0
MAC0_CLK_P/N
MAC0_TX_P/N[0:3]
MAC0_RX_P/N[0:3]
MAC0_RST
I2C_0
Clock
Reset
PCIe Hard
Block Gen3 x8
PCIE_REFCLK_P/N PCIE_RST PCIE_MGT_RX_P/N[0:7] PCIE_MGT_TX_P/N[0:7]
EEPROM
Clock Generator
I2C Level
Translator
MCU
Outlet Temp
Sensor
Inlet Temp
Sensor
I2C_0
I2C_2I2C_1
PSU FTDI
Chip
CLOCK
Buffer
Configuration
Block
IO[0:7]
SCK
CS
DDR4
DDR4_1_A[0:16]
DDR4_1_BA[0:1]
DDR4_1_DM[0:4]
DDR4_1_DQ[0:39]
DDR4_1_A\DQS_T/C[0:4]
DDR4_1_CLK_T/C
DDR4_1_RST
DDR4
DDR4_0_A[0:16]
DDR4_0_BA[0:1]
DDR4_0_DM[0:8]
DDR4_0_DQ[0:71]
DDR4_0_A\DQS_T/C[0:8]
DDR4_0_CLK_T/C
DDR4_0_RST
QSPI Flash
Memory
DDR4, x16
8GB + ECC
DDR4, x16
4GB + ECC
OR
Module
PM
PCIE EDGE FINGER
PS PS
VCC_0V72
VCC_0V85
VCC_0V9
VCC_1V2
VCC_1V8
VCC_3V3
VCC_12V
PCIE_12V
ATX_12V
PCIe Gen 3.0
PCIE_REFCLK_P/N
PCIe Gen 3.0
PPS_IN_MPSOC
PPS_IN_RFSOC
PPS_IN
PPS_OUT
25G
MAC
25G
MAC
100G MAC
X24621-092320
Chapter 1: Introduction
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Zynq UltraScale+ MPSoC Specification
The Zynq UltraScale+ MPSoC on the is an XCZU19EG-L2FFVD1760E. The -L2 speed grade
designates this is a low-voltage capable device, so it can operate at either a 0.72V or 0.85V
VCCINT core voltage. A comparison of the features of this device relave to other devices in the
same family is shown below. Refer to the Zynq UltraScale+ MPSoC Product Selecon Guide
(XMP104) for further details.
Figure 4: Zynq UltraScale+ MPSoC XCZU19EG Device
Zynq UltraScale+ RFSoC Specification
The Zynq UltraScale+ RFSoC device on the card is a XCZU21DR-L2FSVD1156E. The -L2 speed
grade designates this is a low-voltage capable device which can operate at either a 0.72V or
0.85V VCCINT core voltage. A comparison of the features of this device relave to other devices
in the same family is shown in the following gure. Refer to the Zynq UltraScale+ RFSoC Product
Selecon Guide for further details.
Chapter 1: Introduction
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Figure 5: Zynq UltraScale+ RFSoC XCZU21DR Device
Chapter 1: Introduction
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Chapter 2
Pin Mapping
This secon presents the pin mapping for the Zynq UltraScale+ MPSoC and Zynq UltraScale+
RFSoC devices.
Zynq UltraScale+ MPSoC ZU19 Pin Map
The following table presents the pin mapping for the Zynq UltraScale+ MPSoC ZU19 device.
Table 1: Zynq UltraScale+ MPSoC ZU19 Pin Map
Pin Number Signal Name Interface
AM20 BOARD_REV0 Board Rev
AM21 BOARD_REV1 Board Rev
AM22 BOARD_REV2 Board Rev
C14 SFP_HS_PWR_EN Card Power Throttle
P29 NMR Clock Synth Reset
AH23 CLK_GEN_AUX_CS_A0 Clock Synth SDIO Bus
AH20 CLK_GEN_AUX_SCLK Clock Synth SDIO Bus
AJ22 CLK_GEN_AUX_SDI_A1 Clock synth SDIO Bus
AJ21 CLK_GEN_AUX_SDIO Clock synth SDIO Bus
M33 MP_161.13MHZ_MAC_CLK_N Clock: 100G MAC Diff Clock Input (Neg)
M32 MP_161.13MHZ_MAC_CLK_P Clock: 100G MAC Diff Clock Input (Pos)
F28 MP_300MHZ_CLK_DDR_N Clock: DDR4 Diff Clock Input (Neg)
G27 MP_300MHZ_CLK_DDR_P Clock: DDR4 Diff Clock Input (Pos)
AH9 PCIE_MP_REFCLK_N Clock: PCIe Diff Clock (Neg)
AH10 PCIE_MP_REFCLK_P Clock: PCIe Diff Clock (Pos)
AU16 MP_156.25MHZ_CLK1_N Clock: SFP0 & SFP1 Diff Clock1 Input
(Neg)
AU17 MP_156.25MHZ_CLK1_P Clock: SFP0 & SFP1 Diff Clock1 Input
(Pos)
AU18 MP_156.25MHZ_CLK2_N Clock: SFP0 & SFP1 Diff Clock2 Input
(Neg)
AT19 MP_156.25MHZ_CLK2_P Clock: SFP0 & SFP1 Diff Clock2 Input
(Pos)
AK22 AUX_GPIO GPIO - Zynq UltraScale+ MPSoC <--
>Clock Synth
Chapter 2: Pin Mapping
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Table 1: Zynq UltraScale+ MPSoC ZU19 Pin Map (cont'd)
Pin Number Signal Name Interface
C30 CLK_GPIO_5 GPIO - Zynq UltraScale+ MPSoC <--
>Clock Synth
D29 CLK_GPIO_6 GPIO - Zynq UltraScale+ MPSoC <--
>Clock Synth
AP19 MPSOC_RFSOC_PL_GPIO1 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
F13 MPSOC_RFSOC_PL_GPIO10 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
E13 MPSOC_RFSOC_PL_GPIO11 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
E12 MPSOC_RFSOC_PL_GPIO12 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
AR19 MPSOC_RFSOC_PL_GPIO2 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
AP18 MPSOC_RFSOC_PL_GPIO3 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
AP17 MPSOC_RFSOC_PL_GPIO4 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
AN19 MPSOC_RFSOC_PL_GPIO5 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
AN18 MPSOC_RFSOC_PL_GPIO6 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
F15 MPSOC_RFSOC_PL_GPIO7 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
F14 MPSOC_RFSOC_PL_GPIO8 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
G14 MPSOC_RFSOC_PL_GPIO9 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
J30 MPSOC_RFSOC_PS_GPIO1 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PS
K30 MPSOC_RFSOC_PS_GPIO2 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PS
L29 MPSOC_RFSOC_PS_GPIO3 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PS
L30 MPSOC_RFSOC_PS_GPIO4 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PS
M29 MPSOC_RFSOC_PS_GPIO5 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PS
D14 MPSOC_MSP_GPIO1 GPIO - Zynq UltraScale+ MPSoC <-->SC
D13 MPSOC_MSP_GPIO2 GPIO - Zynq UltraScale+ MPSoC <-->SC
AH19 SOC_SCL I2C Bus
AJ18 SOC_SDA I2C Bus
M37 MAC_MP_T0_N Inter-SoC 100G MAC
M36 MAC_MP_T0_P Inter-SoC 100G MAC
L35 MAC_MP_T1_N Inter-SoC 100G MAC
L34 MAC_MP_T1_P Inter-SoC 100G MAC
Chapter 2: Pin Mapping
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Table 1: Zynq UltraScale+ MPSoC ZU19 Pin Map (cont'd)
Pin Number Signal Name Interface
K37 MAC_MP_T2_N Inter-SoC 100G MAC
K36 MAC_MP_T2_P Inter-SoC 100G MAC
J35 MAC_MP_T3_N Inter-SoC 100G MAC
J34 MAC_MP_T3_P Inter-SoC 100G MAC
M42 MAC_RF_TX0_N Inter-SoC 100G MAC
M41 MAC_RF_TX0_P Inter-SoC 100G MAC
L40 MAC_RF_TX1_N Inter-SoC 100G MAC
L39 MAC_RF_TX1_P Inter-SoC 100G MAC
K42 MAC_RF_TX2_N Inter-SoC 100G MAC
K41 MAC_RF_TX2_P Inter-SoC 100G MAC
J40 MAC_RF_TX3_N Inter-SoC 100G MAC
J39 MAC_RF_TX3_P Inter-SoC 100G MAC
BB16 MP_LED LED: MPSoC General Purpose LED1
F30 MP_PS_TEST_LED LED: MPSoC General Purpose LED2
AK19 MP_RST_REQ MPSoC-->SC Reset request
A29 CLK_GPIO_0 NOT USED
A30 CLK_GPIO_1 NOT USED
B29 CLK_GPIO_2 NOT USED
B30 CLK_GPIO_3 NOT USED
C29 CLK_GPIO_4 NOT USED
N30 CONFIG_EEPROM_WP NOT USED
B11 MP_SFP0_SCL NOT USED
B10 MP_SFP0_SDA NOT USED
A11 MP_SFP1_SCL NOT USED
A10 MP_SFP1_SDA NOT USED
AL23 PCIE_SOC_I2C_SCL NOT USED
AL24 PCIE_SOC_I2C_SDA NOT USED
AM16 PCIE_MP_PERST_LS# PCIe
AH17 PCIE_MP_WAKE_LS# PCIe
AH1 PCIE_RX0_N PCIe
AH2 PCIE_RX0_P PCIe
AJ3 PCIE_RX1_N PCIe
AJ4 PCIE_RX1_P PCIe
AK1 PCIE_RX2_N PCIe
AK2 PCIE_RX2_P PCIe
AL3 PCIE_RX3_N PCIe
AL4 PCIE_RX3_P PCIe
AM1 PCIE_RX4_N PCIe
AM2 PCIE_RX4_P PCIe
Chapter 2: Pin Mapping
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Table 1: Zynq UltraScale+ MPSoC ZU19 Pin Map (cont'd)
Pin Number Signal Name Interface
AN3 PCIE_RX5_N PCIe
AN4 PCIE_RX5_P PCIe
AP1 PCIE_RX6_N PCIe
AP2 PCIE_RX6_P PCIe
AR3 PCIE_RX7_N PCIe
AR4 PCIE_RX7_P PCIe
AG7 PCIE_TX0_N PCIe
AG8 PCIE_TX0_P PCIe
AH5 PCIE_TX1_N PCIe
AH6 PCIE_TX1_P PCIe
AJ7 PCIE_TX2_N PCIe
AJ8 PCIE_TX2_P PCIe
AK5 PCIE_TX3_N PCIe
AK6 PCIE_TX3_P PCIe
AL7 PCIE_TX4_N PCIe
AL8 PCIE_TX4_P PCIe
AM5 PCIE_TX5_N PCIe
AM6 PCIE_TX5_P PCIe
AN7 PCIE_TX6_N PCIe
AN8 PCIE_TX6_P PCIe
AP5 PCIE_TX7_N PCIe
AP6 PCIE_TX7_P PCIe
N25 PL_DDR4_2_A0 PL 72-bit DDR4
P26 PL_DDR4_2_A6 PL 72-bit DDR4
E25 PL_DDR4_2_BA1 PL 72-bit DDR4
M28 PL_DDR4_2_BG0 PL 72-bit DDR4
R27 PL_DDR4_2_PAR PL 72-bit DDR4
D25 PL_DDR4_2_CAS# PL 72-bit DDR4
K26 PL_DDR4_2_A7 PL 72-bit DDR4
P25 PL_DDR4_2_A8 PL 72-bit DDR4
F26 PL_DDR4_2_RAS# PL 72-bit DDR4
N27 PL_DDR4_2_A13 PL 72-bit DDR4
J25 MP_DDR4_RST# PL 72-bit DDR4
N26 PL_DDR4_2_BA0 PL 72-bit DDR4
K25 PL_DDR4_2_A1 PL 72-bit DDR4
P27 PL_DDR4_2_A2 PL 72-bit DDR4
H26 PL_DDR4_2_TEN PL 72-bit DDR4
K28 PL_DDR4_2_WE# PL 72-bit DDR4
F25 PL_DDR4_2_A3 PL 72-bit DDR4
Chapter 2: Pin Mapping
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Table 1: Zynq UltraScale+ MPSoC ZU19 Pin Map (cont'd)
Pin Number Signal Name Interface
M27 PL_DDR4_2_A9 PL 72-bit DDR4
E27 PL_DDR4_2_CK_P PL 72-bit DDR4
L28 PL_DDR4_2_A10 PL 72-bit DDR4
E28 PL_DDR4_2_CK_N PL 72-bit DDR4
G26 PL_DDR4_2_CS1# PL 72-bit DDR4
H25 PL_DDR4_2_ALERT# PL 72-bit DDR4
J28 PL_DDR4_2_CKE PL 72-bit DDR4
L26 PL_DDR4_2_A5 PL 72-bit DDR4
C25 PL_DDR4_2_DM0# PL 72-bit DDR4
M21 PL_DDR4_2_DM1# PL 72-bit DDR4
R24 PL_DDR4_2_DM2# PL 72-bit DDR4
H20 PL_DDR4_2_DM3# PL 72-bit DDR4
L20 PL_DDR4_2_DM8# PL 72-bit DDR4
R17 PL_DDR4_2_DM5# PL 72-bit DDR4
D22 PL_DDR4_2_DM6# PL 72-bit DDR4
H17 PL_DDR4_2_DM7# PL 72-bit DDR4
D18 PL_DDR4_2_DM4# PL 72-bit DDR4
C24 PL_DDR4_2_DQ5 PL 72-bit DDR4
A26 PL_DDR4_2_DQ6 PL 72-bit DDR4
J24 PL_DDR4_2_DQ14 PL 72-bit DDR4
K23 PL_DDR4_2_DQ8 PL 72-bit DDR4
J22 PL_DDR4_2_DQ13 PL 72-bit DDR4
K22 PL_DDR4_2_DQ10 PL 72-bit DDR4
H22 PL_DDR4_2_DQ9 PL 72-bit DDR4
J23 PL_DDR4_2_DQ15 PL 72-bit DDR4
R22 PL_DDR4_2_DQ21 PL 72-bit DDR4
M24 PL_DDR4_2_DQ22 PL 72-bit DDR4
M22 PL_DDR4_2_DQ16 PL 72-bit DDR4
N24 PL_DDR4_2_DQ18 PL 72-bit DDR4
B26 PL_DDR4_2_DQ2 PL 72-bit DDR4
P22 PL_DDR4_2_DQ19 PL 72-bit DDR4
R23 PL_DDR4_2_DQ17 PL 72-bit DDR4
P23 PL_DDR4_2_DQ23 PL 72-bit DDR4
M23 PL_DDR4_2_DQ20 PL 72-bit DDR4
G21 PL_DDR4_2_DQ29 PL 72-bit DDR4
G23 PL_DDR4_2_DQ27 PL 72-bit DDR4
F21 PL_DDR4_2_DQ31 PL 72-bit DDR4
E23 PL_DDR4_2_DQ26 PL 72-bit DDR4
F20 PL_DDR4_2_DQ28 PL 72-bit DDR4
Chapter 2: Pin Mapping
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Table 1: Zynq UltraScale+ MPSoC ZU19 Pin Map (cont'd)
Pin Number Signal Name Interface
G24 PL_DDR4_2_DQ30 PL 72-bit DDR4
B28 PL_DDR4_2_DQ4 PL 72-bit DDR4
G22 PL_DDR4_2_DQ25 PL 72-bit DDR4
E22 PL_DDR4_2_DQ24 PL 72-bit DDR4
L18 PL_DDR4_2_DQ65 PL 72-bit DDR4
J17 PL_DDR4_2_DQ66 PL 72-bit DDR4
L16 PL_DDR4_2_DQ71 PL 72-bit DDR4
K18 PL_DDR4_2_DQ70 PL 72-bit DDR4
M19 PL_DDR4_2_DQ69 PL 72-bit DDR4
J18 PL_DDR4_2_DQ64 PL 72-bit DDR4
M16 PL_DDR4_2_DQ67 PL 72-bit DDR4
J19 PL_DDR4_2_DQ68 PL 72-bit DDR4
A24 PL_DDR4_2_DQ3 PL 72-bit DDR4
N20 PL_DDR4_2_DQ44 PL 72-bit DDR4
P17 PL_DDR4_2_DQ47 PL 72-bit DDR4
R20 PL_DDR4_2_DQ41 PL 72-bit DDR4
N17 PL_DDR4_2_DQ42 PL 72-bit DDR4
P20 PL_DDR4_2_DQ40 PL 72-bit DDR4
N16 PL_DDR4_2_DQ43 PL 72-bit DDR4
R18 PL_DDR4_2_DQ45 PL 72-bit DDR4
N19 PL_DDR4_2_DQ46 PL 72-bit DDR4
D20 PL_DDR4_2_DQ48 PL 72-bit DDR4
C22 PL_DDR4_2_DQ49 PL 72-bit DDR4
C27 PL_DDR4_2_DQ0 PL 72-bit DDR4
A21 PL_DDR4_2_DQ50 PL 72-bit DDR4
B22 PL_DDR4_2_DQ51 PL 72-bit DDR4
C21 PL_DDR4_2_DQ52 PL 72-bit DDR4
B23 PL_DDR4_2_DQ53 PL 72-bit DDR4
A20 PL_DDR4_2_DQ54 PL 72-bit DDR4
A23 PL_DDR4_2_DQ55 PL 72-bit DDR4
F16 PL_DDR4_2_DQ62 PL 72-bit DDR4
E18 PL_DDR4_2_DQ63 PL 72-bit DDR4
G17 PL_DDR4_2_DQ58 PL 72-bit DDR4
E17 PL_DDR4_2_DQ59 PL 72-bit DDR4
B24 PL_DDR4_2_DQ7 PL 72-bit DDR4
H19 PL_DDR4_2_DQ61 PL 72-bit DDR4
G19 PL_DDR4_2_DQ57 PL 72-bit DDR4
G16 PL_DDR4_2_DQ56 PL 72-bit DDR4
G18 PL_DDR4_2_DQ60 PL 72-bit DDR4
Chapter 2: Pin Mapping
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Table 1: Zynq UltraScale+ MPSoC ZU19 Pin Map (cont'd)
Pin Number Signal Name Interface
C19 PL_DDR4_2_DQ32 PL 72-bit DDR4
C17 PL_DDR4_2_DQ39 PL 72-bit DDR4
B16 PL_DDR4_2_DQ35 PL 72-bit DDR4
B19 PL_DDR4_2_DQ36 PL 72-bit DDR4
C16 PL_DDR4_2_DQ37 PL 72-bit DDR4
A18 PL_DDR4_2_DQ38 PL 72-bit DDR4
A25 PL_DDR4_2_DQ1 PL 72-bit DDR4
A16 PL_DDR4_2_DQ33 PL 72-bit DDR4
A19 PL_DDR4_2_DQ34 PL 72-bit DDR4
H24 PL_DDR4_2_DQ11 PL 72-bit DDR4
K21 PL_DDR4_2_DQ12 PL 72-bit DDR4
A28 PL_DDR4_2_DQS0_N PL 72-bit DDR4
B27 PL_DDR4_2_DQS0_P PL 72-bit DDR4
J20 PL_DDR4_2_DQS1_N PL 72-bit DDR4
K20 PL_DDR4_2_DQS1_P PL 72-bit DDR4
N22 PL_DDR4_2_DQS2_N PL 72-bit DDR4
N21 PL_DDR4_2_DQS2_P PL 72-bit DDR4
F24 PL_DDR4_2_DQS3_N PL 72-bit DDR4
F23 PL_DDR4_2_DQS3_P PL 72-bit DDR4
K16 PL_DDR4_2_DQS8_N PL 72-bit DDR4
K17 PL_DDR4_2_DQS8_P PL 72-bit DDR4
P18 PL_DDR4_2_DQS5_N PL 72-bit DDR4
P19 PL_DDR4_2_DQS5_P PL 72-bit DDR4
B21 PL_DDR4_2_DQS6_N PL 72-bit DDR4
C20 PL_DDR4_2_DQS6_P PL 72-bit DDR4
F18 PL_DDR4_2_DQS7_N PL 72-bit DDR4
F19 PL_DDR4_2_DQS7_P PL 72-bit DDR4
B17 PL_DDR4_2_DQS4_N PL 72-bit DDR4
B18 PL_DDR4_2_DQS4_P PL 72-bit DDR4
J27 PL_DDR4_2_ACT# PL 72-bit DDR4
K27 PL_DDR4_2_A4 PL 72-bit DDR4
R26 PL_DDR4_2_A11 PL 72-bit DDR4
D27 PL_DDR4_2_CS# PL 72-bit DDR4
E26 PL_DDR4_2_A12 PL 72-bit DDR4
D28 PL_DDR4_2_ODT PL 72-bit DDR4
H27 MP_DDR4_GATING PL 72-bit DDR4 (gating signal)
L13 PPS_IN_PL PPS Input
L15 MPSOC_PPS_OUT PPS Output
BA30 PS_DDR4_2_A0 PS 36-bit DDR4
Chapter 2: Pin Mapping
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Table 1: Zynq UltraScale+ MPSoC ZU19 Pin Map (cont'd)
Pin Number Signal Name Interface
BA32 PS_DDR4_2_A1 PS 36-bit DDR4
AW33 PS_DDR4_2_A10 PS 36-bit DDR4
AV31 PS_DDR4_2_A11 PS 36-bit DDR4
AW31 PS_DDR4_2_A12 PS 36-bit DDR4
AV30 PS_DDR4_2_A13 PS 36-bit DDR4
BB32 PS_DDR4_2_A2 PS 36-bit DDR4
BB33 PS_DDR4_2_A3 PS 36-bit DDR4
BB30 PS_DDR4_2_A4 PS 36-bit DDR4
BB31 PS_DDR4_2_A5 PS 36-bit DDR4
AT30 PS_DDR4_2_A6 PS 36-bit DDR4
AU33 PS_DDR4_2_A7 PS 36-bit DDR4
AU30 PS_DDR4_2_A8 PS 36-bit DDR4
AU31 PS_DDR4_2_A9 PS 36-bit DDR4
AT32 PS_DDR4_2_ACT# PS 36-bit DDR4
AR31 PS_DDR4_2_ALERT# PS 36-bit DDR4
AR30 PS_DDR4_2_BA0 PS 36-bit DDR4
AV33 PS_DDR4_2_BA1 PS 36-bit DDR4
AV34 PS_DDR4_2_BG0 PS 36-bit DDR4
AY31 PS_DDR4_2_CAS# PS 36-bit DDR4
AY29 PS_DDR4_2_CK_N PS 36-bit DDR4
BA29 PS_DDR4_2_CK_P PS 36-bit DDR4
BA34 PS_DDR4_2_CKE PS 36-bit DDR4
BA33 PS_DDR4_2_CS# PS 36-bit DDR4
AY22 PS_DDR4_2_DM1# PS 36-bit DDR4
AY26 PS_DDR4_2_DM3# PS 36-bit DDR4
AT23 PS_DDR4_2_DM0# PS 36-bit DDR4
AU28 PS_DDR4_2_DM2# PS 36-bit DDR4
BA35 PS_DDR4_2_DM4# PS 36-bit DDR4
AW24 PS_DDR4_2_DQ13 PS 36-bit DDR4
AW23 PS_DDR4_2_DQ14 PS 36-bit DDR4
BB28 PS_DDR4_2_DQ25 PS 36-bit DDR4
BB26 PS_DDR4_2_DQ27 PS 36-bit DDR4
AW28 PS_DDR4_2_DQ24 PS 36-bit DDR4
AY25 PS_DDR4_2_DQ30 PS 36-bit DDR4
AY27 PS_DDR4_2_DQ28 PS 36-bit DDR4
BB25 PS_DDR4_2_DQ31 PS 36-bit DDR4
AU25 PS_DDR4_2_DQ1 PS 36-bit DDR4
AR25 PS_DDR4_2_DQ4 PS 36-bit DDR4
AT22 PS_DDR4_2_DQ6 PS 36-bit DDR4
Chapter 2: Pin Mapping
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Table 1: Zynq UltraScale+ MPSoC ZU19 Pin Map (cont'd)
Pin Number Signal Name Interface
AT25 PS_DDR4_2_DQ0 PS 36-bit DDR4
BB23 PS_DDR4_2_DQ8 PS 36-bit DDR4
AU23 PS_DDR4_2_DQ3 PS 36-bit DDR4
AV23 PS_DDR4_2_DQ7 PS 36-bit DDR4
AV25 PS_DDR4_2_DQ5 PS 36-bit DDR4
AU22 PS_DDR4_2_DQ2 PS 36-bit DDR4
AW26 PS_DDR4_2_DQ18 PS 36-bit DDR4
AT28 PS_DDR4_2_DQ21 PS 36-bit DDR4
AV26 PS_DDR4_2_DQ16 PS 36-bit DDR4
AT27 PS_DDR4_2_DQ23 PS 36-bit DDR4
AW27 PS_DDR4_2_DQ19 PS 36-bit DDR4
AR27 PS_DDR4_2_DQ20 PS 36-bit DDR4
BA22 PS_DDR4_2_DQ11 PS 36-bit DDR4
AV28 PS_DDR4_2_DQ17 PS 36-bit DDR4
AR26 PS_DDR4_2_DQ22 PS 36-bit DDR4
BB37 PS_DDR4_2_DQ35 PS 36-bit DDR4
BB35 PS_DDR4_2_DQ33 PS 36-bit DDR4
BB36 PS_DDR4_2_DQ37 PS 36-bit DDR4
AY35 PS_DDR4_2_DQ34 PS 36-bit DDR4
BB38 PS_DDR4_2_DQ39 PS 36-bit DDR4
AW36 PS_DDR4_2_DQ36 PS 36-bit DDR4
AY36 PS_DDR4_2_DQ38 PS 36-bit DDR4
AY37 PS_DDR4_2_DQ32 PS 36-bit DDR4
AV24 PS_DDR4_2_DQ12 PS 36-bit DDR4
AW22 PS_DDR4_2_DQ10 PS 36-bit DDR4
BA23 PS_DDR4_2_DQ15 PS 36-bit DDR4
BB22 PS_DDR4_2_DQ9 PS 36-bit DDR4
BA28 PS_DDR4_2_DQ29 PS 36-bit DDR4
BA25 PS_DDR4_2_DQ26 PS 36-bit DDR4
BA24 PS_DDR4_2_DQS1_N PS 36-bit DDR4
AY24 PS_DDR4_2_DQS1_P PS 36-bit DDR4
BB27 PS_DDR4_2_DQS3_N PS 36-bit DDR4
BA27 PS_DDR4_2_DQS3_P PS 36-bit DDR4
AT24 PS_DDR4_2_DQS0_N PS 36-bit DDR4
AR24 PS_DDR4_2_DQS0_P PS 36-bit DDR4
AU27 PS_DDR4_2_DQS2_N PS 36-bit DDR4
AU26 PS_DDR4_2_DQS2_P PS 36-bit DDR4
BA38 PS_DDR4_2_DQS4_N PS 36-bit DDR4
BA37 PS_DDR4_2_DQS4_P PS 36-bit DDR4
Chapter 2: Pin Mapping
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Table 1: Zynq UltraScale+ MPSoC ZU19 Pin Map (cont'd)
Pin Number Signal Name Interface
AT33 PS_DDR4_2_MP_BG1 PS 36-bit DDR4
AY30 PS_DDR4_2_ODT PS 36-bit DDR4
AR29 PS_DDR4_2_PAR PS 36-bit DDR4
AU32 PS_DDR4_2_RAS# PS 36-bit DDR4
AR33 PS_DDR4_2_RST# PS 36-bit DDR4
AY32 PS_DDR4_2_WE# PS 36-bit DDR4
AH24 MP_QSPI_LWR_CLK QSPI Flash
AP24 MP_QSPI_LWR_CS# QSPI Flash
AP23 MP_QSPI_LWR_DQ0 QSPI Flash
AH25 MP_QSPI_LWR_DQ1 QSPI Flash
AM27 MP_QSPI_LWR_DQ2 QSPI Flash
AN29 MP_QSPI_LWR_DQ3 QSPI Flash
AK24 MP_QSPI_UPR_CLK QSPI Flash
AP27 MP_QSPI_UPR_CS# QSPI Flash
AP28 MP_QSPI_UPR_DQ0 QSPI Flash
AP29 MP_QSPI_UPR_DQ1 QSPI Flash
AJ23 MP_QSPI_UPR_DQ2 QSPI Flash
AJ24 MP_QSPI_UPR_DQ3 QSPI Flash
E15 SOC_INT# Zynq UltraScale+ RFSoC and
Zynq UltraScale+ MPSoC interrupt to SC
W29 MP_PS_RST# SC-->Zynq UltraScale+ MPSoC PS Reset
BA17 MP_CPU_RST# SC-->Zynq UltraScale+ MPSoC User
Reset
F33 SFP0_161.13MHZ_CLK_N SFP0
F32 SFP0_161.13MHZ_CLK_P SFP0
H33 SFP0_IN_CLK_C_N SFP0
H32 SFP0_IN_CLK_C_P SFP0
D12 SFP0_MOD_ABS SFP0
AT17 SFP0_REC_CLK_C_N SFP0
AT18 SFP0_REC_CLK_C_P SFP0
C12 SFP0_RX_LOS SFP0
E40 SFP0_RX_N SFP0
E39 SFP0_RX_P SFP0
B13 SFP0_TX_DISABLE SFP0
B12 SFP0_TX_FAULT SFP0
E35 SFP0_TX_N SFP0
E34 SFP0_TX_P SFP0
B33 SFP1_161.13MHZ_CLK_N SFP1
B32 SFP1_161.13MHZ_CLK_P SFP1
D33 SFP1_IN_CLK_C_N SFP1
Chapter 2: Pin Mapping
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Table 1: Zynq UltraScale+ MPSoC ZU19 Pin Map (cont'd)
Pin Number Signal Name Interface
D32 SFP1_IN_CLK_C_P SFP1
A15 SFP1_MOD_ABS SFP1
AR16 SFP1_REC_CLK_C_N SFP1
AR17 SFP1_REC_CLK_C_P SFP1
A14 SFP1_RX_LOS SFP1
A40 SFP1_RX_N SFP1
A39 SFP1_RX_P SFP1
B14 SFP1_TX_DISABLE SFP1
A13 SFP1_TX_FAULT SFP1
A35 SFP1_TX_N SFP1
A34 SFP1_TX_P SFP1
AN24 MP_UART0_RXD UART to Maintenance Port
AN25 MP_UART0_TXD UART to Maintenance Port
Zynq UltraScale+ RFSoC ZU21 Pin Map
The following table presents the pin mapping for the Zynq UltraScale+ RFSoC ZU21 device.
Table 2: Zynq UltraScale+ RFSoC ZU21 Pin Map
Pin Number Signal Name Interface
T29 RF_161.13MHZ_MAC_CLK_N Clock: 100G MAC Diff Clock Input (Neg)
T28 RF_161.13MHZ_MAC_CLK_P Clock: 100G MAC Diff Clock Input (Pos)
AB6 RF_300MHZ_CLK_DDR_N Clock: DDR4 Diff Clock Input (Neg)
AB7 RF_300MHZ_CLK_DDR_P Clock: DDR4 Diff Clock Input (Pos)
M29 PCIE_RF_REFCLK_N Clock: PCIe Diff Clock (Neg)
M28 PCIE_RF_REFCLK_P Clock: PCIe Diff Clock (Pos)
AK2 RF_156.25MHZ_CLK1_N Clock: User Diff Clock1 Input (Neg)
AK3 RF_156.25MHZ_CLK1_P Clock: User Diff Clock1 Input (Pos)
AJ2 RF_156.25MHZ_CLK2_N Clock: User Diff Clock2 Input (Neg)
AJ3 RF_156.25MHZ_CLK2_P Clock: User Diff Clock2 Input (Pos)
AK8 GP1 GPIO - Zynq UltraScale+
Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
H1 GP10 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
G3 GP11 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
Chapter 2: Pin Mapping
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Table 2: Zynq UltraScale+ RFSoC ZU21 Pin Map (cont'd)
Pin Number Signal Name Interface
G2 GP12 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
AK7 GP2 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
AJ9 GP3 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
AJ8 GP4 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
AH5 GP5 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
AH4 GP6 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
J3 GP7 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
J2 GP8 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
H2 GP9 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
A18 MPSOC_RFSOC_PS_GPIO1 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PS
B19 MPSOC_RFSOC_PS_GPIO2 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PS
A19 MPSOC_RFSOC_PS_GPIO3 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PS
A20 MPSOC_RFSOC_PS_GPIO4 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PS
C19 MPSOC_RFSOC_PS_GPIO5 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PS
AF6 SOC_SCL I2C Bus
AE8 SOC_SDA I2C Bus
P34 MAC_MP_TX0_N Inter-SoC 100G MAC
P33 MAC_MP_TX0_P Inter-SoC 100G MAC
M34 MAC_MP_TX1_N Inter-SoC 100G MAC
M33 MAC_MP_TX1_P Inter-SoC 100G MAC
K34 MAC_MP_TX2_N Inter-SoC 100G MAC
K33 MAC_MP_TX2_P Inter-SoC 100G MAC
H34 MAC_MP_TX3_N Inter-SoC 100G MAC
H33 MAC_MP_TX3_P Inter-SoC 100G MAC
R31 MAC_RF_T0_N Inter-SoC 100G MAC
R30 MAC_RF_T0_P Inter-SoC 100G MAC
N31 MAC_RF_T1_N Inter-SoC 100G MAC
N30 MAC_RF_T1_P Inter-SoC 100G MAC
L31 MAC_RF_T2_N Inter-SoC 100G MAC
L30 MAC_RF_T2_P Inter-SoC 100G MAC
Chapter 2: Pin Mapping
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