Xilinx T1 User manual

T1 Telco Accelerator Card
User Guide
UG1495 (v1.0) December 17, 2021
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Table of Contents
Chapter 1: Introduction.............................................................................................. 4
Features........................................................................................................................................5
Overview.......................................................................................................................................6
Chapter 2: Pin Mapping...............................................................................................9
Zynq UltraScale+ MPSoC ZU19 Pin Map................................................................................... 9
Zynq UltraScale+ RFSoC ZU21 Pin Map...................................................................................19
Satellite Controller Pin Map..................................................................................................... 28
Chapter 3: Ports............................................................................................................. 31
SFP28 Ports.................................................................................................................................31
Maintenance Port for UART and JTAG Access........................................................................ 31
IEEE 1588 Support..................................................................................................................... 32
PCI Express.................................................................................................................................33
Chapter 4: Clocking......................................................................................................34
IEEE 1588 Clocking.................................................................................................................... 34
PCIe Reference Clock................................................................................................................ 35
SFP28 Clocks...............................................................................................................................35
DDR4 SDRAM Reference Clocks...............................................................................................36
MAC to MAC Interface Reference Clock..................................................................................36
User Clocks.................................................................................................................................36
Chapter 5: LEDs.............................................................................................................. 38
Chapter 6: Xilinx Design Constraints (XDC) File.......................................... 39
Appendix A: Programming the Devices Using JTAG.................................. 40
Flashing the Images to ZU19 Zynq UltraScale+ MPSoC QSPI Using SDK........................... 43
Flashing the Images to ZU21 Zynq UltraScale+ RFSoC QSPI Using SDK............................ 45
Programming the Bitstreams Directly ...................................................................................46
Flashing the Images Using the Program Flash Application.................................................47
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Appendix B: Regulatory Compliance Statements...................................... 49
FCC Class A Products.................................................................................................................49
Safety.......................................................................................................................................... 49
EMC Compliance........................................................................................................................50
FCC Class A User Information..................................................................................................50
VCCI Class A Statement............................................................................................................ 51
Appendix C: Additional Resources and Legal Notices............................. 52
Xilinx Resources.........................................................................................................................52
Documentation Navigator and Design Hubs.........................................................................52
References..................................................................................................................................53
Revision History.........................................................................................................................53
Please Read: Important Legal Notices................................................................................... 53
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T1 Telco Accelerator Card User Guide 3
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Chapter 1
Introduction
The Xilinx® T1 Telco accelerator card is a PCI Express® (PCIe) Gen3 x16 compliant card featuring
the 16 nm Zynq® UltraScale+™ MPSoC and Zynq UltraScale+ RFSoC devices. The T1 form factor
is full height, half length (FHHL) and single slot, with a PCIe Gen 3 x16 interface that is x8x8
bifurcated providing x8 links from the host to each MPSoC and RFSoC device. Target applicaons
for the T1 card include:
• O-RAN fronthaul terminaon
• 4G LTE and 5G NR high-PHY lookaside acceleraon (supporng 3GPP split opon 7-2x)
• 5G layer 1 (L1) high-PHY lookaside acceleraon
•Oponal use of fronthaul ports for a midhaul (F1) interface between distributed and
centralized units (DU and CU)
• 4G LTE and 5G NR inline acceleraon of L1 funcons (supporng 3GPP split opon 7-2x) for
up to 4TRX
Figure 1: T1 Telco Accelerator Card
Chapter 1: Introduction
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Features
A high-level block diagram of the T1 card card is shown in the following gure.
Figure 2: T1 card High-Level Block Diagram
X25153-030821
ZU21DR
L1 Channel Coding
· Hardened LDPC / TURBO
Codec
· Polar Codec
· HARQ Buffer Management
· Channel Coding Wrapper
Logic
ZU19EG
Network Interface
Fronthaul/Midhaul
4GB DDR4
(PL)
2GB DDR4
(PS)
4GB DDR4
(PL)
2GB DDR4
(PS)
Timing Circuit
TCXO/OCXO
Board Management
Controller
SFP28 Optics
SFP28 Optics
25G
25G
25G
25G
PPS IN
PPS OUT
Gen3 x16 with Bifurcation
Gen3 x8 Gen3 x8
100G
The main features and components of the T1 card are as follows:
• Xilinx ZU19EG MPSoC device targeng 5G fronthaul terminaon
• Xilinx ZU21DR RFSoC device targeng L1 channel coding
• Dual NOR ash of 2x 256 MB in QSPI mode for Zynq UltraScale+ MPSoC
• Dual NOR ash of 2x 256 MB in QSPI mode for Zynq UltraScale+ RFSoC
• 4 GB of DDR4 programmable logic (PL) memory to each Zynq UltraScale+ MPSoC and Zynq
UltraScale+ RFSoC device
• 2 GB of DDR4 processor system (PS) memory to each Zynq UltraScale+ MPSoC and Zynq
UltraScale+ RFSoC device
• 100G (MAC-to-MAC) communicaon link between Zynq UltraScale+ MPSoC and Zynq
UltraScale+ RFSoC devices
• Two SFP28 cages supporng up to 25G signaling and pluggable opcs
• IEEE 1588 Network Synchronizer ming circuit with PPS in/out connectors
• Satellite controller for IPMI compliant monitoring and telemetry
• Bifurcated x8x8 PCIe Gen 3 x16 link to the host from each FPGA
• FHHL form factor with a 75W power envelope
Chapter 1: Introduction
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• x16 standard card form factor (FHHL), single slot (111.15 mm x 167.65 mm)
• Maintenance port for card maintenance and developer access using the DMB II Interface
(proprietary, requires Xilinx® DMB II kit)
Overview
The system hardware contains a single PCB assembly. The MNC2 card is built with a XCZU21DR
Zynq UltraScale+ RFSoC and a XCZU19EG Zynq UltraScale+ MPSoC. The connecvity includes
two 25G interfaces and one x16 Gen 3.0 PCIe interface. Each SoC acts as a Gen3.0 x8 endpoint
with respect to root complex. One DDR4 Memory controller is implemented inside the PL
secon of both SoCs. A second set of DDR4 memory is interfaced to PS secon of both SoCs.
One 100G transceiver is implemented on both SoCs for inter-SoC communicaon. A detailed
block diagram of the T1 card card is shown in the following gure.
Figure 3: Detailed T1 card Block Diagram
Zync UltraScale+
RFSoC
XCZU21DR
-L2FSVD1156E
Zync UltraScale+
MPSoC
XCZU19EG
-L2FFVD1760E
QSPI Flash
Memory
Configuration
Block
IO[0:7]
SCK
CS
DDR4
DDR4_1_A[0:16]
DDR4_1_BA[0:1]
DDR4_1_DM[0:4]
DDR4_1_DQ[0:39]
DDR4_1_A\DQS_T/C[0:4]
DDR4_1_CLK_T/C
DDR4_1_RST
DDR4
DDR4_0_A[0:16]
DDR4_0_BA[0:1]
DDR4_0_DM[0:8]
DDR4_0_DQ[0:71]
DDR4_0_A\DQS_T/C[0:8]
DDR4_0_CLK_T/C
DDR4_0_RST
I2C_0
25G MAC0
GT_RX_P/N
GT_RX_P/N
SFP0_REFCLK_RST
I2C_1
25G MAC1
GT_RX_P/N
GT_RX_P/N
SFP1_REFCLK_RST
JTAG
TCK
TMS
TDI
TDO
UART
100G MAC0
MAC0_CLK_P/N
MAC0_TX_P/N[0:3]
MAC0_RX_P/N[0:3]
MAC0_RST
I2C_0
Clock
Reset
PCIe Hard
Block Gen3 x8
PCIE_MGT_TX_P/N[0:7] PCIE_MGT_RX_P/N[0:7] PCIE_RST PCIE_REFCLK_P/N
Clock
Buffer
MPSOC
RFSOC
Clock
Synchronizer
Level
Translator
Level
Translator
DDR4, x16
8GB + ECC
DDR4, x16
4GB + ECC
SFP28
SFP28
FTDI
Chip
Mini-USB
Conn
JTAG
TCK
TMS
TDI
TDO
UART
100G MAC0
MAC0_CLK_P/N
MAC0_TX_P/N[0:3]
MAC0_RX_P/N[0:3]
MAC0_RST
I2C_0
Clock
Reset
PCIe Hard
Block Gen3 x8
PCIE_REFCLK_P/N PCIE_RST PCIE_MGT_RX_P/N[0:7] PCIE_MGT_TX_P/N[0:7]
EEPROM
Clock Generator
I2C Level
Translator
MCU
Outlet Temp
Sensor
Inlet Temp
Sensor
I2C_0
I2C_2I2C_1
PSU FTDI
Chip
CLOCK
Buffer
Configuration
Block
IO[0:7]
SCK
CS
DDR4
DDR4_1_A[0:16]
DDR4_1_BA[0:1]
DDR4_1_DM[0:4]
DDR4_1_DQ[0:39]
DDR4_1_A\DQS_T/C[0:4]
DDR4_1_CLK_T/C
DDR4_1_RST
DDR4
DDR4_0_A[0:16]
DDR4_0_BA[0:1]
DDR4_0_DM[0:8]
DDR4_0_DQ[0:71]
DDR4_0_A\DQS_T/C[0:8]
DDR4_0_CLK_T/C
DDR4_0_RST
QSPI Flash
Memory
DDR4, x16
8GB + ECC
DDR4, x16
4GB + ECC
OR
Module
PM
PCIE EDGE FINGER
PS PS
VCC_0V72
VCC_0V85
VCC_0V9
VCC_1V2
VCC_1V8
VCC_3V3
VCC_12V
PCIE_12V
ATX_12V
PCIe Gen 3.0
PCIE_REFCLK_P/N
PCIe Gen 3.0
PPS_IN_MPSOC
PPS_IN_RFSOC
PPS_IN
PPS_OUT
25G
MAC
25G
MAC
100G MAC
X24621-092320
Chapter 1: Introduction
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Zynq UltraScale+ MPSoC Specification
The Zynq UltraScale+ MPSoC on the is an XCZU19EG-L2FFVD1760E. The -L2 speed grade
designates this is a low-voltage capable device, so it can operate at either a 0.72V or 0.85V
VCCINT core voltage. A comparison of the features of this device relave to other devices in the
same family is shown below. Refer to the Zynq UltraScale+ MPSoC Product Selecon Guide
(XMP104) for further details.
Figure 4: Zynq UltraScale+ MPSoC XCZU19EG Device
Zynq UltraScale+ RFSoC Specification
The Zynq UltraScale+ RFSoC device on the card is a XCZU21DR-L2FSVD1156E. The -L2 speed
grade designates this is a low-voltage capable device which can operate at either a 0.72V or
0.85V VCCINT core voltage. A comparison of the features of this device relave to other devices
in the same family is shown in the following gure. Refer to the Zynq UltraScale+ RFSoC Product
Selecon Guide for further details.
Chapter 1: Introduction
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Figure 5: Zynq UltraScale+ RFSoC XCZU21DR Device
Chapter 1: Introduction
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Chapter 2
Pin Mapping
This secon presents the pin mapping for the Zynq UltraScale+ MPSoC and Zynq UltraScale+
RFSoC devices.
Zynq UltraScale+ MPSoC ZU19 Pin Map
The following table presents the pin mapping for the Zynq UltraScale+ MPSoC ZU19 device.
Table 1: Zynq UltraScale+ MPSoC ZU19 Pin Map
Pin Number Signal Name Interface
AM20 BOARD_REV0 Board Rev
AM21 BOARD_REV1 Board Rev
AM22 BOARD_REV2 Board Rev
C14 SFP_HS_PWR_EN Card Power Throttle
P29 NMR Clock Synth Reset
AH23 CLK_GEN_AUX_CS_A0 Clock Synth SDIO Bus
AH20 CLK_GEN_AUX_SCLK Clock Synth SDIO Bus
AJ22 CLK_GEN_AUX_SDI_A1 Clock synth SDIO Bus
AJ21 CLK_GEN_AUX_SDIO Clock synth SDIO Bus
M33 MP_161.13MHZ_MAC_CLK_N Clock: 100G MAC Diff Clock Input (Neg)
M32 MP_161.13MHZ_MAC_CLK_P Clock: 100G MAC Diff Clock Input (Pos)
F28 MP_300MHZ_CLK_DDR_N Clock: DDR4 Diff Clock Input (Neg)
G27 MP_300MHZ_CLK_DDR_P Clock: DDR4 Diff Clock Input (Pos)
AH9 PCIE_MP_REFCLK_N Clock: PCIe Diff Clock (Neg)
AH10 PCIE_MP_REFCLK_P Clock: PCIe Diff Clock (Pos)
AU16 MP_156.25MHZ_CLK1_N Clock: SFP0 & SFP1 Diff Clock1 Input
(Neg)
AU17 MP_156.25MHZ_CLK1_P Clock: SFP0 & SFP1 Diff Clock1 Input
(Pos)
AU18 MP_156.25MHZ_CLK2_N Clock: SFP0 & SFP1 Diff Clock2 Input
(Neg)
AT19 MP_156.25MHZ_CLK2_P Clock: SFP0 & SFP1 Diff Clock2 Input
(Pos)
AK22 AUX_GPIO GPIO - Zynq UltraScale+ MPSoC <--
>Clock Synth
Chapter 2: Pin Mapping
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Table 1: Zynq UltraScale+ MPSoC ZU19 Pin Map (cont'd)
Pin Number Signal Name Interface
C30 CLK_GPIO_5 GPIO - Zynq UltraScale+ MPSoC <--
>Clock Synth
D29 CLK_GPIO_6 GPIO - Zynq UltraScale+ MPSoC <--
>Clock Synth
AP19 MPSOC_RFSOC_PL_GPIO1 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
F13 MPSOC_RFSOC_PL_GPIO10 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
E13 MPSOC_RFSOC_PL_GPIO11 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
E12 MPSOC_RFSOC_PL_GPIO12 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
AR19 MPSOC_RFSOC_PL_GPIO2 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
AP18 MPSOC_RFSOC_PL_GPIO3 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
AP17 MPSOC_RFSOC_PL_GPIO4 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
AN19 MPSOC_RFSOC_PL_GPIO5 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
AN18 MPSOC_RFSOC_PL_GPIO6 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
F15 MPSOC_RFSOC_PL_GPIO7 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
F14 MPSOC_RFSOC_PL_GPIO8 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
G14 MPSOC_RFSOC_PL_GPIO9 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PL
J30 MPSOC_RFSOC_PS_GPIO1 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PS
K30 MPSOC_RFSOC_PS_GPIO2 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PS
L29 MPSOC_RFSOC_PS_GPIO3 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PS
L30 MPSOC_RFSOC_PS_GPIO4 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PS
M29 MPSOC_RFSOC_PS_GPIO5 GPIO - Zynq UltraScale+ MPSoC <--
>Zynq UltraScale+ RFSoC PS
D14 MPSOC_MSP_GPIO1 GPIO - Zynq UltraScale+ MPSoC <-->SC
D13 MPSOC_MSP_GPIO2 GPIO - Zynq UltraScale+ MPSoC <-->SC
AH19 SOC_SCL I2C Bus
AJ18 SOC_SDA I2C Bus
M37 MAC_MP_T0_N Inter-SoC 100G MAC
M36 MAC_MP_T0_P Inter-SoC 100G MAC
L35 MAC_MP_T1_N Inter-SoC 100G MAC
L34 MAC_MP_T1_P Inter-SoC 100G MAC
Chapter 2: Pin Mapping
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