Acqiris SA230E User manual

Acqiris SA230E
Acquisition Module
1 channel, 14-bit, 4 GS/s,
DC up to 2 GHz bandwidth
User's Manual

2 Acqiris SA230E User's Manual
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© Acqiris, 2018 - 2019
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and retrieval or translation into a foreign language) without prior agreement and written consent from
Acqiris SA as governed by international copyright laws.
Version
August 2019
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SA230E Acquisition Module User's Manual
Acqiris SA230E User's Manual 3
SA230E Acquisition Module User's Manual
This help document is intended to provide in-depth information and reference material specific to your
ADC module.
For information about installation and about getting started with your ADC module, please refer to the
Startup Guide which can be downloaded from https://extranet.acqiris.com/ or which is installed with
your software.
Content
SA230E Acquisition Module User's Manual 3
Content 3
Introduction 5
New generation of Signal Acquisition Cards 5
Product description 5
Product configurable options 7
Main Module Features 8
1.1 SA230E front panel features 9
1.2 Channel input specifications 10
1.3 Sampling and data acquisition 12
1.4 Trigger 13
1.5 Calibration 15
Signal Acquisition Modes and Real-Time Processing 17
2.1 Digitizer acquisition mode 18
2.2 Real-time averaging mode (AVG option) 22
2.3 Real-time peak-listing mode (PKL option) 28
Readout Modes 37
3.1 Standard readout modes 37
3.2 Simultaneous acquisition and readout (CST option) 38
3.3 Averager with simultaneous acquisition and readout (AVG & CST) 47
Other Signal Processing Features 50
4.1 Baseline stabilization and digital offset 51
4.2 Sampling rate reduction (binary decimation) 54
4.3 Data inversion 55
4.4 Equalization 56
Control and Synchronization 59
5.1 External reference 60
5.2 Trigger modes and time-stamps 60

Content
4 Acqiris SA230E User's Manual
5.3 Trigger output 65
5.4 Multi-purpose inputs and outputs 67
Programming Information 69
6.1 Overview of the AqMD3 Driver 69
6.2 Programming with the IVI-C Driver in various development environments 70
6.3 Migrating from MD2 2.x to MD3 3.x 72
6.4 Initial configuration 73
6.5 Apply setup 74
How To ... ? 75
7.1 How to discover the PXI Instrument? 76
7.2 How to calibrate the module? 77
7.3 How to access repeated capabilities? 80
7.4 How to generate a software trigger? 81
7.5 How to enable or bypass the bandwidth limiter? 82
7.6 How to set the external trigger? 83
7.7 How to perform binary decimation? (depending on firmware) 84
7.8 How to load a new firmware? 85
7.9 How to configure of the baseline stabilization? 86
Software utilities 89
8.1 ADC card Verification Utility (AqMD3Verify) 89
FAQ 91
9.1 Q. What is coherent sampling? 91
9.2 Q. How to manage the internal temperature? 91
9.3 Q. What happens if the host processor goes in hibernation mode? 92
General information 93
10.1 Safety notes 93
10.2 Cleaning precautions 95
10.3 Product markings 95
10.4 Electrical &environmental specifications 96
10.5 Related documentation 96

Introduction
Acqiris SA230E User's Manual 5
Introduction
New generation of Signal Acquisition Cards
The Acqiris SA2 is a high-performance 14-bit ADC card platform, performing signal acquisitions from
1GS/s up to 10GS/s, with excellent signal fidelity across a wide bandwidth. This new card and
module generation with advanced real-time processing capabilities is designed for embedded OEM
applications in a variety of challenging measurements, imaging and processing systems.
Product description
The SA230E ADC module is the 4 GS/s and single channel version of the SA2 product family. This
unique DC-coupled 14-bit digitizer captures waveforms from DC up to 2 GHz.

Product description
6 Acqiris SA230E User's Manual
Featuring very long acquisition memory up to 8 GB, the SA230E includes a powerful Xilinx Kintex
UltraScale FPGA offering real-time signal processing capability such as waveform averaging or peak
listing.
All the ADC cards and modules from the SA2 family implement a proprietary low noise front-end. With
undisputed spurious-free dynamic range (SFDR) and signal noise ratio (SNR) performances in high
frequencies, it is ideal for OEM applications requiring digitizer sampling at wide bandwidth and very
high dynamic range, especially at 500 mV full scale range (FSR). Moreover, optimized response
allows few hundred picoseconds pulse analysis. Overall performance enables final products to
measure deeper, faster and more precisely.
Figure 1.1 - SA230E block diagram
Most of the technical specifications concerning your particular ADC card are covered in this manual,
however for the complete specifications please refer to the SA230E datasheet.

Product configurable options
Acqiris SA230E User's Manual 7
Product configurable options
The SA230E comes with several options:
Additional memory:
4 GB (MEA option)
8 GB (MEB option)
ADC Card modes:
Digitizer mode (DGT)
Real-time averaging (AVG option)
Real-time peak listing (PKL option)
Optional features:
Simultaneous acquisition and readout - Streaming records (CST option)
Custom firmware capability (CFW option)
Other internal references:
Module version (-BXA)
I/O ports for SA230E: 3 I/Os,1 trigger output (EXC)

Main Module Features
8 Acqiris SA230E User's Manual
Chapter 1
Main Module Features
1.1 SA230E front panel features 9
1.2 Channel input specifications 10
1.3 Sampling and data acquisition 12
1.4 Trigger 13
1.5 Calibration 15

1.1 SA230E front panel features
Acqiris SA230E User's Manual 9
1.1 SA230E front panel features
Front panel connectors
Connector Type Description
TRG IN MMCX
female External trigger input, 50 Ω DC terminated, ± 5 V range.
IN 1, 2
SMA
female
Analog signal inputs, DC-coupled and 50 Ω terminated. The input full scale ranges
are selectable:
Voltage 500 mV FSR 2.5 V FSR
Recommended maximum oper-
ating voltage ± 600 mVpk ±3 Vpk
TRGOUT1
MMCX Trigger Out signal (programmable).
50Ω source, LVCMOS 3.3V
I/O 1, 2, 3
MMCX
User configurable digital Input / Output signal.
DC coupling, LVCMOS 3.3 V.
Output: 50Ω source, Input: +5V max.
REF IN MMCX External reference clock input, AC coupled and 50 Ω terminated.
It can accept a 10MHz or a 100 MHz signal from -3 to +3 dBm.
Table 1.1 - List of SA230E front-panel IOs.
The ADC module can usually work with signal present at the external reference input (REF IN).
However, to ensure the best performance, or if the calibration is found to be unreliable, it is
recommended to remove such signals when working with internal clock.
1The trigger out connector depends on the product version.

1.2 Channel input specifications
10 Acqiris SA230E User's Manual
1.2 Channel input specifications
This section provides information and specifications regarding the input characteristics of the ADC
module.
The SA230E provides one 14-bit DC-coupled channel at the sampling rate of 4 GS/s.
Channel input
The SA230E has the following front end capabilities:
Coupling / Impedance Full Scale Ranges (FSR) Maximum operating voltage Input voltage offset
DC / 50 Ω
500 mV ± 600 mVpk ± FSR/2
2.5 V ± 3 Vpk ± FSR/2
Table 1.2 - Channel input specifications.
It is also possible to optimize the calibration for a specified target voltage. For details, see
Calibration optimized for a target voltage (page 77).
Impedance & coupling
The input channel termination is 50Ω. The input coupling is DC.
Input protection
The input amplifiers are designed to accept signals within the absolute maximum operating voltages
shown in the table.
Bandwidth and rise time
The bandwidth specification indicates the frequency at which an input signal will be attenuated by 3dB
(approximately 30% loss of amplitude).
The bandwidth of the SA230E is from DC to 2 GHz (typical).
The bandwidth also has an impact on the minimum rise and fall times that can be passed through the
front-end electronics. A pulse with a very sharp edge will be observed to have a minimum rise time
Tmin determined by the front-end electronics. In general a pulse with a given 10-90% rise time T10-
90real will be observed with a lower value given by:
T10-902=T10-90real2+Tmin2
where Tmin(ns) ≈ 0.35/BW(GHz).

1.2 Channel input specifications
Acqiris SA230E User's Manual 11
Bandwidth limitation
SA230E ADC modules offer a bandwidth limiter capability at 20 MHz, 200 MHz or 700 MHz.
Also see Programing section > How to enable or bypass the bandwidth limiter? (page 82).
Vertical resolution
The SA230E uses 14-bit ADCs giving 16384 levels at each input full scale range i.e. 16384 level of
~152 μV average width when using the 2.5 V FSR, or 30 μV using the 500 mV FSR. See Acquired
data format (page 20) for more details.

1.3 Sampling and data acquisition
12 Acqiris SA230E User's Manual
1.3 Sampling and data acquisition
The ADC module acquires waveforms in association with triggers. Each waveform is made of a series
of measured voltage values (sample points) coming from the ADC at a uniform sampling rate.
Sampling rate
The SA230E acquisition module contains an analog-to-digital conversion (ADC) system that can
sample waveforms, in a real time sampling mode, at the maximum rates shown in the table below.
Model Max. Sampling
Rate
Available
Channels Resolution Acquisition Modes
SA230E 4 GS/s 1 14 bits
Single or multi-record
(up to 131'072 )
or continuoussteaming with CST option.
Table 1.3 - Acquisition sampling rate and resolution per channel.
Data acquisition modes and functions
The SA230E ADC module supports several acquisition modes and optional functions for real-time
signal processing in FPGA. You can refer to the corresponding section for details.
ADC module modes:
Digitizer acquisition mode (page 18)
Real-time averaging mode (AVG option) (page 22)
Available signal processing features:
Sampling rate reduction (binary decimation) (page 54)
Data inversion (page 55)
Equalization (page 56)
Read out modes:
One shot with single waveform
One shot with multiple waveforms
Simultaneous acquisition and readout (CST option) (page 38)

1.4 Trigger
Acqiris SA230E User's Manual 13
1.4 Trigger
The trigger settings applied to the ADC module are used to determine at which time the device will
start recording data. The various trigger settings are outlined below.
Trigger source
The trigger source can be:
the signal applied to an input channel (internal triggering)
an external signal applied to the TRG IN front panel input connector (external triggering)
a self-trigger (See Self-Trigger (page 63) for this specific mode)
a software trigger (See How to generate a software trigger? (page 81)).
The different trigger modes are detailed in section Trigger modes and time-stamps (page 60)
Trigger impedance & coupling
The SA230E has a fixed 50 Ω termination impedance with DC coupling.
Trigger input bandwidths
The bandwidth depends on the trigger source.
Channel trigger
The -3 dB bandwidth of the comparator of the channel triggers is from DC to 2 GHz.
External trigger
The external trigger input has a bandwidth from DC to 2.5 GHz.
Refer to section How to set the external trigger? (page 83) for additional information.
Trigger level
The trigger level specifies the voltage at which the selected trigger source will produce a valid trigger.
All trigger circuits have sensitivity levels that must be exceeded in order for reliable trigger to occur.
Both the external trigger input and channel triggers have a hysteresis of 1% of FSR (Full Scale
Range).
On the external trigger, the Full Scale Range FSR is ±5 V, therefore the ADC module will trigger on
signals with a peak-to-peak amplitude > 0.5 V.
When using the channel triggers, the trigger level must be set within Offset ± FSR .

1.4 Trigger
14 Acqiris SA230E User's Manual
Edge trigger slope
The trigger slope defines which one of the two possible transitions will be used to initiate the trigger
when it passes through the specified trigger level. Positive slope indicates that the signal is
transitioning from a lower voltage to a higher voltage. Negative slope indicates the signal is
transitioning from a higher voltage to a lower voltage.
Trigger delays
For more details about triggers modes, post/pre-trigger delays and time-stamps, see Trigger modes
and time-stamps (page 60).

1.5 Calibration
Acqiris SA230E User's Manual 15
1.5 Calibration
The SA230E is factory calibrated and shipped with a calibration certificate.
The internal calibration refers to the adjustment of ADC module internal parameters, corresponding to
user selected parameters and required before starting acquisition.
Internal calibration
The internal calibration (or self-calibration) measures and adjusts the internal timing, gain and offset
parameters between the ADCs and against a precise reference.
The ADC module includes a high precision voltage source and a 16-bit DAC, used to perform the input
voltage and offset calibration.
The supplied software drivers include self-calibration function which can be executed upon user
request. The ADC modules are never self-calibrated in an automatic way, (i.e. as a consequence of
another operation). This ensures programmers have full control of all calibration operations performed
through software in order to maintain proper event synchronization within automated test applications.
For accurate time and voltage measurements it is recommended to perform a self-calibration once
the module has attained a stable operating temperature (usually reached after 20 minutes of ADC
module operation after power on).
A full internal calibration of a ADC module can be time consuming because of the many possible
configuration states. Therefore, the self-calibration is performed only for the current configuration
state, and is mandatory before making the first acquisition with given settings. Indeed the AqMD3
driver prevents an acquisition from being performed unless a self-calibration has first been completed.
Note that some configuration changes do not require a new self-calibration. To avoid unnecessary
self-calibrations, the IAqMD3Calibration.IsRequired IVI.NETproperty or the AQMD3_ATTR_
CALIBRATION_IS_REQUIRED IVI-C attribute should be queried.
ADC module can usually work with signals present at the channel input, or trigger input. However,
to ensure the best performance, or if the calibration is found to be unreliable (as shown by a
calibration failure status), it is recommended to remove such signals.
Similarly, when working with internal clock, it is recommended to remove external reference input
during calibration to avoid parasitic effects.
It is not recommended to perform multiple successive calibrations. If a recurrent calibration failure
occurs, in case of specific application, please contact support for advice.
Smart-calibration
The smart calibration implemented in MD3 drivers allows to save time by automatically keeping in
memory the calibration information from any self-calibration performed since the beginning of the
session. When the acquisition parameters are changed, no re-calibration of the module is necessary if

1.5 Calibration
16 Acqiris SA230E User's Manual
a self-calibration has already been performed with the same acquisition conditions (i.e. the same set of
parameters), unless the clock mode parameters are changed.
Indeed, any change in the clock mode parameters (i.e. External clock frequency or Reference
mode parameters), induces a restart of the clocks which requires a new self-calibration.
For details, see Parameter change requiring a new self calibration (page 78).
Calibration optimized for a target voltage
It is possible to optimize the calibration for a specified target voltage. In this case, the self-calibration
will minimize the noise level at the channel input value equal to this specified target voltage. For
details, see Calibration optimized for a target voltage (page 77).
Factory calibration
Factory calibration is the process of measuring the actual performance of a device-under-test (DUT)
using laboratory instruments that have significantly better performance than the DUT. Laboratory
instrument performance must be traceable to the International System (SI) Units via a national
metrology institute (NIST, NPL, NRC, PTB, CENAM, INMETRO, BIPM, etc.)
The measured performance is then compared to published datasheet specifications. For each factory
calibration, Acqiris tests the performance corresponding to all datasheet specifications, for every
installed option. If needed, the DUT is adjusted and re-qualified ; ensuring it is in line with full
specifications.
Our ADC modules are calibrated at factory during the production phase. There is no need to
systematically calibrate each year.
Firstly, the modules include a self-calibration function providing a good degree of confidence that your
module is operating within its specifications on a day-to-day basis, and triggering an error message if
out of calibration relative to the internal calibration signal.
Secondly, our modules are warranted to stay within specification over the standard 3-year warranty.
They usually stay within specification much longer and we rarely have to effectively recalibrate the
modules.
Lastly, a onetime calibration can be ordered in case customer detects a deviation in the measure of its
final product that appears to be caused by the ADC module. The onetime calibration consists in
processing the module through production test to determine if it is still within specification:
If yes, the ADC module is returned with the certificate of calibration which certifies it is within
specification.
If not, the required calibration is performed, and another production test is done to provide the
certificate of calibration.
If repair is required, and the module is out of warranty, a repair quote will be provided.
For more information, or to request for a calibration, please contact technical support
[e-mail].

Signal Acquisition Modes and Real-Time Processing
Acqiris SA230E User's Manual 17
Chapter 2
Signal Acquisition Modes and Real-Time
Processing
Thanks to the powerful Xilinx Kintex Ultrascale FPGA, the SA230E enables real-time signal pre-
processing on the sampled data e.g. data compression or noise reduction. This allows to save
analysis time and make the user application running faster. Acqiris proposes various firmware and
real-time processing features in the FPGA, so on-board processing can be optimized for each
application and eventually for each of your system.
This section details the acquisition modes.
2.1 Digitizer acquisition mode 18
2.2 Real-time averaging mode (AVG option) 22
2.3 Real-time peak-listing mode (PKL option) 28
The modes available with your product depends on the firmware options ordered with your products.
To check which options and mode are present on your ADC module you can use the MD3 Software
Front Panel from the: Windows Start Menu > Acqiris > MD3 > Acqiris MD3 SFP. Then use the
menu Help > About. The field System Options gives the option list.
Easy mode switch
A simple change of acquisition mode allows to automatically switch, for instance, from the digitizer
to the average mode. The corresponding firmware switches automatically.

2.1 Digitizer acquisition mode
18 Acqiris SA230E User's Manual
2.1 Digitizer acquisition mode
The digitizer mode (normal mode) allows standard data acquisition, including: ADC module
initialization, setting of the acquisition, management of channel triggering for best synchronization,
storing data in the internal memory and/or transferring them to the host computer.
The digitizer mode is the acquisition mode by default.
For units ordered without the Digitizer mode (DGToption), a basic digitizer function is still available
with some limitations. For the list of limitation, please refer to section Using basic digitizer function
(without DGT option) (page 21).
Single and multi-record acquisition modes
To maximize sampling rates and utilize memory as efficiently as possible the ADC modules include
both single and multi-record modes. For both of these modes the data of all of the active channels is
acquired synchronously; all of the ADC's are acquiring data at the same time, to within a small fraction
of the maximum sampling rate.
The single record acquisition mode is the normal operation of most ADC module products. In this
mode an acquisition consists of a waveform recorded with a single trigger. The user selects the
sampling rate and record size, and sets the number of records to 1 (default value). For details about the
trigger sources, see Trigger (page 13).
Figure 2.1 - Acquisition sequence using a single record.
The ADC modules also feature a multi-record acquisition mode. This mode allows the capture and
storage of consecutive single waveforms. Multi-record acquisition mode is useful as it can optimize
the ADC module's sampling rate and memory requirements for applications where only portions of the
signal being analyzed are important. The mode is extremely useful in almost all impulse-response type
applications (RADAR, SONAR, LIDAR, Time-of-Flight, Ultrasonics, Medical and Biomedical
Research, etc.).
In multi-record acquisition mode the acquisition memory is divided into a pre-selected number of
records. Waveforms are stored in successive memory records as they arrive. Each waveform requires
its own individual trigger.

2.1 Digitizer acquisition mode
Acqiris SA230E User's Manual 19
Figure 2.2 - Acquisition sequence using a multi-records. It is possible to miss a trigger at high trigger rate, as
illustrated with trigger 3.
The multi-record acquisition mode enables successive events, occurring within a very short time,
to be captured and stored without loss. A very fast trigger rearm time is a crucial feature for multi-
record acquisitions. Thanks to fast trigger rearm, the SA230E achieves very low “dead time” between
the records of a multi-record acquisition. The “dead time” is the period after the end of an event when
the module cannot accept a new trigger event. The re-arm time is provided in the SA230E's SA230E
datasheet.
Program examples for Single record or multi-records acquisitions are available:
For IVI-C C1:\Program Files\IVI Foundation\IVI\Drivers\AqMD3\Examples\IVI-C
For IVI.NET C:\Program Files\IVI Foundation\IVI\Drivers\AqMD3\Examples\IVI.NET
Acquisition memory
Data from the ADC is stored in on-board acquisition memory. The amount of memory in use for
acquisition can be programmed and is selectable from 1 point to the full amount of acquisition memory
available.
Model Memory option
ordered
Acquisition memory
ordered Max samples/channel
SA230E -MEA (default) 4 GB 2 GSamples
-MEB (optional) 8 GB 4 GSamples
Table 2.1 - Maximum number of samples which can be recorded per channel, depending on ordered memory
option.
For technical reasons, a certain acquisition memory overhead is required for each waveform, reducing
the available memory by a small amount.
1Or the alternative drive letter where the Acqiris MD3 Software has been installed on your machine.

2.1 Digitizer acquisition mode
20 Acqiris SA230E User's Manual
The effective maximum memory available for acquisition depends on several parameters, such as
the acquisition mode (single / multi-record / streaming), sampling rate, record size, number of
records, trigger delay, etc.... This maximum is determined by the driver for each specific
configuration. The AQMD3_ATTR_MAX_SAMPLES_PER_CHANNEL attribute in IVI-C or
IAqMD3Acquisition.MaxSamplesPerChannel property in IVI.NET can be used to retrieve
the maximum number of samples per channel that can be acquired for a specific configuration.
When using the Soft Front Panel, the Max Samples per channel parameter is given on the
Acquisition panel.
Acquisition time (Timebase range)
The timebase range defines the time period over which data is being acquired.
For example, the SA230E has a standard acquisition memory of and a sampling rate of 4 GS/s.
Therefore, at the maximum sampling rate, the ADC module can record a signal over a time window of
up to 500 ms.
Model Memory option
ordered
Acquisition
memory Max sampling rate
Max recording time
window at higher
sampling rate
SA230P -MEA (default) 4 GB 4 GS/s 500 ms
-MEB (optional) 8 GB 1 s
Table 2.2 - Maximum recorded time at maximum sampling rate, depending on ordered memory option.
Maximum acquisition time
There is a limit on the acquisition time / acquisition length in digitizer mode depending on the record
size, post trigger delay and binary decimation factor. Above this limit, the driver returns a post-trigger
overflow.
Acquired data format
The raw 14-bit data is subjected to post-calibration processing, which compensates for gain and offset
errors in the internal ADCs, The result of this post-processing is then stored and read-out as a 16-bit
value. For this reason the returned data will not always be divisible by 4 as may be expected, neither
equally spaced.
Signed left-aligned 16-bit ADC code
The signed, raw ADC code is shifted to the left to align to 16 bits. The result is then converted, with the
sign, to the final format (16, 32 or 64 bits).
For the 14-bit SA230E, signed left-aligned 16-bit ADC code means that the signed raw ADC code is
shifted to the left by 2 bits, and coded in 2’s complement to the final number of bits (16, 32 or 64) as
illustrated below.