Acqiris U5303A User manual

Acqiris U5303A
Acquisition Card
2 channels, 12-bit, 500 MS/s to 4 GS/s,
DC up to 2 GHz bandwidth, with real-time processing
User's Manual

2 U5303A User's Manual
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© Acqiris, 2017 - 2019
No part of this manual may be reproduced in any form or by any means (including electronic storage
and retrieval or translation into a foreign language) without prior agreement and written consent from
Acqiris SA as governed by international copyright laws.
Version
July 2019
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U5303A Acquisition Card User's Manual
U5303A User's Manual 3
U5303A Acquisition Card User's Manual
This help document is intended to provide in-depth information and reference material specific to your
ADC Card.
For information about installation and about getting started with your ADC Card, please refer to the
Startup Guide which can be downloaded from https://extranet.acqiris.com/ or which is installed with
your software.
Content
U5303A Acquisition Card User's Manual 3
Content 3
Introduction 5
Overview 5
Block diagram 6
Main ADC Card Features 7
1.1 U5303A front panel features 8
1.2 Channel input specifications 9
1.3 Sampling and Data Acquisition 11
1.4 Trigger 12
1.5 Calibration 14
Real-Time Processing Options 16
2.1 Acquisition modes and specific features 16
2.2 Easy firmware switch 16
2.3 Digitizer firmware (DGT option) 17
2.4 Real-time averaging (AVG option) 20
2.5 Peak Detection (PKD) 33
Readout modes 39
3.1 Standard readout modes 39
3.2 Continuous Simultaneous acquisition and Readout (CSR) 40
3.3 Triggered simultaneous acquisition and readout (TSR) 49
3.4 Averager with triggered simultaneous acquisition and readout (AVG/TSR/INT option) 53
Other Signal Processing Features 57
4.1 Sampling rate reduction (binary decimation) 58
4.2 Custom firmware capability (FPGA Development Kit) 59
Application Options 60
5.1 Swept Source OCT(SS1/SS2/SS3) 60
Control and Synchronization 61

Content
4 U5303A User's Manual
6.1 External clock and reference 62
6.2 Trigger modes and time-stamps 63
6.3 Trigger output 67
6.4 Multi-purpose inputs and outputs 70
Programming Information 72
7.1 Overview of the AqMD3 Driver 72
7.2 Programming with the IVI-C Driver in various development environments 73
7.3 Migrating from MD2 2.x to MD3 3.x 75
7.4 Initial configuration 76
7.5 Apply setup 77
How To ... ? 78
8.1 How to discover the PXI Instrument? 79
8.2 How to calibrate the card? 80
8.3 How to configure and read data on two channels? 84
8.4 How to access repeated capabilities? 85
8.5 How to generate a software trigger? 86
8.6 How to perform time-interleaving acquisitions? 87
8.7 How to enable or bypass the bandwidth limiter? 88
8.8 How to set the external trigger? 89
8.9 How to perform binary decimation? (depending on firmware) 90
8.10 How to perform partial readout? 91
8.11 How to load a new firmware? 94
8.12 How to switch from normal mode acquisition (Multi-record) to averager mode or peak
detection mode? 95
Software utilities 96
9.1 ADC card Verification Utility (AqMD3Verify) 96
Accessories 98
10.1 U5300A-118 SMA Input Over-voltage Protection 98
FAQ 100
11.1 Q. What is coherent sampling? 100
11.2 Q. How to manage the internal temperature? 100
11.3 Q. What are the differences between the various data streaming firmware options
supported by high-speed ADC cards ? 101
11.4 Q. What happens if the host processor goes in hibernation mode? 102
General information 103
12.1 Safety notes 103
12.2 Cleaning precautions 105
12.3 Product markings 105
12.4 Electrical &environmental specifications 106
12.5 Related documentation 106
12.6 Full product family 107

Introduction
U5303A User's Manual 5
Introduction
Overview
The Acqiris U5303A is a fast 12-bit PCIe signal acquisition card with programmable on-board
processing, making it ideal for biotechnology, semiconductors, and physics. The U5303A is
particularly suited for OEM applications with its fast PCI Express 2.0 eight lanes connection.
The U5303A occupies a single full-length PCIe slot of the host PC. It features sample rates of
500MS/s, 1GS/s, 1.6GS/s or 2GS/s per channel (depending on the option), and up to 4GS/s in
interleaved mode, along with an analog bandwidth of up to 2 GHz and DDR3 acquisition memory
options up to 4 GB. The U5303A includes a Xilinx Virtex-6 FPGA allowing implementation of custom
real-time processing algorithms.
At the heart of the U5303A is a data processing unit (DPU) based on the Xilinx Virtex-6 FPGA. This
DPU is responsible for controlling the module functionality, data flow and real-time signal processing.
This powerful feature allows data reduction and storage to be carried out at the ADC card level,
minimizing transfer volumes and speeding-up analysis.

Block diagram
6 U5303A User's Manual
Block diagram
Figure 1.1 - U5303A block diagram
Most of the technical specifications concerning your particular ADC card are covered in this manual,
however for the complete specifications please refer to the U5303A datasheet.

Main ADC Card Features
U5303A User's Manual 7
Chapter 1
Main ADC Card Features
1.1 U5303A front panel features 8
1.2 Channel input specifications 9
1.3 Sampling and Data Acquisition 11
1.4 Trigger 12
1.5 Calibration 14

1.1 U5303A front panel features
8 U5303A User's Manual
1.1 U5303A front panel features
Front panel connectors
Connector Type Description
TRG IN MMCX female External trigger input, 50 Ω DC terminated, ±5 V range.
IN 1, 2 SMA female
Analog signal inputs, DC-coupled and 50 Ω terminated.
The input Full Scale Ranges are selectable:
Voltage 1 V
FSR
2 V
FSR
Recommended maximum
operating voltage ±3 V ±4.3 V
Clamp level ±3.6 V ±6.3 V
Absolute maximum DC voltage
rating ±4.6 V ±5 V
JTAG Micro USB Providesconnection to the DPU for specific reprogramming.
TRGOUT MMCX female Trigger Out signal. User selectable from several functions.
I/O 1, 2, 3 MMCX female User configurable Input / Output signal. 3.3 V CMOS and
TTLcompatible.
CLK IN MMCX female
External clock input. AC coupled and 50 Ω terminated, signal
level: +5 to +15 dBm. Please refer to U5303A datasheet for
details.
REF IN MMCX female External reference clock input, AC coupled and 50 Ω ter-
minated. It can accept a 100MHzsignalfrom -3 to +3 dBm.
Table 1.1 - List of U5303A front-panel IOs.
The ADC card can usually work with signals present at the external reference and clock inputs
(REF IN and CLK IN). However, to ensure the best performance, or if the calibration is found to be
unreliable, it is recommended to remove such signals when working with internal clock.

1.2 Channel input specifications
U5303A User's Manual 9
1.2 Channel input specifications
This section provides information and specifications regarding the input characteristics of the ADC
card.
The U5303A provides two 12-bit DC-coupled channels at the sampling rate of:
- 500 MS/s (-SR0)
- 1 GS/s (-SR1)
- 1.6 GS/s (-SR2)
- 2 GS/s (-SR3).
For U5303A with INT option, the two channels may be combined to form an interleaved channel at:
- 1 GS/s (-SR0)
- 2 GS/s (-SR1)
- 3.2 GS/s (-SR2)
- 4 GS/s (-SR3).
Channel input
The U5303A has the following front end capabilities:
Coupling /
Impedance
Full Scale
Ranges
(FSR)
Recommended maximum
operating voltage
Clamp
level
Absolute maximum
DC voltage rating Offset Adjustment
DC / 50 Ω
1 V ±3 V ±3.6 V ±4.6 V ±2 xFSR
2 V ±4.3 V ±6.3 V ±5 V ±2 xFSR
Table 1.2 - Front-end specifications of the channel input(s).
It is also possible to optimize the calibration for a specified target voltage. For details, see
Calibration optimized for a target voltage (page 80).
Impedance & coupling
The input channel termination is 50Ω. The input coupling is DC.
Input protection
The input amplifiers are designed to accept signals below the level shown in the table.

1.2 Channel input specifications
10 U5303A User's Manual
Front-end mezzanine
The front-end electronics are all mounted on a removable mezzanine card. In the event of accidental
damage or as components fatigue over time (e.g. relays in high duty cycle automated testing
applications), the mezzanine card allows for fast and efficient replacement.
Bandwidth and rise time
The bandwidth specification indicates the frequency at which an input signal will be attenuated by 3dB
(approximately 30% loss of amplitude).
U5303A ADC cards with -F10 option offer a 650 MHz bandwidth limiter -also see How to enable or
bypass the bandwidth limiter? (page 88).
Options Input Frequency Range BW Limiter selection
1 V FSR 2 V FSR
-F05
-SR0 —DC to 400 MHz(typical) No BW limiter
-INT
-SR1/-SR2/-SR3 —DC to 650 MHz (typical) 650 MHz
-INT
-F10 -SR1/-SR2/-SR3
— DC to 1.9 GHz(typical) DC to 2.0 GHz (typical)
650 MHz
-INT DC to 1.3 GHz(typical)
Table 1.3 - Channel input bandwidth vs.ordered options.
The bandwidth also affects the minimum rise and fall times that can be passed through the front-end
electronics. A pulse with a very sharp edge will be observed to have a minimum rise time Tmin
determined by the front-end electronics. In general a pulse with a given 10-90% rise time T10-90real will
be observed with a lower value given by:
T10-902=T10-90real2+Tmin2
where Tmin(ns)≈0.35/BW(GHz).
Vertical resolution
The U5303A ADC Card uses a 12-bit ADC giving 4096 levels of ~0.25 mV average width when using
the 1 V FSR.