Acqiris U5303A User manual

Acqiris U5303A
Acquisition Card
2 channels, 12-bit, 500 MS/s to 4 GS/s,
DC up to 2 GHz bandwidth, with real-time processing
User's Manual

2 U5303A User's Manual
Copyright Statement
© Acqiris, 2017 - 2019
No part of this manual may be reproduced in any form or by any means (including electronic storage
and retrieval or translation into a foreign language) without prior agreement and written consent from
Acqiris SA as governed by international copyright laws.
Version
July 2019
Contact us
Acqiris Americas
[e-mail]
Acqiris Europe
[e-mail]
Acqiris Asia-Pacific
[e-mail]
Acqiris Japan
[e-mail]
Worldwide contact for support
[e-mail]
Acqiris SA
Chemin des Aulx, 12
1228 Plan-Les-Ouates
Switzerland
www.acqiris.com

U5303A Acquisition Card User's Manual
U5303A User's Manual 3
U5303A Acquisition Card User's Manual
This help document is intended to provide in-depth information and reference material specific to your
ADC Card.
For information about installation and about getting started with your ADC Card, please refer to the
Startup Guide which can be downloaded from https://extranet.acqiris.com/ or which is installed with
your software.
Content
U5303A Acquisition Card User's Manual 3
Content 3
Introduction 5
Overview 5
Block diagram 6
Main ADC Card Features 7
1.1 U5303A front panel features 8
1.2 Channel input specifications 9
1.3 Sampling and Data Acquisition 11
1.4 Trigger 12
1.5 Calibration 14
Real-Time Processing Options 16
2.1 Acquisition modes and specific features 16
2.2 Easy firmware switch 16
2.3 Digitizer firmware (DGT option) 17
2.4 Real-time averaging (AVG option) 20
2.5 Peak Detection (PKD) 33
Readout modes 39
3.1 Standard readout modes 39
3.2 Continuous Simultaneous acquisition and Readout (CSR) 40
3.3 Triggered simultaneous acquisition and readout (TSR) 49
3.4 Averager with triggered simultaneous acquisition and readout (AVG/TSR/INT option) 53
Other Signal Processing Features 57
4.1 Sampling rate reduction (binary decimation) 58
4.2 Custom firmware capability (FPGA Development Kit) 59
Application Options 60
5.1 Swept Source OCT(SS1/SS2/SS3) 60
Control and Synchronization 61

Content
4 U5303A User's Manual
6.1 External clock and reference 62
6.2 Trigger modes and time-stamps 63
6.3 Trigger output 67
6.4 Multi-purpose inputs and outputs 70
Programming Information 72
7.1 Overview of the AqMD3 Driver 72
7.2 Programming with the IVI-C Driver in various development environments 73
7.3 Migrating from MD2 2.x to MD3 3.x 75
7.4 Initial configuration 76
7.5 Apply setup 77
How To ... ? 78
8.1 How to discover the PXI Instrument? 79
8.2 How to calibrate the card? 80
8.3 How to configure and read data on two channels? 84
8.4 How to access repeated capabilities? 85
8.5 How to generate a software trigger? 86
8.6 How to perform time-interleaving acquisitions? 87
8.7 How to enable or bypass the bandwidth limiter? 88
8.8 How to set the external trigger? 89
8.9 How to perform binary decimation? (depending on firmware) 90
8.10 How to perform partial readout? 91
8.11 How to load a new firmware? 94
8.12 How to switch from normal mode acquisition (Multi-record) to averager mode or peak
detection mode? 95
Software utilities 96
9.1 ADC card Verification Utility (AqMD3Verify) 96
Accessories 98
10.1 U5300A-118 SMA Input Over-voltage Protection 98
FAQ 100
11.1 Q. What is coherent sampling? 100
11.2 Q. How to manage the internal temperature? 100
11.3 Q. What are the differences between the various data streaming firmware options
supported by high-speed ADC cards ? 101
11.4 Q. What happens if the host processor goes in hibernation mode? 102
General information 103
12.1 Safety notes 103
12.2 Cleaning precautions 105
12.3 Product markings 105
12.4 Electrical &environmental specifications 106
12.5 Related documentation 106
12.6 Full product family 107

Introduction
U5303A User's Manual 5
Introduction
Overview
The Acqiris U5303A is a fast 12-bit PCIe signal acquisition card with programmable on-board
processing, making it ideal for biotechnology, semiconductors, and physics. The U5303A is
particularly suited for OEM applications with its fast PCI Express 2.0 eight lanes connection.
The U5303A occupies a single full-length PCIe slot of the host PC. It features sample rates of
500MS/s, 1GS/s, 1.6GS/s or 2GS/s per channel (depending on the option), and up to 4GS/s in
interleaved mode, along with an analog bandwidth of up to 2 GHz and DDR3 acquisition memory
options up to 4 GB. The U5303A includes a Xilinx Virtex-6 FPGA allowing implementation of custom
real-time processing algorithms.
At the heart of the U5303A is a data processing unit (DPU) based on the Xilinx Virtex-6 FPGA. This
DPU is responsible for controlling the module functionality, data flow and real-time signal processing.
This powerful feature allows data reduction and storage to be carried out at the ADC card level,
minimizing transfer volumes and speeding-up analysis.

Block diagram
6 U5303A User's Manual
Block diagram
Figure 1.1 - U5303A block diagram
Most of the technical specifications concerning your particular ADC card are covered in this manual,
however for the complete specifications please refer to the U5303A datasheet.

Main ADC Card Features
U5303A User's Manual 7
Chapter 1
Main ADC Card Features
1.1 U5303A front panel features 8
1.2 Channel input specifications 9
1.3 Sampling and Data Acquisition 11
1.4 Trigger 12
1.5 Calibration 14

1.1 U5303A front panel features
8 U5303A User's Manual
1.1 U5303A front panel features
Front panel connectors
Connector Type Description
TRG IN MMCX female External trigger input, 50 Ω DC terminated, ±5 V range.
IN 1, 2 SMA female
Analog signal inputs, DC-coupled and 50 Ω terminated.
The input Full Scale Ranges are selectable:
Voltage 1 V
FSR
2 V
FSR
Recommended maximum
operating voltage ±3 V ±4.3 V
Clamp level ±3.6 V ±6.3 V
Absolute maximum DC voltage
rating ±4.6 V ±5 V
JTAG Micro USB Providesconnection to the DPU for specific reprogramming.
TRGOUT MMCX female Trigger Out signal. User selectable from several functions.
I/O 1, 2, 3 MMCX female User configurable Input / Output signal. 3.3 V CMOS and
TTLcompatible.
CLK IN MMCX female
External clock input. AC coupled and 50 Ω terminated, signal
level: +5 to +15 dBm. Please refer to U5303A datasheet for
details.
REF IN MMCX female External reference clock input, AC coupled and 50 Ω ter-
minated. It can accept a 100MHzsignalfrom -3 to +3 dBm.
Table 1.1 - List of U5303A front-panel IOs.
The ADC card can usually work with signals present at the external reference and clock inputs
(REF IN and CLK IN). However, to ensure the best performance, or if the calibration is found to be
unreliable, it is recommended to remove such signals when working with internal clock.

1.2 Channel input specifications
U5303A User's Manual 9
1.2 Channel input specifications
This section provides information and specifications regarding the input characteristics of the ADC
card.
The U5303A provides two 12-bit DC-coupled channels at the sampling rate of:
- 500 MS/s (-SR0)
- 1 GS/s (-SR1)
- 1.6 GS/s (-SR2)
- 2 GS/s (-SR3).
For U5303A with INT option, the two channels may be combined to form an interleaved channel at:
- 1 GS/s (-SR0)
- 2 GS/s (-SR1)
- 3.2 GS/s (-SR2)
- 4 GS/s (-SR3).
Channel input
The U5303A has the following front end capabilities:
Coupling /
Impedance
Full Scale
Ranges
(FSR)
Recommended maximum
operating voltage
Clamp
level
Absolute maximum
DC voltage rating Offset Adjustment
DC / 50 Ω
1 V ±3 V ±3.6 V ±4.6 V ±2 xFSR
2 V ±4.3 V ±6.3 V ±5 V ±2 xFSR
Table 1.2 - Front-end specifications of the channel input(s).
It is also possible to optimize the calibration for a specified target voltage. For details, see
Calibration optimized for a target voltage (page 80).
Impedance & coupling
The input channel termination is 50Ω. The input coupling is DC.
Input protection
The input amplifiers are designed to accept signals below the level shown in the table.

1.2 Channel input specifications
10 U5303A User's Manual
Front-end mezzanine
The front-end electronics are all mounted on a removable mezzanine card. In the event of accidental
damage or as components fatigue over time (e.g. relays in high duty cycle automated testing
applications), the mezzanine card allows for fast and efficient replacement.
Bandwidth and rise time
The bandwidth specification indicates the frequency at which an input signal will be attenuated by 3dB
(approximately 30% loss of amplitude).
U5303A ADC cards with -F10 option offer a 650 MHz bandwidth limiter -also see How to enable or
bypass the bandwidth limiter? (page 88).
Options Input Frequency Range BW Limiter selection
1 V FSR 2 V FSR
-F05
-SR0 —DC to 400 MHz(typical) No BW limiter
-INT
-SR1/-SR2/-SR3 —DC to 650 MHz (typical) 650 MHz
-INT
-F10 -SR1/-SR2/-SR3
— DC to 1.9 GHz(typical) DC to 2.0 GHz (typical)
650 MHz
-INT DC to 1.3 GHz(typical)
Table 1.3 - Channel input bandwidth vs.ordered options.
The bandwidth also affects the minimum rise and fall times that can be passed through the front-end
electronics. A pulse with a very sharp edge will be observed to have a minimum rise time Tmin
determined by the front-end electronics. In general a pulse with a given 10-90% rise time T10-90real will
be observed with a lower value given by:
T10-902=T10-90real2+Tmin2
where Tmin(ns)≈0.35/BW(GHz).
Vertical resolution
The U5303A ADC Card uses a 12-bit ADC giving 4096 levels of ~0.25 mV average width when using
the 1 V FSR.

1.3 Sampling and Data Acquisition
U5303A User's Manual 11
1.3 Sampling and Data Acquisition
The ADC Card acquires waveforms in association with triggers. Each waveform is made of a series of
measured voltage values (sample points) coming from the ADC at a uniform sampling rate.
Sampling rate
The U5303A Acquisition card contains an analog-to-digital conversion (ADC) system that can sample
waveforms, in a real time sampling mode, at the maximum rates shown in the table below. The
maximum sampling rate shown above is achieved by combining the two channels.
Model Option Max. Sampling
Rate
Available
Channels Resolution Readout Modes
U5303A
-SR0 0.5 GS/s 2
12 bits
Single or multi-record
(up to 131'072 records)
or continuous (depends on firmware
options)
-SR0 and
-INT 1 GS/s 1
-SR1 1 GS/s 2
-SR1 and
-INT 2 GS/s 1
-SR2 1.6 GS/s 2
-SR2 and
-INT 3.2 GS/s 1
-SR3 2 GS/s 2
-SR3 and
-INT 4 GS/s 1
Table 1.4 - Acquisition sampling rate and resolution per channel.
The External Clock can be used to vary the sampling rate of the ADC card, see External clock and
reference (page 62).
Combining channels (Interleaving -INT option)
When ordered with -INT option, the U5303A ADC card supports the capability of combining the
converters (and their memories) from two channels to analyze a single input channel. With this feature
the maximum sampling rate and the maximum amount of acquisition memory are doubled.

1.4 Trigger
12 U5303A User's Manual
1.4 Trigger
The trigger settings applied to the ADC card are used to determine at which time the device will start
recording data. The various trigger settings are outlined below.
Trigger source
The trigger source can be:
the signal applied to an input channel (internal triggering)
an external signal applied to the TRG IN front panel input connector (external triggering)
a software trigger (See How to generate a software trigger? (page 86)).
The different trigger modes are detailed in section Trigger modes and time-stamps (page 63)
Trigger impedance & coupling
The U5303A has a fixed 50 Ω termination impedance with DC coupling.
Trigger input bandwidths
The bandwidth depends on the trigger source.
Channel trigger
The -3 dB bandwidth of the comparator of the channel triggers is from DC to 250 MHz. For input
signals with high frequency components, this means that the signal acquired and displayed doesn’t
correspond exactly to the signal seen from the trigger comparator input. Since, the signal seen on the
trigger comparator can be attenuated, this should be taken into account when selecting channel
triggers and specifying the trigger level.
External trigger
The external trigger input has a bandwidth from DC to 2 GHz.
Refer to section How to set the external trigger? (page 89) for additional information.
Trigger level
The trigger level specifies the voltage at which the selected trigger source will produce a valid trigger.
All trigger circuits have sensitivity levels that must be exceeded in order for reliable trigger to occur.
Both the external trigger input and channel triggers have a hysteresis of 5% of FSR (Full Scale
Range).
On the external trigger, the Full Scale Range FSR is ±5 V, therefore the ADC card will trigger on
signals with a peak-to-peak amplitude > 0.5 V.
When using the channel triggers, the trigger level must be set within Offset ± FSR .

1.4 Trigger
U5303A User's Manual 13
Edge trigger slope
The trigger slope defines which one of the two possible transitions will be used to initiate the trigger
when it passes through the specified trigger level. Positive slope indicates that the signal is
transitioning from a lower voltage to a higher voltage. Negative slope indicates the signal is
transitioning from a higher voltage to a lower voltage.
Trigger precision and resolution
With -SR1 option, the U5303A trigger time interpolator offers a resolution of 7.75 ps (nominal) and a
precision of 20.7 ps RMS (nominal) .
With -SR2/-SR3 options, the trigger resolution is 6.25 ps (nominal) and the precision 15 ps RMS
(nominal) .
The accuracy of absolute trigger time is guaranteed (as specified in the datasheet) down to sample
rates 1/16 of the highest sample rate (1/32 of the highest sample rate with interleaving).
If comparing the initial trigger time T0 measured using the same waveform either used as channel
input trigger or as an external trigger, the T0 position can be slightly different (especially if the
waveform used as trigger has a slow edge).
First, the analog bandwidth can be different for the channel trigger input and the external trigger
input, resulting in a different slope and so a different T0.
Secondly, compared with the channel trigger, the external trigger threshold is not calibrated. The
input channel trigger calibration allows a T0 adjustment both in threshold and in timing, resulting in a
more accurate T0. However, when using the external trigger, the measured T0 is still precise and
theT0 position difference stays stable.
Using a signal with faster edge as external trigger can reduce this effect.
Trigger delays
For more details about triggers modes, post/pre-trigger delays and time-stamps, see Trigger modes
and time-stamps (page 63).

1.5 Calibration
14 U5303A User's Manual
1.5 Calibration
The U5303A is factory calibrated and shipped with a calibration certificate.
The internal calibration refers to the adjustment of ADC card internal parameters, corresponding to
user selected parameters and required before starting acquisition.
Internal calibration
The internal calibration (or self-calibration) measures and adjusts the internal timing, gain and offset
parameters between the ADCs and against a precise reference.
The ADC card includes a high precision voltage source and a 16-bit DAC, used to perform the input
voltage and offset calibration.
The supplied software drivers include self-calibration function which can be executed upon user
request. The ADC cards are never self-calibrated in an automatic way, (i.e. as a consequence of
another operation). This ensures programmers have full control of all calibration operations performed
through software in order to maintain proper event synchronization within automated test applications.
For accurate time and voltage measurements it is recommended to perform a self-calibration once
the module has attained a stable operating temperature (usually reached after 20 minutes of ADC
card operation after power on).
A full internal calibration of a ADC card can be time consuming because of the many possible
configuration states. Therefore, the self-calibration is performed only for the current configuration
state, and is mandatory before making the first acquisition with given settings. Indeed the AqMD3
driver prevents an acquisition from being performed unless a self-calibration has first been completed.
Note that some configuration changes do not require a new self-calibration. To avoid unnecessary
self-calibrations, the IAqMD3Calibration.IsRequired IVI.NETproperty or the AQMD3_ATTR_
CALIBRATION_IS_REQUIRED IVI-C attribute should be queried.
ADC card can usually work with signals present at the channel input, or trigger input. However, to
ensure the best performance, or if the calibration is found to be unreliable (as shown by a calibration
failure status), it is recommended to remove such signals.
Similarly, when working with internal clock, it is recommended to remove external reference and
external clock inputs during calibration to avoid parasitic effects.
It is not recommended to perform multiple successive calibrations. If a recurrent calibration failure
occurs, in case of specific application, please contact support for advice.
Smart-calibration
The smart calibration implemented in MD3 drivers allows to save time by automatically keeping in
memory the calibration information from any self-calibration performed since the beginning of the
session. When the acquisition parameters are changed, no re-calibration of the card is necessary if a

1.5 Calibration
U5303A User's Manual 15
self-calibration has already been performed with the same acquisition conditions (i.e. the same set of
parameters), unless the clock mode parameters are changed.
Indeed, any change in the clock mode parameters (i.e. External clock frequency, Clock source or
Reference mode parameters), induces a restart of the clocks which requires a new self-calibration.
For details, see Parameter change requiring a new self calibration (page 81).
Calibration optimized for a target voltage
It is possible to optimize the calibration for a specified target voltage. In this case, the self-calibration
will minimize the noise level at the channel input value equal to this specified target voltage. For
details, see Calibration optimized for a target voltage (page 80).
Factory calibration
Factory calibration is the process of measuring the actual performance of a device-under-test (DUT)
using laboratory instruments that have significantly better performance than the DUT. Laboratory
instrument performance must be traceable to the International System (SI) Units via a national
metrology institute (NIST, NPL, NRC, PTB, CENAM, INMETRO, BIPM, etc.)
The measured performance is then compared to published datasheet specifications. For each factory
calibration, Acqiris tests the performance corresponding to all datasheet specifications, for every
installed option. If needed, the DUT is adjusted and re-qualified ; ensuring it is in line with full
specifications.
Our ADC cards are calibrated at factory during the production phase. There is no need to
systematically calibrate each year.
Firstly, the cards include a self-calibration function providing a good degree of confidence that your
card is operating within its specifications on a day-to-day basis, and triggering an error message if out
of calibration relative to the internal calibration signal.
Secondly, our cards are warranted to stay within specification over the standard 3-year warranty. They
usually stay within specification much longer and we rarely have to effectively recalibrate the cards.
Lastly, a onetime calibration can be ordered in case customer detects a deviation in the measure of its
final product that appears to be caused by the ADC card. The onetime calibration consists in
processing the card through production test to determine if it is still within specification:
If yes, the ADC card is returned with the certificate of calibration which certifies it is within spe-
cification.
If not, the required calibration is performed, and another production test is done to provide the
certificate of calibration.
If repair is required, and the card is out of warranty, a repair quote will be provided.
For more information, or to request for a calibration, please contact technical support
[e-mail].

Real-Time Processing Options
16 U5303A User's Manual
Chapter 2
Real-Time Processing Options
The U5303A ADC Card provides several optional modes. This section describes each acquisition
mode and associated real-time signal processing.
2.1 Acquisition modes and specific features 16
2.2 Easy firmware switch 16
2.3 Digitizer firmware (DGT option) 17
2.4 Real-time averaging (AVG option) 20
2.5 Peak Detection (PKD) 33
The modes available with your product depends on the firmware options ordered with your products.
To check which options and mode are present on your ADC card you can use the MD3 Software
Front Panel from the: Windows Start Menu > Acqiris > MD3 > Acqiris MD3 SFP. Then use the
menu Help > About. The field System Options gives the option list.
2.1 Acquisition modes and specific features
The following table show the availability of firmware options versus sampling rate.
Firmware Sampling Rate
-SR0 -SR1 -SR2 -SR3
-DGT üüüü
-AVG — üüü
-PKD — üüü
-TSR — üüü
-CSR — ü ü —
Combining
INT/AVG/TSR —ü— —
Table 2.1 - List of supported firmware options vs. sampling rate option.
2.2 Easy firmware switch
A simple call to the configuration function will enable to switch to the required option.

2.3 Digitizer firmware (DGT option)
U5303A User's Manual 17
2.3 Digitizer firmware (DGT option)
The digitizer firmware (normal mode) allows standard data acquisition, including: ADC card
initialization, setting of the acquisition and clocking modes, management of channel triggering for best
synchronization, storing data in the internal memory and/or transferring them to the host computer.
Single and multi-record acquisition modes
To maximize sampling rates and utilize memory as efficiently as possible the ADC cards include both
single and multi-record modes. For both of these modes the data of all of the active channels is
acquired synchronously; all of the ADC's are acquiring data at the same time, to within a small fraction
of the maximum sampling rate.
The single record acquisition mode is the normal operation of most ADC card products. In this
mode an acquisition consists of a waveform recorded with a single trigger. The user selects the
sampling rate and record size, and sets the number of records to 1 (default value). For details about the
trigger sources, see Trigger (page 12).
Figure 2.1 - Acquisition sequence using a single record.
The ADC cards also feature a multi-record acquisition mode. This mode allows the capture and
storage of consecutive single waveforms. Multi-record acquisition mode is useful as it can optimize
the ADC card's sampling rate and memory requirements for applications where only portions of the
signal being analyzed are important. The mode is extremely useful in almost all impulse-response type
applications (RADAR, SONAR, LIDAR, Time-of-Flight, Ultrasonics, Medical and Biomedical
Research, etc.).
In multi-record acquisition mode the acquisition memory is divided into a pre-selected number of
records. Waveforms are stored in successive memory records as they arrive. Each waveform requires
its own individual trigger.
Figure 2.2 - Acquisition sequence using a multi-records. It is possible to miss a trigger at high trigger rate, as
illustrated with trigger 3.

2.3 Digitizer firmware (DGT option)
18 U5303A User's Manual
The multi-record acquisition mode enables successive events, occurring within a very short time,
to be captured and stored without loss. A very fast trigger rearm time is a crucial feature for multi-
record acquisitions. Thanks to fast trigger rearm, the U5303A achieves very low “dead time” between
the records of a multi-record acquisition. The “dead time” is the period after the end of an event when
the card cannot accept a new trigger event. The re-arm time is provided in the U5303A's U5303A
datasheet.
Program examples for Single record or multi-records acquisitions are available:
For IVI-C C1:\Program Files\IVI Foundation\IVI\Drivers\AqMD3\Examples\IVI-C
For IVI.NET C:\Program Files\IVI Foundation\IVI\Drivers\AqMD3\Examples\IVI.NET
Acquisition memory
Data from the ADC is stored in on-board acquisition memory. The amount of memory in use for
acquisition can be programmed and is selectable from 1 point to the full amount of acquisition memory
available.
Model Memory option
ordered Acquisition memory Max samples/channel
U5303A
-M02 256 MB 64 MS/ch
-M10 1 GB 256 MS/ch
-M40 4 GB 1 GS/ch
Table 2.2 - Maximum number of samples which can be recorded per channel, depending on ordered memory
option.
For technical reasons, a certain acquisition memory overhead is required for each waveform, reducing
the available memory by a small amount.
The effective maximum memory available for acquisition depends on several parameters, such as
the acquisition mode (single / multi-record / streaming), sampling rate, record size, number of
records, trigger delay, etc.... This maximum is determined by the driver for each specific
configuration. The AQMD3_ATTR_MAX_SAMPLES_PER_CHANNEL attribute in IVI-C or
IAqMD3Acquisition.MaxSamplesPerChannel property in IVI.NET can be used to retrieve
the maximum number of samples per channel that can be acquired for a specific configuration.
When using the Soft Front Panel, the Max Samples per channel parameter is given on the
Acquisition panel.
1Or the alternative drive letter where the Acqiris MD3 Software has been installed on your machine.

2.3 Digitizer firmware (DGT option)
U5303A User's Manual 19
Acquisition time (Timebase range)
The timebase range defines the time period over which data is being acquired.
For example, the U5303A-M02-SR2 has a standard acquisition memory of 64 MS/ch and a maximum
sampling rate of 1.6GS/s (non-interleaved). Therefore, at the maximum sampling rate, the ADC card
can record a signal over a time window of up to 41 ms (approx. 67 M samples * 625 ps/sample).
Maximum acquisition time
There is a limit on the acquisition time / acquisition length in digitizer mode depending on the record
size, post trigger delay and binary decimation factor. Above this limit, the driver returns a post-trigger
overflow.
This limitation is given by the table below, where acquisition time = record size x sampling interval +
post-trigger delay.
Sample rate Max acquisition time (in
seconds)
1.60E+09 42.95
1.00E+09 68.72
Table 2.3 - Maximum acquisition time vs. sampling rate.
Acquired data format
The raw 12-bit data is subjected to post-calibration processing, which compensates for gain and offset
errors in the internal ADCs, The result of this post-processing is then stored and read-out as a 16-bit
value. For this reason the returned data will not always be divisible by 16 as may be expected.

2.4 Real-time averaging (AVG option)
20 U5303A User's Manual
2.4 Real-time averaging (AVG option)
Introduction
Averaging signals reduces random noise effects, improving the signal-to-noise ratio, as well as
increasing resolution and dynamic range.
The averaging is performed by accumulating successive recorded waveforms.
The number of waveforms to be accumulated and the record length are defined by user. The
waveforms are successively acquired and stored in a record. The accumulation of all the waveform
records results in an "accumulated record" which is provided in output.
The main features are:
Synchronous, single-channel and dual-channel, real-time sampling and averaging up to
3.2GS/s
Averaging from 1 up to 520'000 triggers, in steps of 8 triggers (excepted when using less than 8
triggers). Some possible values are 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32, … triggers
Effective acquisition length from 1 up to 480 KSamples in interleaving mode or up to
240KSamples per channel in dual-channel
Noise suppressed accumulation (NSA)
Self-Trigger mode for minimal synchronous (pattern) noise
Baseline stabilization algorithm and digital offset
Timing sequence
The minimum time between summed events depends on the trigger Rearm Time as specified in the
U5303A datasheet.
Figure 2.3 - Timing sequence in real-time averaging mode.
The current solution supports a single accumulated record.
The number of potential trigger lost between two acquisitions depends on several factors:
The time needed to perform the last accumulation AVG Dead Time, which depends on the
number of samples acquired. The AVG Dead Time can be estimated at #Samples x 2.1 [ns]
for SR2, or at #Samples x 1.77 [ns] for SR3.