Actel Core1553 User manual

Core1553 Development Kit
User’s Guide

© 2009 Actel Corporation. All rights reserved.
Printed in the United States of America
Part Number: 50200184-0
Release: August 2009
No part of this document may be copied or reproduced in any form or by any means without prior written
consent of Actel.
Actel makes no warranties with respect to this documentation and disclaims any implied warranties of
merchantability or fitness for a particular purpose. Information in this document is subject to change without
notice. Actel assumes no responsibility for any errors that may appear in this document.
This document contains confidential proprietary information that is not to be disclosed to any unauthorized
person without prior written consent of Actel Corporation.
Trademarks
Actel, IGLOO, Actel Fusion, ProASIC, Libero, Pigeon Point and the associated logos are trademarks or registered
trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective
owners.

Core1553 Development Kit
3
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
CORE1553 Development Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Core1553 Development Kit Web Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Core1553 Development Kit Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
User’s Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Required Items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1 Core1553 Development Kit Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Core1553BRM IP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Core1553 Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Core1553BRM Demonstration Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
FPGA Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Interpreting the HyperTerminal Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Script Mode Demonstration Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Auto Mode Demonstration Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Monitoring 1553B Message Traffic Using Silicon Explorer II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Interrupt Status Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3 Modifying the Demonstration Design Through Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Core1553BRM Verification Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Scripting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
A Programming the Fusion FPGA on M1AFS-ADV-DEV-KIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
B Communication from HyperTerminal to M1AFS-ADV-DEV-KIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
C Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Actel Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Actel Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5
Introduction
The Core1553 Development Kit demonstration enables users to evaluate the functionality of Actel’s
Core1553 Development Kit (Figure 1) without having to create a complete MIL-STD-1553B-
compliant system. You can use the files included with the Core1553 Development Kit to program a
Fusion Advanced Development Kit and create a 1553 bus controller, remote terminal, and bus
monitor compliant with the MIL-STD-1553B standard. The targeted FPGA (M1AFS1500) is mounted
on the Fusion Advanced Development Kit board and 1553 bus physical connections are included on
the Core1553 Daughter Card, which plugs directly onto the Fusion Advanced Development Kit
board. Once programmed, the development board provides the customer with a self-contained
1553 bus evaluation system.
CORE1553 Development Kit Contents
The Core1553 Development Kit includes the following items:
Figure 1 • Core1553 Development Kit
Table 1 • CORE1553-DEV-KIT Contents
Ordering Code Description
M1AFS-ADV-DEV-KIT-PWR Fusion Advanced Development Kit with power supplies
CORE1553-SA Core1553 Daughter Card
Note: You can order the full development kit or if you already have a Fusion Advanced
Development Kit ,then order only the CORE1553-SA Daughter Card.

6
Core1553 Development Kit Web Resources
CORE1553-DEV-KIT Design Files
www.actel.com/download/rsc/?f=CORE1553_DEV_KIT_DF
CORE1553-DEV-KIT Schematics
www.actel.com/products/hardware/devkits_boards/core1553_fadk.aspx
Core1553BRM IP Handbook
www.actel.com/ipdocs/Core1553BRM_HB.pdf
Fusion Advanced Development Kit Documentation
www.actel.com/products/hardware/devkits_boards/fusion_adv.aspx#rsc
Core1553 Development Kit Design Files
Associated files for this demonstration can be downloaded from the Actel website:
www.actel.com/download/rsc/?f=CORE1553_DEV_KIT_DF. These files include an Actel design
example and programming files for the example design, and contain the following folders:
• Programming_File: Pdb programming files
• Driver: Contains the CP210x_Drivers.zip file, which has the driver for the USB-to-UART
interface
• Script: Script file for testing the demo in script mode
• Designer_adb: ADB file for the demonstration design
• RTL: FPGA example design source files
Note: Core1553BRM source files are not provided in the CORE1553 Development Kit design files.
Core1553BRM IP must be purchased separately.
User’s Guide Contents
This user’s guide describes the contents, architecture, and guidelines for working with the
Core1553 Development Kit demonstration and the Core1553 Development Kit. This document
provides the following:
• Detailed user information and description of the Core1553BRM demonstration design
• Detailed reference material to be used when implementing a new design using the
Core1553 Development Kit
This user's guide covers these topics:
• Core1553 Development Kit overview
• Board description
• Core1553 Development Kit demonstration design
• Running the demonstration in script mode
• Running the demonstration in auto mode
• Modifying the demonstration script
• Programming the Fusion FPGA on M1AFS-ADV-DEV-KIT
• Communication from HyperTerminal to M1AFS-ADV-DEV-KIT

User’s Guide Contents
7
Required Items
The following items are required in order to run the Core1553 Development Kit demonstration:
• HyperTerminal or similar serial communication program
• PC system running Windows®XP operating system or later
• FlashPro software, v8.5 or later
Optional Items
• Core1553BRM obfuscated or RTL license
•Libero
®Integrated Design Environment (IDE) v8.5 or later
• Silicon Explorer II or any signal analyzer
• Silicon Explorer v5.2 or later

9
1 – Core1553 Development Kit Hardware
Core1553BRM IP Core
Actel Core1553BRM provides a complete MIL-STD-1553B bus controller (BC), remote terminal (RT),
or bus monitor terminal (BM or MT). Core1553BRM can be configured to provide all three 1553
functions or any combination thereof. The core is supported in all recent Actel flash, antifuse, and
radiation-tolerant product families. A typical system implementation using Core1553BRM is shown
in Figure 1-1.
A typical Core1553BRM system requires a connection to an external CPU, used to set up the core
registers and initialize the data tables in memory. To facilitate system integration, Core153BRM is
register-compatible with the SUMMITTM family of 1553B devices from Aeroflex®.
The external memory block is used to store the received and transmitted data. This memory can be
internal or external to the FPGA, depending upon the family targeted. The core interfaces to the
1553 bus through an external 1553 transceiver and transformer.
Core1553BRM is available in the following versions:
• An evaluation version that allows core simulation with Actel Libero IDE or ModelSim®.
• An obfuscated version that provides obfuscated RTL and precompiled testbenches.
• An RTL version with full access to the source code.
Refer to the Core1553BRM Handbook for more information.
Figure 1-1 • Typical Core1553 Application
Actel FPGA
Memory
Core1553BRM
Master
CPU
Glue
Logic
Backend
Interface
CPU
Interface
1553B
Encoders
and
Decoders
Protocol
Controller
Pulse
Transformer
Pulse
Transformer
Transceiver
Not Included

Core1553 Development Kit Hardware
10
Core1553 Development Kit
The Core1553 Development Kit includes the Fusion Advanced Development Kit board and the
Core1553 Daughter Card. This section describes the board components briefly. The CD contains the
board schematic and other required files.
Fusion Advanced Development Kit Board Description
The Fusion Advanced Development Kit (Figure 1-2) provides a low-cost board for the system
management platform, using Actel Fusion®FPGA. The evaluation board supports an ARM®
CortexTM-M1 embedded processor on a Fusion device in the FGG484 package. The evaluation
board includes the following:
• Ethernet and USB-to-UART interface for communication with the Fusion FPGA
• SRAM, parallel flash, and SPI flash
•I
2C interface, organic light-emitting diode (OLED)
• Temperature diode, potentiometer, and pulse-width modulation (PWM) circuit
• Mixed-signal header for several daughter boards to be attached for extended mixed-signal
applications
• Programming stick header so the low-cost programming stick (LCPS) can be attached to the
board for programming
Figure 1-2 • Fusion Advanced Development Kit
OLED
Display
Legacy
Connector
SPI Flash
Memory RealView
Header
SRAM/Flash
Memory
Navigation-Style
Push Switches
USB/UART
Battery Area
Main 9 V Jack
Main Power
Switch
LEDs
DirectC Header
Potentiometer
Ethernet
Connector
DIP Switches
I2C Header
50 MHz
Oscillator
32 KHz
Oscillator
M1AFS1500-
FGG484
Push-Button
Reset
Power
Programming
Header
Temperature
Diode
Mixed-Signal
Header
Interface
Header
MPM 9 V
Jack
MPM
Area
Push-
Button
PUB
MPM
Power
Switch
Current
Sensor
Gate
Driver
Internet Voltage
Regulator

Core1553 Development Kit
11
Core1553 Daughter Card Description
The Core1553 Daughter Card (Figure 1-3) has 1553B bus components mounted. Table 1 lists the
main 1553 components and their locations.
Jumpers J22 and J23
Jumpers J22 and J23 are used to configure the type of coupling to be used when connecting to a
1553B bus—either Direct or Transformer Coupling (Figure 1-4 on page 1-12). Both Bus A and Bus B
Figure 1-3 • Core1553 Daughter Card
Table 1 • Core1553 Daughter Card Components
Component Part Number Manufacturer Location
1553B transceiver BU-63147F3-320 Data Device Corporation U26
1553B transformers HLP600 Beta T1 and T2
Triax sockets CBBJR79 Trompeter J24 and J25
Note: J24 is designated as Bus A and J25 as Bus B in this demonstration design.
Connector to CORE429-SA
5 V Power
3.3 V Power
9 V Jack
CAN Interface
Connector to M1AFS-ADV-DEV-KIT Buffers
Terminators
Core1553 Interface

Core1553 Development Kit Hardware
12
can be configured independently, based upon your needs and the type of 1553B device to be
attached.
Jumpers J11 and J17
The daughter card must be connected to an external 9 V supply. When using the external power
supply, make sure that jumper JP11 and JP17 are properly installed as described in Table 1-1.
Figure 1-4 • Jumpers J5 and J7 Settings
Table 1-1 • Jumper JP11 and JP17 Settings
Jumper Function Default Setting
JP11 Jumper to select either external 3.3 V or 3.3 V
provided through connector
Pin 1–2
JP17 Jumper to select either external 5 V or 5 V provided
through legacy connector
Pin 1–2
Figure 1-5 • Core1553 Daughter Card
11
66
Direct Bus
Coupling
Transformer
Coupling
V3P3_EXT V3P3
V3P3_COMM
+
C8
10uF 16V
+
C8
10uF 16V
1
2
3
JP11JP11
V5V_EXT V5V
V5V_COMM
+
C9
10uF 16V
+
C9
10uF 16V
1
2
3
JP17JP17

13
2 – Core1553BRM Demonstration Design
The Core1553BRM demonstration design implements two complete Core1553BRM cores into a
single M1AFS1500 FPGA and allows you to evaluate the 1553 bus controller, remote terminal, and
bus monitor (monitor terminal) functions of the core (Figure 2-1). In addition, the design allows for
the monitoring of 1553B bus activity using Actel Silicon Explorer II hardware.
FPGA Design
The demonstration design contained within the M1AFS1500 FPGA consists of the following blocks:
• Two complete Core1553BRM cores
• 1553B bus interface
• Memory interface
• Bus arbiter
• Control sequencer
• UART
• DIP switches
•LEDs
• Data generator
• External memory
Figure 2-1 • Core1553BRM Demo Design Architecture
Controller
Sequencer
Core1553BRM
UNIT1
1553B
Interface
Bus Arbiter
1553B
Transceiver
Memory
2 Pages Each
64 K×16
UART
Terminal
Memory
Interface
Data
Generator
DIP
SwitchLEDs
1553 Bus
M1AFS1500
Core1553BRM
UNIT2

Core1553BRM Demonstration Design
14
Core1553BRM
Each Core1553BRM block can be configured as a bus controller or a remote/monitor terminal and
operates off 16 MHz clock. This 16 MHz clock is generated using a PLL from an on-board 50 MHz
clock. The two blocks are configured to share CPU and memory busses. Each core has access to its
own 64 K words of memory within the off-chip memory. The demo design allows configuring one
core as a bus controller and the other as remote/monitor terminal, depending on dip switch
settings.
1553B Bus Interface
The 1553B bus interface block allows the Core1553BRM blocks to be connected and form a
complete 1553 bus without any external transceivers and transformers. This block also allows the
Core1553BRM blocks to interface to an off-chip 1553B bus transceiver that is fitted on the
Core1553 Daughter Card.
Memory Interface
The memory interface ties the internal data bus to the on-board external memories, allowing each
core to interface its dedicated memory space.
Bus Arbiter
This block allows the control sequencer block and the two Core1553BRM cores to access the
internal bus.
Control Sequencer
The control sequencer connects to the BRM CPU interfaces and replaces the CPU in a typical system.
This block handles system interrupts and provides user interfaces via an external terminal over a
serial interface.
UART
The UART block implements a simple RS-232 interface running at 115,200 baud, tied to the off-chip
USB-to-UART interface. The USB-to-UART interface enables HyperTerminal on a PC to communicate
with the Fusion FPGA. HyperTerminal is a serial communications application program that can be
installed in the Windows operating system. With a USB driver properly installed, and the correct
COM port and communication settings selected, you can use the HyperTerminal program to
communicate with a design running on the Fusion FPGA device.
DIP Switches
Configuration of the demonstration design is handled by the 8-position DIP switch located at
position S1. Setting the DIP switch controls the operating mode of each Core1553BRM, sets the
remote terminal address, and can enable the bus loopback logic internal to the FPGA. Figure 2-2

FPGA Design
15
shows DIP switch bank. These switches are wired to inputs of the FPGA so that open will
correspond to logic 1 (4.7 K pull-up to 3.3 V) and closed will correspond to logic 0 (GND).
Switches 1 and 2
Switches 1 and 2 control the basic operating modes of the demonstration design.
00: Qualification testing mode. Not used for the demonstration design.
01: Script mode (non-initialization mode). The BRM core is not initialized. The core is set up via the
UART interface.
10: Auto mode. Sets one Core1553BRM core as bus controller and the other as remote/monitor
terminal and gets the data from internal data generator. Upon power-up, the state machine within
the control sequencer steps through the following set of commands to be sent to the two BRM
cores:
1. Sends configuration setting through UART.
2. Sets frame time to 0.75 seconds.
3. RT to BC transfer (SA = 25, WC = 9). RT to transmit the data from Data generator block.
4. BC generates an interrupt.
5. BC to RT transfer (SA = 2, WC = 9). BC will transmit its Data generator block data.
6. BC to RT transfer (SA = 1). BC transmits test data.
7. Waits for frame time to complete and then jumps to state 3.
8. End of frame
When the interrupt in state 4 occurs, the control sequencer increments the state 6 word count by 2.
This should be observable on HyperTerminal and the bus traffic acquired by Silicon Explorer II or
any logic analyzer. If a 1553 message fails, then the control sequencer will jump to state 8 and stop.
SA stands for 1553B subaddress; WC stands for word count.
11: Reserved
Figure 2-2 • DIP Switch Schematic
Mfr P/N :76SB08ST
Mfr: Grayhill Inc
V3P3
DIP1 {5}
DIP2 {5}
DIP3 {5}
DIP4 {5}
DIP5 {5}
DIP6 {5}
DIP7 {5}
DIP8 {5}
R144 4.7K
R146 4.7K
R143 4.7K
R142 4.7K
R141 4.7K
R140 4.7K
S1
SW DIP-8
S1
SW DIP-8
1
2
3
4
5
6
12
11
10
9
8
7
13
14
15
16
R155 4.7K
R145 4.7K

Core1553BRM Demonstration Design
16
Switches 3 and 4 (Auto Mode)
In Auto mode, switches 3 and 4 control which Core1553BRM core is the bus controller.
01: BRM 1 is the BC, BRM 2 is RT 2.
10: BRM 2 is the BC, BRM 1 is RT 1.
11: No BC, BRM 1 is RT1, and BRM 2 is RT 2.
00: No BC, BRM 1 is RT1, and BRM 2 is RT 2.
Switch 5 (Auto and Script Modes)
In Auto and Script modes, this switch sets the autobus/loopback feature.
1: 1553B buses are within the FPGA Loopback mode.
0: External 1553 transceiver is used.
Switches 6, 7, and 8 (Auto Mode)
In Auto mode, these switches set the remote terminal address to be used in the command words
sent by the bus controller. Address values can be set in the range of 000 to 111. The demonstration
configuration sets these switches to 010 (BRM core 2 is configured as remote terminal 2).
Switches 3 through 8 (Qualification Testing Mode)
In qualification testing mode, these switches set the RT address parity and RT address that the
single active BRM core will use in Qualification mode. Switch 3 is the parity and 4 to 8 are the RT
address.
LEDs
There are twelve LEDs (Figure 2-3) on the board used to indicate the status of the two BRM cores
and the message traffic between them. Table 2-1 shows the LEDs board location and functions.
Figure 2-3 • LEDs on M1AFS-ADV-DEV-KIT Board
Mfr P/N :SML-512DWT86
Mfr: Rohm
Mfr P/N :SML-512DWT86
Mfr: Rohm
Mfr P/N :SML-512DWT86
Mfr: Rohm
ACTIVE LOW
Mfr P/N :SML-512DWT86
Mfr: Rohm
V3P3V3P3
LED3_N
{5}
LED2_N{5}
LED1_N
{5}
LED4_N
{5}
LED7_N
{5}
LED8_N{5}
LED5_N{5}
LED6_N
{5}
LED9_N{5}
LED10_N{5}
LED11_N{5}
LED12_N
{5}
R48 1.5KR48 1.5K
D1
LED_ORANGE
D1
LED_ORANGE
R15 1.5KR15 1.5K
R57 1.5KR57 1.5K
D9
LED_ORANGE
D9
LED_ORANGE
R13 1.5KR13 1.5K
R56 1.5KR56 1.5K
D2
LED_ORANGE
D2
LED_ORANGE
D3
LED_ORANGE
D3
LED_ORANGE
R10 1.5KR10 1.5K
D5
LED_ORANGE
D5
LED_ORANGE
R14 1.5KR14 1.5K R41 1.5KR41 1.5K
D6
LED_ORANGE
D6
LED_ORANGE
D11
LED_ORANGE
D11
LED_ORANGE
D7
LED_ORANGE
D7
LED_ORANGE
R214 1.5KR214 1.5K
R215 1.5KR215 1.5K
D10
LED_ORANGE
D10
LED_ORANGE
R213 1.5KR213 1.5K
D8
LED_ORANGE
D8
LED_ORANGE
D12
LED_ORANGE
D12
LED_ORANGE
R216 1.5KR216 1.5K
D4
LED_ORANGE
D4
LED_ORANGE

Interpreting the HyperTerminal Display
17
Data Generator
The gata generator block generates data for 1553B messages within the demonstration design.
This data are mainly used during Auto mode.
External Memory
Core1553BRM requires a connection memory interface. It supports up to 128 Kbytes of memory,
but it mainly depends on the design. In the demonstration design, the bus arbiter allows the
controller and two cores to access the memory, which provides 64 K words of memory for each of
the cores. The two on-board SRAMs on the M1-embedded Fusion Advanced Development Kit
board are used for that purpose.
Interpreting the HyperTerminal Display
Once programmed with the Core1553BRM demonstration design and the board is powered up, the
HyperTerminal display will give information regarding the core configuration. This information is
displayed in the following form:
Core1553BRM XYZZ
The meaning of these codes depends upon the mode in which the core was powered up.
Auto mode
While in Auto mode:
• X indicates which BRM core is configured as the bus controller.
• Y: L = Loopback mode; T = Transceiver mode.
• ZZ indicates the remote terminal address for the RT.
Example display: Core1553BRM 1L02
Script mode (Non-Initialization mode)
While in Non-Initialization mode:
• X: N indicates Non-Initialization mode.
• Y: L = Loopback mode; T = Transceiver mode.
Table 2-1 • Demonstration Board LEDs
LED Board Location Function
1 D1 Heartbeat, flashes at 2 KHz
2 D2 Not used
3 D3 BRM core 1 busy
4 D4 BRM core 2 busy
5 D5 Data compare error
6 D6 Message of failure interrupt
7 D7 SRAM1 byte High enable
8 D8 SRAM1 byte Low enable
9 D9 SRAM2 byte High enable
10 D10 SRAM2 byte Low enable
11 D11 SRAM1 and SRAM2 output enable
12 D12 SRAM1 and SRAM2 write enable

Core1553BRM Demonstration Design
18
• ZZ indicates the settings for switches 6 to 8, but does not affect operation.
Example display: Core1553BRM NT00
Qualification Testing mode
While in Qualification Testing mode:
• X: Q = Qual mode; P = Qual mode, RT address parity error detected
• Y: T = Transceiver mode (only)
• ZZ indicates the RT address
Example display: Core1553BRM QT01
HyperTerminal Commands
Table 2-2 lists the available commands for use in controlling the demonstration design via
HyperTerminal.
HyperTerminal Commands Examples
Display register at location 00:
BRM1> R 00 [RETURN]
Set the value of register 00 of BRM unit 1 to 1234h:
BRM1> R1:00=0000 1234 [RETURN]
Display memory at location 0a00:
BRM1> M 0a00 [RETURN]
Set memory at location 0a00 of BRM unit 1 to value 1234h:
BRM1> M1:0a00=0000 1234 [RETURN]
Note: The system does not support backspace/delete. Use ESC and re-enter the command if an error
is made.
Table 2-2 • Core1553BRM Demonstration Terminal Commands
Commands Function Format
1 Access BRM core 1 –
2 Access BRM core 2 –
# Comment –
[ Handle commands without full echoing,
Command File mode
–
] Use full echoing, Interactive mode –
C Compare memory c 0a00 bcda
Esc Exit back to main prompt –
I Clear interrupts –
K TCLK is 1 MHz –
M Display/set memory to hex value m 0a00 [1234]
R Display/set register to hex value r 00 [1234]
T Test register t 00 1234
X Clear compare fail LED and TCLK counts on 1553B
syncs
–
Z Stop interrupt logging –

Script Mode Demonstration Design
19
Script Mode Demonstration Design
The DIP switch setting allows setting the core in script mode. In this mode the BRM cores are not
initialized. The core is set up via the UART interface.
Setting Up the Demonstration Design
The Core1553BRM Development Kit boards come preprogrammed with demonstration designs. If
you want to reprogram the FPGA or if the FPGA is programmed with a different design, follow the
steps in "Programming the Fusion FPGA on M1AFS-ADV-DEV-KIT" section on page A-29 to program
the FPGA. Once the FPGA is programmed with the correct design, you need to set up the board
according to the steps below:
1. Connect one end of the USB mini cable to USB port J2 on the M1AFS-ADV-DEV-KIT board
(labeled USB2 in Figure 2-4) and connect the other end to the USB port on your PC.
2. Connect one end of a 9 V power supply to power input J3 on the M1AFS-ADV-DEV-KIT
board (Figure 2-4) and plug the supply into an electrical outlet.
3. Set the DIP switch at S1 to the default configuration of 00011010.
Note: These switches are wired to inputs of the FPGA so that open will correspond to logic 1 (4.7 K
pull-up to 3.3 V) and closed will correspond to logic 0 GND.
4. Determine the COM port assigned to the USB interface. Open the Windows Control Panel
and double-click the System icon. Click the Hardware tab and click the Device Manager
button. Expand the Ports (Com & LPT) item in the Device Manager. Look for the CP2102 USB
to UART Bridge Controller in the list of ports. The COM port in parentheses identifies the
COM port assigned to this device (Figure 2-5). If you do not see CP2102, you need to install
the CP210x_Drivers driver. Refer to "Installing the M1AFS-ADV-DEV-KIT Board USB Serial
Driver" section on page B-31 for more information.
5. Open HyperTerminal and set the communications parameters as shown below. Set the COM
port to match the USB serial port of the board, as shown in Step 4.
Figure 2-4 • Connecting the USB and 9 V Power Supplies on the M1AFS-ADV-DEV-KIT Board
Figure 2-5 • Determining the USB Serial Port’s COM Port

Core1553BRM Demonstration Design
20
– 115,200 bits per second
– 8 data bit
– Parity set to none
– 1 stop bit
– Flow control set to none
Running the Demonstration Design in Script Mode
1. Turn the power switch SW7 on the board to the ON position.
2. Press RESET (RSTN) to restart the core. Once initialized, HyperTerminal will display the
following:
Core1553BRM NL00 0409-1
– N indicates the design is configured in Non-Initialization/Script mode.
– L indicates that bus loopback is enabled.
– 00 indicates the remote terminal address is set to 00.
Note: If the display shows any other message, check the DIP switch settings.
3. Press ESC to enter command mode (Figure 2-6).
4. From the Transfer menu, choose Send Text File. Browse to select the script file demo_log.txt
(available in the script folder of the Core1553BRM_DEV_KIT_DS.zip file), and click Open to
start the download.
The demo_log.txt script programs one Core1553BRM as the BC and the other as RT 1,
initializes the RT memory tables and sets up the BC to do a BC-to-RT, RT-to-BC, and RT
Figure 2-6 • HyperTerminal Window in Command Mode