NXP Semiconductors P89LPC952 User manual

UM10147
P89LPC952/954 User manual
Rev. 02 — 28 April 2008 User manual
Document information
Info Content
Keywords P89LPC952, P89LPC954
Abstract Technical information for the P89LPC952/954 devices.

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Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NXP Semiconductors UM10147
P89LPC952/954 User manual
Revision history
Rev Date Description
02 20080428 Added LQFP48 package information
01 20070917 Initial version

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P89LPC952/954 User manual
1. Introduction
1.1 Pin configuration
Fig 1. PLCC44 pin configuration
P89LPC952FA
P89LPC954FA
P1.3/INT0/SDA P0.4/CIN1A/KBI4/AD03
P1.2/T0/SCL P0.5/CMPREF/KBI5
P1.1/RXD0 P0.6/CMP1/KBI6
P1.0/TXD0 VDD
P3.1/XTAL1 P0.7/T1/KBI7
P3.0/XTAL2/CLKOUT P2.2/MOSI
VDD P2.3/MISO
P5.7 P2.4/SS
P5.6 P2.5/SPICLK
P5.5 P4.0
P5.4 P4.1/TRIG
P5.3 P1.4/INT1 P5.2 P1.5/RST P5.1 P1.6 P5.0 VSS
VSS P1.7/AD04
P4.7/TCLK P2.0/AD07
P4.6 P2.1/AD06
P4.5/TDI P0.0/CMP2/KBI0/AD05
P4.4 P0.1/CIN2B/KBI1/AD00
P4.3/RXD1 P0.2/CIN2A/KBI2/AD01
P4.2/TXD1 P0.3/CIN1B/KBI3/AD02
002aab307
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27
28
6 5 4 3 2 1
44
43
42 41 40

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P89LPC952/954 User manual
Fig 2. LQFP44 pin configuration
P89LPC952FBD
P89LPC954FBD
P4.1/TRIG
002aab306
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34
P1.3/INT0/SDA
P1.2/T0/SCL
P1.1/RXD0
P1.0/TXD0
P3.1/XTAL1
P3.0/XTAL2/CLKOUT
VDD
P5.7
P5.6
P5.5
P5.4
P1.4/INT1 P1.5/RST P1.6 VSS P1.7/AD04 P2.0/AD07 P2.1/AD06 P0.0/CMP2/KBI0/AD05 P0.1/CIN2B/KBI1/AD00 P0.2/CIN2A/KBI2/AD01 P0.3/CIN1B/KBI3/AD02
P0.4/CIN1A/KBI4/AD03
P0.5/CMPREF/KBI5
P0.6/CMP1/KBI6
VDD
P0.7/T1/KBI7
P2.2/MOSI
P2.3/MISO
P2.4/SS
P2.5/SPICLK
P4.0
P5.3 P5.2 P5.1 P5.0
VSS
P4.7/TCLK
P4.6
P4.5/TDI
P4.4
P4.3/RXD1
P4.2/TXD1

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P89LPC952/954 User manual
1.2 Pin description
Fig 3. LQFP48 pin configuration
P89LPC954FBD48
VDD
VREFN
P4.1/TRIG
002aad095
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23
48 47 46 45 44 43 42 41 40 39 38 37
24
P1.3/INT0/SDA
P1.2/T0/SCL
P1.1/RXD0
P1.0/TXD0
P2.7
P3.1/XTAL1
P3.0/XTAL2/CLKOUT
VDD
P5.7
P5.6
P5.5
P5.4
P5.3 P5.2 P5.1 P5.0
VSS
P4.7/TCLK
P4.6
P4.5/TDI
P4.4
P4.3/RXD1
P4.2/TXD1
P4.0
P0.4/CIN1A/KBI4/AD03
P0.5/CMPREF/KBI5
P0.6/CMP1/KBI6
VREFP
P0.7/T1/KBI7
P2.2/MOSI
P2.3/MISO
P2.4/SS
P2.5/SPICLK
P2.6
P1.4/INT1 P1.5/RST P1.6 VSS P1.7/AD04 P2.0/AD07 P2.1/AD06 P0.0/CMP2/KBI0/AD05 P0.1/CIN2B/KBI1/AD00 P0.2/CIN2A/KBI2/AD01 P0.3/CIN1B/KBI3/AD02
Table 1. Pin description
Symbol Pin Type Description
LQFP48 PLCC44 LQFP44
P0.0 to P0.7 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable
output type. During reset Port 0 latches are configured in the
input only mode with the internal pull-up disabled. The
operation of Port 0 pins as inputs and outputs depends upon
the port configuration selected. Each port pin is configured
independently. Refer to Section 5.1 “Port configurations”.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described
below:
P0.0/CMP2/
KBI0/AD05 40 43 37 I/O P0.0 — Port 0 bit 0.
OCMP2 — Comparator 2 output.
IKBI0 — Keyboard input 0.
IAD05 — ADC0 channel 5 analog input.

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P0.1/CIN2B/
KBI1/AD00 39 42 36 I/O P0.1 — Port 0 bit 1.
ICIN2B — Comparator 2 positive input B.
IKBI1 — Keyboard input 1.
IAD00 — ADC0 channel 0 analog input.
P0.2/CIN2A/
KBI2/AD01 38 41 35 I/O P0.2 — Port 0 bit 2.
ICIN2A — Comparator 2 positive input A.
IKBI2 — Keyboard input 2.
IAD01 — ADC0 channel 1 analog input.
P0.3/CIN1B/
KBI3/AD02 37 40 34 I/O P0.3 — Port 0 bit 3.
ICIN1B — Comparator 1 positive input B.
IKBI3 — Keyboard input 3.
IAD02 — ADC0 channel 2 analog input.
P0.4/CIN1A/
KBI4/AD03 36 39 33 I/O P0.4 — Port 0 bit 4.
ICIN1A — Comparator 1 positive input A.
IKBI4 — Keyboard input 4.
IAD03 — ADC0 channel 3 analog input.
P0.5/CMPREF/
KBI5 35 38 32 I/O P0.5 — Port 0 bit 5.
ICMPREF — Comparator reference (negative) input.
IKBI5 — Keyboard input 5.
P0.6/CMP1/
KBI6 34 37 31 I/O P0.6 — Port 0 bit 6.
OCMP1 — Comparator 1 output.
IKBI6 — Keyboard input 6.
P0.7/T1/KBI7313529I/OP0.7 — Port 0 bit 7.
I/O T1 — Timer/counter 1 external count input or overflow
output.
IKBI7 — Keyboard input 7.
P1.0 to P1.7 I/O,I
[1] Port 1: Port 1 is an 8-bit I/O port with a user-configurable
output type, except for three pins as noted below. During
reset Port 1 latches are configured in the input only mode
with the internal pull-up disabled. The operation of the
configurable Port 1 pins as inputs and outputs depends upon
the port configuration selected. Each of the configurable port
pins are programmed independently. Refer to Section 5.1
“Port configurations”. P1.2 to P1.3 are open drain when used
as outputs. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described
below:
P1.0/TXD0 4 10 4 I/O P1.0 — Port 1 bit 0.
OTXD0 — Transmitter output for serial port 0.
P1.1/RXD0393I/OP1.1 — Port 1 bit 1.
IRXD0 — Receiver input for serial port 0.
Table 1. Pin description …continued
Symbol Pin Type Description
LQFP48 PLCC44 LQFP44

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P1.2/T0/SCL282I/OP1.2 — Port 1 bit 2 (open-drain when used as output).
I/O T0 — Timer/counter 0 external count input or overflow output
(open-drain when used as output).
I/O SCL — I2C-bus serial clock input/output.
P1.3/INT0/SDA171I/OP1.3 — Port 1 bit 3 (open-drain when used as output).
IINT0 — External interrupt 0 input.
I/O SDA — I2C-bus serial data input/output.
P1.4/INT1 48 6 44 I/O P1.4 — Port 1 bit 4.
IINT1 — External interrupt 1 input.
P1.5/RST 47 5 43 I P1.5 — Port 1 bit 5 (input only).
IRST — External Reset input during power-on or maybe a
reset input/output if selected via UCFG1 and UCFG2. When
functioning as a reset input or input/output, a LOW on this
pin resets the microcontroller, causing I/O ports and
peripherals to take on their default states, and the processor
begins execution at address 0. When functioning as a reset
output or input/output an internal reset source will drive this
pin LOW. Also used during a power-on sequence to force
ISP mode. When using an oscillator frequency above
12 MHz, the reset input function of P1.5 must be
enabled. An external circuit is required to hold the
device in reset at power-up until VDD has reached its
specified level. When system power is removed VDD will
fall below the minimum specified operating voltage.
When using an oscillator frequency above 12 MHz, in
some applications, an external brownout detect circuit
may be required to hold the device in reset when VDD
falls below the minimum specified operating voltage.
P1.6 46 4 42 I/O P1.6 — Port 1 bit 6.
P1.7/AD04 43 2 40 I/O P1.7 — Port 1 bit 7.
IAD04 — ADC0 channel 4 analog input.
P2.0 to P2.5 I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable
output type. During reset Port 2 latches are configured in the
input only mode with the internal pull-up disabled. The
operation of Port 2 pins as inputs and outputs depends upon
the port configuration selected. Each port pin is configured
independently. Refer to Section 5.1 “Port configurations”.
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described
below:
P2.0/AD07 42 1 39 I/O P2.0 — Port 2 bit 0.
IAD07 — ADC0 channel 7 analog input.
P2.1/AD06414438I/OP2.1 — Port 2 bit 1.
IAD06 — ADC0 channel 6 analog input.
Table 1. Pin description …continued
Symbol Pin Type Description
LQFP48 PLCC44 LQFP44

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P2.2/MOSI303428I/OP2.2 — Port 2 bit 2.
I/O MOSI — SPI master out slave in. When configured as
master, this pin is output; when configured as slave, this pin
is input.
P2.3/MISO293327I/OP2.3 — Port 2 bit 3.
I/O MISO — When configured as master, this pin is input, when
configured as slave, this pin is output.
P2.4/SS 28 32 26 I/O P2.4 — Port 2 bit 4.
I/O SS — SPI Slave select.
P2.5/SPICLK273125I/OP2.5 — Port 2 bit 5.
I/O SPICLK — SPI clock. When configured as master, this pin is
output; when configured as slave, this pin is input.
P2.6 26 - - I/O P2.6 — Port 2 bit 6.
P2.7 5 - - I/O P2.7 — Port 2 bit 7.
P3.0 to P3.1 I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable
output type. During reset Port 3 latches are configured in the
input only mode with the internal pull-up disabled. The
operation of Port 3 pins as inputs and outputs depends upon
the port configuration selected. Each port pin is configured
independently. Refer to Section 5.1 “Port configurations”.
All pins have Schmitt triggered inputs.
Port 3 also provides various special functions as described
below:
P3.0/XTAL2/
CLKOUT 7126I/OP3.0 — Port 3 bit 0.
OXTAL2 — Output from the oscillator amplifier (when a crystal
oscillator option is selected via the flash configuration.
OCLKOUT — CPU clock divided by 2 when enabled via SFR
bit (ENCLK -TRIM.6). It can be used if the CPU clock is the
internal RC oscillator, watchdog oscillator or external clock
input, except when XTAL1/XTAL2 are used to generate clock
source for the RTC/system timer.
P3.1/XTAL1 6 11 5 I/O P3.1 — Port 3 bit 1.
IXTAL1 — Input to the oscillator circuit and internal clock
generator circuits (when selected via the flash configuration).
It can be a port pin if internal RC oscillator or watchdog
oscillator is used as the CPU clock source, and if
XTAL1/XTAL2 are not used to generate the clock for the
RTC/system timer.
P4.0 to P4.7 I/O Port 4: Port 4 is an 8-bit I/O port with a user-configurable
output type. During reset Port 4 latches are configured in the
input only mode with the internal pull-up disabled. The
operation of Port 4 pins as inputs and outputs depends upon
the port configuration selected. Each port pin is configured
independently. Refer to Section 5.1 “Port configurations”.
All pins have Schmitt triggered inputs.
Port 4 also provides various special functions as described
below:
Table 1. Pin description …continued
Symbol Pin Type Description
LQFP48 PLCC44 LQFP44

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[1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.
P4.0 25 30 24 I/O P4.0 — Port 4 bit 0.
P4.1/TRIG242923I/OP4.1 — Port 4 bit 1.
OTRIG — Debugger trigger output.
P4.2/TXD1232822I/OP4.2 — Port 4 bit 2.
OTXD1 — Transmitter output for serial port 1.
P4.3/RXD1222721I/OP4.3 — Port 4 bit 3.
IRXD1 — Receiver input for serial port 1.
P4.4 21 26 20 I/O P4.4 — Port 4 bit 4.
P4.5/TDI 20 25 19 I/O P4.5 — Port 4 bit 5.
I/O TDI — Serial data input/output for debugger interface.
P4.6 19 24 18 I/O P4.6 — Port 4 bit 6.
P4.7/TCLK182317I/OP4.7 — Port 4 bit 7.
ITCLK — Serial clock input for debugger interface.
P5.0 to P5.7 I/O Port 5: Port 5 is an 8-bit I/O port with a user-configurable
output type. During reset Port 5 latches are configured in the
input only mode with the internal pull-up disabled. The
operation of Port 5 pins as inputs and outputs depends upon
the port configuration selected. Each port pin is configured
independently. Refer to Section 5.1 “Port configurations”.
All pins have Schmitt triggered inputs.
Port 5 also provides various special functions as described
below:
P5.0 16 21 15 I/O P5.0 — Port 5 bit 0. High current output.
P5.1 15 20 14 I/O P5.1 — Port 5 bit 1. High current output.
P5.2 14 19 13 I/O P5.2 — Port 5 bit 2. High current output.
P5.3 13 18 12 I/O P5.3 — Port 5 bit 3. High current output.
P5.4 12 17 11 I/O P5.4 — Port 5 bit 4. High current output.
P5.5 11 16 10 I/O P5.5 — Port 5 bit 5. High current output.
P5.6 10 15 9 I/O P5.6 — Port 5 bit 6. High current output.
P5.7 9 14 8 I/O P5.7 — Port 5 bit 7. High current output.
VSS 17, 45 3, 22 16, 41 I Ground: 0 V reference.
VREFN 44 - - negative ADC reference voltage
VDD 8, 32 13, 36 7, 30 I Power supply: This is the power supply voltage for normal
operation as well as Idle and Power-down modes.
VREFP 33 - - positive ADC reference voltage
Table 1. Pin description …continued
Symbol Pin Type Description
LQFP48 PLCC44 LQFP44

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(1) 44-pin package.
(2) 48-pin package.
Fig 4. Block diagram
ACCELERATED 2-CLOCK 80C51 CPU
8 kB/16 kB
CODE FLASH
256-BYTE
DATA RAM
PORT 2
CONFIGURABLE I/Os
PORT 1
CONFIGURABLE I/Os
PORT 0
CONFIGURABLE I/Os
KEYPAD
INTERRUPT
PROGRAMMABLE
OSCILLATOR DIVIDER CPU
clock
CONFIGURABLE
OSCILLATOR
ON-CHIP RC
OSCILLATOR WITH
CLOCK DOUBLER
internal
bus
CRYSTAL
OR
RESONATOR
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
002aab305
UART0
ANALOG
COMPARATORS
256-BYTE
AUXILIARY RAM I2C-BUS
PORT 3
CONFIGURABLE I/Os
DEBUGGER
INTERFACE
P89LPC952/954
WATCHDOG TIMER
AND OSCILLATOR
TIMER 0
TIMER 1
REAL-TIME CLOCK/
SYSTEM TIMER
SPI
ADC0
P3[1:0]
P2[5:0](1)
P2[7:0](2)
PORT 4
CONFIGURABLE I/Os
PORT 5
CONFIGURABLE I/Os
P5[7:0]
P4[7:0]
P1[7:0]
P0[7:0]
XTAL2
XTAL1
TXD0
RXD0
UART1 TXD1
RXD1
SCL
SDA
T0
T1
CMP2 CIN2B
TCLK
TRIG
TDI
CIN2A CMP1
CIN1A CIN1B
AD00 AD01
AD02 AD03
AD04 AD05
AD06 AD07
SPICLK
MOSI
MISO
SS

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P89LPC952/954 User manual
1.3 Special function registers
Remark: SFR accesses are restricted in the following ways:
•User must not attempt to access any SFR locations not defined.
•Accesses to any defined SFR locations must be strictly for the functions for the SFRs.
•SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:
–‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value
when read (even if it was written with ‘0’). It is a reserved bit and may be used in
future derivatives.
–‘0’ must be written with ‘0’, and will return a ‘0’ when read.
–‘1’ must be written with ‘1’, and will return a ‘1’ when read.

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P89LPC952/954 User manual
Table 2. Special function registers
* indicates SFRs that are bit addressable.
Name Description SFR
addr. Bit functions and addresses Reset value
MSB LSB Hex Binary
BitaddressE7E6E5E4E3E2E1E0
ACC* Accumulator E0H 00 0000 0000
AD0CON ADC0 control
register 97H ENBI0 ENADCI0 TMM0 EDGE0 ADCI0 ENADC0 ADCS01 ADCS00 00 0000 0000
AD0INS ADC0 input
select A3H ADI07 ADI06 ADI05 ADI04 ADI03 ADI02 ADI01 ADI00 00 0000 0000
AD0MODA ADC0 mode
register A C0HBNDI0BURST0SCC0SCAN0----0000000000
AD0MODB ADC0 mode
register B A1HCLK2CLK1CLK0-----00000x0000
AUXR1 Auxiliary
function
register
A2H CLKLP EBRR ENT1 ENT0 SRST 0 - DPS 00 0000 00x0
BitaddressF7F6F5F4F3F2F1F0
B* B register F0H 00 0000 0000
BRGR0_0 Baud rate
generator 0
rate low
BEH 00 0000 0000
BRGR1_0 Baud rate
generator 0
rate high
BFH 00 0000 0000
BRGCON_0 Baud rate
generator 0
control
BDH------SBRGS_0BRGEN_000
[2] xxxx xx00
CMP1 Comparator 1
control register ACH - - CE1 CP1 CN1 OE1 CO1 CMF1 00[1] xx00 0000
CMP2 Comparator 2
control register ADH - - CE2 CP2 CN2 OE2 CO2 CMF2 00[1] xx00 0000
DIVM CPU clock
divide-by-M
control
95H 00 0000 0000
DPTR Data pointer
(2 bytes)

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P89LPC952/954 User manual
DPH Data pointer
high 83H 00 0000 0000
DPL Data pointer
low 82H 00 0000 0000
FMADRH Program flash
address high E7H 00 0000 0000
FMADRL Program flash
address low E6H 00 0000 0000
FMCON Program flash
control (Read) E4H BUSY - - - HVA HVE SV OI 70 0111 0000
Program flash
control (Write) E4H FMCMD.7 FMCMD.6 FMCMD.5 FMCMD.4 FMCMD.3 FMCMD.2 FMCMD.1 FMCMD.0
FMDATA Program flash
data E5H 00 0000 0000
I2ADR I2C-bus slave
address
register
DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC 00 0000 0000
Bit address DF DE DD DC DB DA D9 D8
I2CON* I2C-bus control
register D8H - I2EN STA STO SI AA - CRSEL 00 x000 00x0
I2DAT I2C-bus data
register DAH
I2SCLH Serial clock
generator/SCL
duty cycle
register high
DDH 00 0000 0000
I2SCLL Serial clock
generator/SCL
duty cycle
register low
DCH 00 0000 0000
I2STAT I2C-bus status
register D9H STA.4 STA.3 STA.2 STA.1 STA.0 0 0 0 F8 1111 1000
Bit address AF AE AD AC AB AA A9 A8
Table 2. Special function registers …continued
* indicates SFRs that are bit addressable.
Name Description SFR
addr. Bit functions and addresses Reset value
MSB LSB Hex Binary

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P89LPC952/954 User manual
IEN0* Interrupt
enable 0 A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0 EX0 00 0000 0000
Bit address EF EE ED EC EB EA E9 E8
IEN1* Interrupt
enable 1 E8H - EST - - ESPI EC EKBI EI2C 00[1] 00x0 0000
IEN2 Interrupt
enable 2 D5H - - - - EST1 ES1/ESR1 EADC - 00[1] 00x0 0000
Bit address BF BE BD BC BB BA B9 B8
IP0* Interrupt
priority 0 B8H - PWDRT PBO PS/PSR PT1 PX1 PT0 PX0 00[1] x000 0000
IP0H Interrupt
priority 0 high B7H - PWDRTH PBOH PSH/ PSRH PT1H PX1H PT0H PX0H 00[1] x000 0000
Bit address FF FE FD FC FB FA F9 F8
IP1* Interrupt
priority 1 F8H - PST - - PSPI PC PKBI PI2C 00[1] 00x0 0000
IP1H Interrupt
priority 1 high F7H - PSTH - - PSPIH PCH PKBIH PI2CH 00[1] 00x0 0000
IP2 Interrupt
priority 2 D6H - - - - PEST1 PES1/ PESR1 PADC - 00[1] 00x0 0000
IP2H Interrupt
priority 2 high D7H - - - - PEST1H PES1H/ PESR1H PADCH - 00[1] 00x0 0000
KBCON Keypad control
register 94H------PATN _SEL KBIF 00[1] xxxx xx00
KBMASK Keypad
interrupt mask
register
86H 00 0000 0000
KBPATN Keypadpattern
register 93H FF 1111 1111
Bitaddress8786858483828180
P0* Port 0 80H T1/KB7 CMP1
/KB6 CMPREF /KB5 CIN1A /KB4 CIN1B /KB3 CIN2A /KB2 CIN2B /KB1 CMP2 /KB0 [1]
Bitaddress9796959493929190
P1* Port 1 90H - - RST INT1 INT0/SDA T0/SCL RXD0 TXD0 [1]
Table 2. Special function registers …continued
* indicates SFRs that are bit addressable.
Name Description SFR
addr. Bit functions and addresses Reset value
MSB LSB Hex Binary

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Bitaddress9796959493929190
P2* Port 2 A0H - - SPICLK SS MISO MOSI - - [1]
BitaddressB7B6B5B4B3B2B1B0
P3*Port3B0H------XTAL1XTAL2
[1]
P4 Port 4 B3H - TMS - - RXD1 TXD1 TRIG T3EX [1]
P5Port5B4HT3-------
[1]
P0M1 Port 0 output
mode 1 84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF[1] 1111 1111
P0M2 Port 0 output
mode 2 85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00[1] 0000 0000
P1M1 Port 1 output
mode 1 91H (P1M1.7) (P1M1.6) - (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3[1] 11x1 xx11
P1M2 Port 1 output
mode 2 92H (P1M2.7) (P1M2.6) - (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00[1] 00x0 xx00
P2M1 Port 2 output
mode 1 A4H - - (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0) FF[1] 1111 1111
P2M2 Port 2 output
mode 2 A5H - - (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0) 00[1] 0000 0000
P3M1 Port 3 output
mode 1 B1H------(P3M1.1)(P3M1.0)03xxxx xx11
P3M2 Port 3 output
mode 2 B2H------(P3M2.1)(P3M2.0)00
[1] xxxx xx00
PCON Power control
register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 0000 0000
PCONA Power control
register A B5H RTCPD - VCPD ADPD I2PD SPPD SPD - 00[1] 0000 0000
BitaddressD7D6D5D4D3D2D1D0
PSW* Programstatus
word D0H CY AC F0 RS1 RS0 OV F1 P 00 0000 0000
PT0AD Port 0 digital
input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 xx00 000x
RSTSRC Reset source
register DFH - - BOF POF R_BK R_WD R_SF R_EX [3]
Table 2. Special function registers …continued
* indicates SFRs that are bit addressable.
Name Description SFR
addr. Bit functions and addresses Reset value
MSB LSB Hex Binary

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RTCCON RTC control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60[1][6] 011x xx00
RTCH RTC register
high D2H 00[6] 0000 0000
RTCL RTC register
low D3H 00[6] 0000 0000
S0ADDR Serial port
address
register
A9H 00 0000 0000
S0ADEN Serial port
address enable B9H 00 0000 0000
S0BUF SerialPortdata
buffer register 99H xx xxxx xxxx
Bit address 9F 9E 9D 9C 9B 9A 99 98
S0CON* Serial port
control 98H SM0_0/FE _0 SM1_00 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00 0000 0000
S0STAT Serial port
extended
status register
BAH DBMOD_0 INTLO_0 CIDIS_0 DBISEL_0 FE_0 BR_0 OE_0 STINT_0 00 0000 0000
SP Stack pointer 81H 07 0000 0111
SPCTL SPI control
register E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 04 0000 0100
SPSTAT SPI status
register E1HSPIFWCOL------0000xxxxxx
SPDAT SPI data
register E3H 00 0000 0000
S1CON Serial port 1
control B6H SM0_1/FE _1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00 0000 0000
S1STAT Serial port 1
extended
status register
D4H DBMOD_1 INTLO_1 CIDIS_1 DBISEL_1 FE_1 BR_1 OE_1 STINT_1 00 0000 0000
TAMOD Timer 0 and 1
auxiliary mode 8FH - - - T1M2 - - - T0M2 00 xxx0 xxx0
Bit address 8F 8E 8D 8C 8B 8A 89 88
Table 2. Special function registers …continued
* indicates SFRs that are bit addressable.
Name Description SFR
addr. Bit functions and addresses Reset value
MSB LSB Hex Binary

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[1] All ports are in input only (high-impedance) state after power-up.
[2] BRGR1_0 and BRGR0_0 must only be written if BRGEN_0 in BRGCON_0 SFR is logic 0. If any are written while BRGEN_0 = 1, the result is unpredictable.
[3] The RSTSRC register reflects the cause of the UM10147 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is
xx11 0000.
[4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6] The only reset source that affects these SFRs is power-on reset.
TCON* Timer 0 and 1
control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 0000 0000
TH0 Timer 0 high 8CH 00 0000 0000
TH1 Timer 1 high 8DH 00 0000 0000
TL0 Timer 0 low 8AH 00 0000 0000
TL1 Timer 1 low 8BH 00 0000 0000
TMOD Timer 0 and 1
mode 89H T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 0000 0000
TRIM Internal
oscillator trim
register
96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 [5] [6]
WDCON Watchdog
control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK [4] [6]
WDL Watchdog load C1H FF 1111 1111
WFEED1 Watchdog
feed 1 C2H
WFEED2 Watchdog
feed 2 C3H
Table 2. Special function registers …continued
* indicates SFRs that are bit addressable.
Name Description SFR
addr. Bit functions and addresses Reset value
MSB LSB Hex Binary

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Table 3. Extended special function registers
Name Description SFR
addr. Bit functions and addresses Reset value
MSB LSB Hex Binary
ADC0HBND ADC0 high_boundary register,
left (MSB) FFEFH FF 1111 1111
ADC0LBND ADC0 low_boundary register
(MSB) FFEEH 00 0000 0000
AD0DAT0R ADC0 data register 0, right
(LSB) FFFEH AD0DAT0[7:0] 00 0000 0000
AD0DAT0L ADC0 data register 0, left
(MSB) FFFFH AD0DAT0[9:2] 00 0000 0000
AD0DAT1R ADC0 data register 1, right
(LSB) FFFCH AD0DAT1[7:0] 00 0000 0000
AD0DAT1L ADC0 data register 1, left
(MSB) FFFDH AD0DAT1[9:2] 00 0000 0000
AD0DAT2R ADC0 data register 2, right
(LSB) FFFAH AD0DAT2[7:0] 00 0000 0000
AD0DAT2L ADC0 data register 2, left
(MSB) FFFBH AD0DAT2[9:2] 00 0000 0000
AD0DAT3R ADC0 data register 3, right
(LSB) FFF8H AD0DAT3[7:0] 00 0000 0000
AD0DAT3L ADC0 data register 3, left
(MSB) FFF9H AD0DAT3[9:2] 00 0000 0000
AD0DAT4R ADC0 data register 4, right
(LSB) FFF6H AD0DAT4[7:0] 00 0000 0000
AD0DAT4L ADC0 data register 4, left
(MSB) FFF7H AD0DAT4[9:2] 00 0000 0000
AD0DAT5R ADC0 data register 5, right
(LSB) FFF4H AD0DAT5[7:0] 00 0000 0000
AD0DAT5L ADC0 data register 5, left
(MSB) FFF5H AD0DAT5[9:2] 00 0000 0000
AD0DAT6R ADC0 data register 6, right
(LSB) FFF2H AD0DAT6[7:0] 00 0000 0000
AD0DAT6L ADC0 data register 6, left
(MSB) FFF3H AD0DAT6[9:2] 00 0000 0000
AD0DAT7R ADC0 data register 7, right
(LSB) FFF0H AD0DAT7[7:0]

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[1] Extended SFRs are physically located on-chip but logically located in external data memory address space (XDATA). The MOVX A,@DPTR and MOVX @DPTR,A instructions are
used to access these extended SFRs.
[2] BRGR1_1 and BRGR0_1 must only be written if BRGEN_1 in BRGCON_1 SFR is logic 0. If any are written while BRGEN_1 = 1, the result is unpredictable.
AD0DAT7L ADC0 data register 7, left
(MSB) FFF1H AD0DAT7[9:2]
BNDSTA0 ADC0 boundary status register FFEDH
BRGCON_1 Baud rate generator 1 control FFB3H - - - - - - SBRGS_
1BRGEN_ 100[2] xxxx xx00
BRG0_1 Baud rate generator 1 rate low FFB4H
BRG1_1 Baud rate generator 1 rate high FFB5H
FREEZE Peripheral clock freeze FFD0H - - - RTC_F - WDT_F T1_F T0_F 00 xxx0 0000
P4M1 Port 4 output mode 1 FFB8H (P4M1.7) (P4M1.6) (P4M1.5) (P4M1.4) (P4M1.3) (P4M1.2) (P4M1.1) (P4M1.0) FF[1] 1111 1111
P4M2 Port 4 output mode 2 FFB9H (P4M2.7) (P4M2.6) (P4M2.5) (P4M2.4) (P4M2.3) (P4M2.2) (P4M2.1) (P4M2.0) 00[1] 0000 0000
P5M1 Port 5 output mode 1 FFBAH (P5M1.7) (P5M1.6) (P5M1.5) (P5M1.4) (P5M1.3) (P5M1.2) (P5M1.1) (P5M1.0) FF[1] 1111 1111
P5M2 Port 5 output mode 3 FFBBH (P5M2.7) (P5M2.6) (P5M2.5) (P5M2.4) (P5M2.3) (P5M2.2) (P5M2.1) (P5M2.0) 00[1] 0000 0000
S1ADDR Serial port 1 address register FFB2H 00 0000 0000
S1ADEN Serial port 1 address enable FFB1H 00 0000 0000
S1BUF Serial port 1 data buffer
register FFB0H xx xxxx xxxx
Table 3. Extended special function registers …continued
Name Description SFR
addr. Bit functions and addresses Reset value
MSB LSB Hex Binary

UM10147_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 28 April 2008 20 of 134
NXP Semiconductors UM10147
P89LPC952/954 User manual
1.4 Memory organization
The various P89LPC952/954 memory spaces are as follows:
DATA — 128 bytes of internal data memory space (00h:7Fh) accessed via direct or
indirect addressing, using instruction other than MOVX and MOVC. All or part of the Stack
may be in this area.
IDATA — Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via
indirect addressing using instructions other than MOVX and MOVC. All or part of the
Stack may be in this area. This area includes the DATA area and the 128 bytes
immediately above it.
SFR — Special Function Registers. Selected CPU registers and peripheral control and
status registers, accessible only via direct addressing.
XDATA — ‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory
space addressed via the MOVX instruction using the DPTR, R0, or R1. All or part of this
space could be implemented on-chip. The P89LPC952/954 has 256 bytes of on-chip
XDATA memory.
CODE — 64 kB of Code memory space, accessed as part of program execution and via
the MOVC instruction. The P89LPC952/954 has 8 kB/ 16 kB of on-chip Code memory.
Fig 5. P89LPC952 memory map - P89LPC954 is similar
002aaa948
0000h
03FFh
0400h
07FFh
0800h
0BFFh
0C00h
0FFFh
SECTOR 0
SECTOR 1
SECTOR 2
SECTOR 3
1000h
13FFh
1400h
17FFh
1800h
1BFFh
1C00h
1E00h
1FFFh
SECTOR 4
SECTOR 5
SECTOR 6
FFEFh
FF00h IAP entry-
points
SECTOR 7
ISP CODE
(512B)*
SPECIAL FUNCTION
REGISTERS
(DIRECTLY ADDRESSABLE)
128 BYTES ON-CHIP
DATA MEMORY (STACK,
DIRECT AND INDIR. ADDR.)
4 REG. BANKS R[7:0]
data memory
(DATA, IDATA)
DATA
128 BYTES ON-CHIP
DATA MEMORY (STACK
AND INDIR. ADDR.)
IDATA (incl. DATA)
FFEFh
FF1Fh
FF00h
entry points for:
-51 ASM. code
-C code
IDATA routines
1FFFh
1E00h
entry points for:
-UART (auto-baud)
-I2C, SPI, etc.*
Flexible choices:
-as supplied (UART)
-Philips libraries*
-user-defined
ISP serial loader
entry
points
Read-protected
IAP calls only
Table 4. Data RAM arrangement
Type Data RAM Size (bytes)
DATA Directly and indirectly addressable memory 128
IDATA Indirectly addressable memory 256
XDATA Indirectly addressable using MOVX, MOVC, DPTR, R0, R1 256