SONIX SN8P2604 User manual

SN8P2604
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 1 Version1.1
SN8P2604
USER’S MANUAL
Version 1.1
S
SO ON Ni iX X 8 8- -B Bi it t M Mi ic cr ro o- -C Co on nt tr ro ol ll le er r
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.

SN8P2604
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 2 Version1.1
AMENDENT HISTORY
Version Date Description
VER 0.1 Jan. 2004 Preliminary Version 0.1 first issue
VER 0.2 Apr. 2004 1. Add the Application Notice section.
2. Modify the description of features section.
3. Modify the table of “Migration SN8P1604A to SN8P2604”
4. Modify the description of PUSH/POP in instruction table.
5. Modify the [e] parameter of SSOP28 package outline dimension.
6. Change the wakeup time formula.
VER 0.3 July. 2004 1. The first instruction at ORG 8 must be “JMP” or “NOP”.
2. Change the reset value of Y, Z, H, L, R registers from 00H to unknown.
3. In the operating ambient temperature, insert “D” after package type to indicate the
temperature range is –40°C ~ + 85°C.
4. Modify some electrical characteristics: ViL, ViH, Ilekg, Rup, IoH.
5. Add “Development Tool Version” section in “Application Notice” chapter.
6. Change chapter name “TRANSITION SOCKET” to “OTP PROGRAMMING PIN” and
modify the contents.
7. Remove “Template Code” chapter.
VER 0.4 July. 2004 Change the description of ”S” parameter in all instruction cycle related explanation.
VER 0.5 July. 2004 Remove all TC0 timer description and modify programming information.
VER 0.6 Aug. 2004 Modify Xout = Fcpu output pin in system clock chapter.
VER 1.0 Dec. 2004 1. Add SN8P26042P/S/X pin assignment.
2. Add T0, TC1, PWM application notices.
3. T0C doesn’t support read and modify write instructions.
4. Modify operating mode, stack, reset, I/O, programming pins diagrams.
5. Modify timer, system clock descriptions.
6. Modify system clock description.
7. Remove ORG4~7 limitation.
VER 1.1 Jan. 2005 1. Re-arrange partial edition layout.
2. Strongly recommend using SN8ICE-2K ICE to emulate SN8P2604. SN8IDE V1.99S
or later No More support SN8P2000 series emulation.

SN8P2604
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 3 Version1.1
Table of Content
AMENDENT HISTORY................................................................................................................................ 2
1
1
1PRODUCT OVERVIEW................................................................................................................. 8
1.1 FEATURES........................................................................................................................................ 8
1.2 SYSTEM BLOCK DIAGRAM........................................................................................................ 10
1.3 PIN ASSIGNMENT......................................................................................................................... 11
1.4 PIN DESCRIPTIONS ...................................................................................................................... 12
1.5 PIN CIRCUIT DIAGRAMS ............................................................................................................ 13
2
2
2CENTRAL PROCESSOR UNIT (CPU) ...................................................................................... 14
2.1 MEMORY MAP............................................................................................................................... 14
2.1.1 PROGRAM MEMORY (ROM) ................................................................................................. 14
2.1.1.1 RESET VECTOR (0000H) .................................................................................................. 15
2.1.1.2 INTERRUPT VECTOR (0008H)......................................................................................... 16
2.1.1.3 LOOK-UP TABLE DESCRIPTION.................................................................................... 18
2.1.1.4 JUMP TABLE DESCRIPTION........................................................................................... 20
2.1.1.5 CHECKSUM CALCULATION........................................................................................... 22
2.1.2 CODE OPTION TABLE........................................................................................................... 23
2.1.3 DATA MEMORY (RAM)........................................................................................................... 24
2.1.4 SYSTEM REGISTER.................................................................................................................25
2.1.4.1 SYSTEM REGISTER TABLE ............................................................................................ 25
2.1.4.2 BIT DEFINITION of SYSTEM REGISTER....................................................................... 26
2.1.4.3 ACCUMULATOR ............................................................................................................... 27
2.1.4.4 PROGRAM FLAG............................................................................................................... 28
2.1.4.5 PROGRAM COUNTER....................................................................................................... 29
2.1.4.6 H, L REGISTERS................................................................................................................. 32
2.1.4.7 Y, Z REGISTERS................................................................................................................. 33
2.1.4.8 R REGISTERS..................................................................................................................... 34
2.2 ADDRESSING MODE.................................................................................................................... 35
2.2.1 IMMEDIATE ADDRESSING MODE....................................................................................... 35
2.2.2 DIRECTLY ADDRESSING MODE.......................................................................................... 35
2.2.3 INDIRECTLY ADDRESSING MODE...................................................................................... 35
2.3 STACK OPERATION ..................................................................................................................... 36

SN8P2604
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 4 Version1.1
2.3.1 OVERVIEW .............................................................................................................................. 36
2.3.2 STACK REGISTERS.................................................................................................................37
2.3.3 STACK OPERATION EXAMPLE............................................................................................. 38
3
3
3RESET............................................................................................................................................. 39
3.1 OVERVIEW..................................................................................................................................... 39
3.2 POWER ON RESET........................................................................................................................ 41
3.3 WATCHDOG RESET...................................................................................................................... 41
3.4 EXTERNAL RESET........................................................................................................................ 42
3.4.1 EXTERNAL RESET CIRCUIT.................................................................................................. 42
3.5 LOW VOLTAGE DETECTOR (LVD) ........................................................................................... 43
4
4
4SYSTEM CLOCK.......................................................................................................................... 44
4.1 OVERVIEW..................................................................................................................................... 44
4.2 CLOCK BLOCK DIAGRAM.......................................................................................................... 44
4.3 OSCM REGISTER........................................................................................................................... 45
4.4 SYSTEM HIGH CLOCK................................................................................................................. 46
4.4.1 EXTERNAL HIGH CLOCK...................................................................................................... 46
4.4.1.1 CRYSTAL/CERAMIC......................................................................................................... 47
4.4.1.2 RC......................................................................................................................................... 47
4.4.1.3 EXTERNAL CLOCK SIGNAL........................................................................................... 48
4.5 SYSTEM LOW CLOCK.................................................................................................................. 49
4.5.1 SYSTEM CLOCK MEASUREMENT........................................................................................ 50
5
5
5SYSTEM OPERATION MODE................................................................................................... 51
5.1 OVERVIEW..................................................................................................................................... 51
5.2 SYSTEM MODE SWITCHING...................................................................................................... 52
5.3 WAKEUP......................................................................................................................................... 54
5.3.1 OVERVIEW .............................................................................................................................. 54
5.3.2 WAKEUP TIME........................................................................................................................ 54
5.3.3 P1W WAKEUP CONTROL REGISTER................................................................................... 55

SN8P2604
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 5 Version1.1
6
6
6INTERRUPT................................................................................................................................... 56
6.1 OVERVIEW..................................................................................................................................... 56
6.2 INTEN INTERRUPT ENABLE REGISTER .................................................................................. 57
6.3 INTRQ INTERRUPT REQUEST REGISTER................................................................................ 58
6.4 GIE GLOBAL INTERRUPT OPERATION.................................................................................... 59
6.5 PUSH, POP ROUTINE.................................................................................................................... 60
6.6 INT0 (P0.0) INTERRUPT OPERATION........................................................................................ 61
6.7 INT1 (P0.1) INTERRUPT OPERATION........................................................................................ 62
6.8 T0 INTERRUPT OPERATION....................................................................................................... 63
6.9 TC1 INTERRUPT OPERATION .................................................................................................... 64
6.10 MULTI-INTERRUPT OPERATION............................................................................................... 65
7
7
7I/O PORT........................................................................................................................................ 66
7.1 I/O PORT MODE............................................................................................................................. 66
7.2 I/O PULL UP REGISTER................................................................................................................ 67
7.3 I/O OPEN-DRAIN REGISTER........................................................................................................ 68
7.4 I/O PORT DATA REGISTER ......................................................................................................... 69
8
8
8TIMERS .......................................................................................................................................... 70
8.1 WATCHDOG TIMER ..................................................................................................................... 70
8.2 TIMER 0 (T0)................................................................................................................................... 72
8.2.1 OVERVIEW .............................................................................................................................. 72
8.2.2 T0M MODE REGISTER........................................................................................................... 73
8.2.3 T0C COUNTING REGISTER................................................................................................... 74
8.2.4 T0 TIMER OPERATION SEQUENCE..................................................................................... 75
8.2.5 T0 TIMER NOTICE.................................................................................................................. 76
8.3 TIMER/COUNTER 1 (TC1)............................................................................................................ 77
8.3.1 OVERVIEW .............................................................................................................................. 77
8.3.2 TC1M MODE REGISTER........................................................................................................ 78
8.3.3 TC1C COUNTING REGISTER................................................................................................ 79
8.3.4 TC1R AUTO-LOAD REGISTER .............................................................................................. 80
8.3.5 TC1 CLOCK FREQUENCY OUTPUT (BUZZER).................................................................. 81
8.3.6 TC1 TIMER OPERATION SEQUENCE .................................................................................. 82

SN8P2604
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 6 Version1.1
8.3.7 TC1 TIMER NOTICE ............................................................................................................... 84
8.4 PWM1 MODE.................................................................................................................................. 85
8.4.1 OVERVIEW .............................................................................................................................. 85
8.4.2 TC1IRQ AND PWM DUTY ...................................................................................................... 86
8.4.3 PWM PROGRAM EXAMPLE .................................................................................................. 87
8.4.4 PWM1 DUTY CHANGING NOTICE....................................................................................... 88
9
9
9INSTRUCTION TABLE ...............................................................................................................90
1
1
10
0
0ELECTRICAL CHARACTERISTIC.................................................................................. 91
10.1 ABSOLUTE MAXIMUM RATING................................................................................................ 91
10.2 ELECTRICAL CHARACTERISTIC .............................................................................................. 91
1
1
11
1
1APPLICATION NOTICE ..................................................................................................... 92
11.1 DEVELOPMENT TOOL VERSION ......................................................................................................... 92
11.1.1 ICE (In circuit emulation) ........................................................................................................ 92
11.1.2 OTP Writer............................................................................................................................... 92
11.1.3 SN8IDE..................................................................................................................................... 92
11.2 CODE OPTION................................................................................................................................ 93
11.2.1 FCPU CODE OPTION ............................................................................................................ 93
11.2.2 NOISE FILTER CODE OPTION ............................................................................................. 93
11.2.3 WATCHDOG............................................................................................................................ 93
11.3 INTERRUPT VECTOR (ORG 8).................................................................................................... 94
11.4 INSTRUCTION................................................................................................................................ 95
11.4.1 B0MOV M,I .............................................................................................................................. 95
11.4.2 B0XCH A, M............................................................................................................................. 95
11.5 S8KD-2 ICE ENULATION ............................................................................................................. 96
11.5.1 ICE_MODE.............................................................................................................................. 96
11.5.2 INSTRUCTION CYCLE............................................................................................................ 97
11.5.3 SYSTEM CLOCK...................................................................................................................... 99
11.5.4 WATCHDOG TIMER............................................................................................................. 100
11.5.5 P0 EMULATION .................................................................................................................... 101
11.5.5.1 @P00_MODE, @P01_MODE....................................................................................... 101
11.5.5.2 @P00_OUT, @P01_OUT.............................................................................................. 102

SN8P2604
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 7 Version1.1
11.5.5.3 PEDGE ........................................................................................................................... 103
11.5.6 PWM DUTY............................................................................................................................ 104
11.5.7 OTHER MACRO..................................................................................................................... 105
1
1
12
2
2OTP PROGRAMMING PIN............................................................................................... 106
12.1.1 The pin assignment of Easy Writer transition board socket:................................................. 106
12.1.2 The pin assignment of Writer V3.0 and V2.5 transition board socket:.................................. 106
12.1.3 SN8P2604 Programming Pin Mapping: ................................................................................ 107
1
1
13
3
3PACKAGE INFORMATION ............................................................................................. 108
13.1 SK-DIP 28 PIN............................................................................................................................... 108
13.2 SOP 28 PIN .................................................................................................................................... 109
13.3 SSOP 28 PIN.................................................................................................................................. 110
13.4 P-DIP 20 PIN.................................................................................................................................. 111
13.5 SOP 20 PIN .................................................................................................................................... 112
13.6 SSOP 20 PIN.................................................................................................................................. 113

SN8P2604
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 8 Version1.1
1
1
1 PRODUCT OVERVIEW
1.1 FEATURES
 Features Selection Table
Timer PWM
CHIP ROM RAM Stack T0 TC1 I/O Green
Mode Buzzer
Wakeup
Pin No. Package
SN8P1604A 4K*16 128 8 V 22 - V 10 SK-DIP28/SOP28
SN8P2604 4K*16 128 8 V V 24 V V 11 SK-DIP28/SOP28/SSOP28
SN8P26042 4K*16 128 8 V V 16 V V 11 P-DIP20/SOP20/SSOP20
♦Memory configuration ♦Four interrupt sources
OTP ROM size: 4K * 16 bits. Two internal interrupts: T0, TC1.
RAM size: 128 * 8 bits. Two external interrupts: INT0, INT1.
Eight levels stack buffer
♦Two 8-bit Timer/Counter
♦I/O pin configuration T0: Basic timer
Bi-directional: P0, P1, P2, P5 TC1: Auto-reload timer counter/PWM1/Buzzer output
Programmable open-drain: P1.0, P1.1
Wakeup: P0, P1 level change trigger ♦On chip watchdog timer and clock source is internal
Pull-up resisters: P0, P1, P2, P5 low clock RC type (16KHz @3V, 32KHz @5V).
External interrupt input: P0.0, P0.1
External Interrupt trigger edge: ♦Dual system clocks
P0.0 controlled by PEDGE register External high clock: RC type up to 10 MHz
P0.1 is falling edge trigger only External high clock: Crystal type up to 16 MHz
Internal low clock: RC type 16KHz(3V), 32KHz(5V)
♦Powerful instructions ♦Operating modes
One clocks per instruction cycle (1T) Normal mode: Both high and low clock active
Most of instructions are one cycle only. Slow mode: Low clock only
All ROM area JMP instruction. Sleep mode: Both high and low clock stop
All ROM area CALL address instruction. Green mode: Periodical wakeup by T0 timer
All ROM area lookup table function (MOVC)
♦Package (Chip form support)
SK-DIP 28 pins
SOP 28 pins
SSOP 28 pins
P-DIP 20 pins
SOP 20 pins
SSOP 20 pins

SN8P2604
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 9 Version1.1
 Migration SN8P1604A to SN8P2604
Item SN8P2604 SN8P1604A
DAA Not available Available
PUSH/POP Available Not available
B0MOV M, I I can’t be 0E6h or 0E7h -
B0XCH A, M The address of M can’t be
80h~FFh -
Valid instruction in ROM address 8 JMP or NOP No Limitation
AC Noise Immunity Capability Excellent
(Add an 47uF bypass Capacitor) Normal
Computation Power (16Mhz Crystal) Up to 16 MIPS Up to 4 MIPS
High Speed PWM
PWM Resolution: 8bit/6bit/5bit/4bit
High Clock = 16MHz
Up to 31.25K at 8bit resolution
Up to 500K at 4bit resolution
PWM Resolution: 8bit only
High Clock = 16MHz
Up to 7.8125K at 8bit resolution
Timer T0/TC1 TC1
Maximum I/O number 24 (P0.2) 22
Programmable Open-Drain Output P1.0/P1.1 -
On-chip Pull-up Resistor Configuration by pin
(use PnUR register) Configuration by port (Use PUR register)
Green Mode Yes (by T0 timer) -
P0.0 Interrupt trigger Edge
Controlled by PEDGE register:
P00G[1:0]: (bit4 and bit3)
00: Reserved
01: Rising edge
10: Falling edge
11: Level change
Controlled by PEDGE register:
PEDGEN (bit7):
0: Falling edge
1: Defined by P00G[1:0]
P00G[1:0]: (bit4 and bit3)
00: Reserved
01: Falling edge
10: Rising edge
11: Level change
P0.1 Interrupt trigger Edge Falling P0.1 no interrupt function
P0.0 Wakeup Level Change
Controlled by PEDGE register:
PEDGEN (bit7):
0: Falling edge
1: Defined by P00G[1:0]
P00G[1:0]: (bit4 and bit3)
00: Reserved
01: Falling edge
10: Rising edge
11: Level change
P0.1 Wakeup Level Change
Controlled by PEDGE register:
PEDGEN (bit7):
0: Low level wakeup
1: Level change
Port 1 Wakeup Level Change
Controlled by PEDGE register:
PEDGEN (bit7):
0: Low level wakeup
1: Level change
Wakeup Time 1/Fosc * 4096 (sec)
+ Oscillator settling time 1/Fosc * 2048 (sec) + Oscillator settling time
Schmitt Trigger input All input pin P0.0, P0.1, RST, XIN
Watchdog timer clock source Internal Low RC Only Internal Low RC
External High Clock
Clear Watchdog MOV A, #0x5A
B0MOV WDTR, A B0BSET FWDRST
Standby Current 1uA at 5V 10uA at 5V
LVD 1.8V always ON 1.8V always ON
 Note: Level change trigger mean falling or rising edge trigger.

SN8P2604
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 10 Version1.1
1.2 SYSTEM BLOCK DIAGRAM
PC
IR R
O
M
H-OSC
TIMING GENERATOR
RAM
SYSTEM REGISTER
ALU
ACC
INTERRUPT
CONTROL TIMER & COUNTER
PORT 0
PORT 1
FLAGS
Internal
Low
RC
POR
Watch
Dog
SN8P2604
PWM
PORT 5
PWM & BUZZER
PORT 2
PC
IR R
O
M
H-OSC
TIMING GENERATOR
RAM
SYSTEM REGISTER
ALU
ACC
INTERRUPT
CONTROL TIMER & COUNTER
PORT 0
PORT 1
FLAGS
Internal
Low
RC
POR
Watch
Dog
SN8P2604
PWM
PORT 5
PWM & BUZZER
PORT 2

SN8P2604
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 11 Version1.1
1.3 PIN ASSIGNMENT
SN8P2604K (SK-DIP 28 pins)
SN8P2604S (SOP 28 pins)
SN8P2604X (SSOP 28 pins)
P0.1/INT1 1 U 28 RST/VPP/P0.2
VDD 2 27 XIN
P5.4 3 26 XOUT/Fcpu
VSS 4 25 P2.7
P0.0/INT0 5 24 P2.6
P5.0 6 23 P2.5
P5.1 7 22 P2.4
P5.2 8 21 P2.3
P5.3/BZ1/PWM1 9 20 P2.2
P1.0 10 19 P2.1
P1.1 11 18 P2.0
P1.2 12 17 P1.7
P1.3 13 16 P1.6
P1.4 14 15 P1.5
SN8P2604K
SN8P2604S
SN8P2604X
SN8P26042P (P-DIP 20 pins)
SN8P26042S (SOP 20 pins)
SN8P26042X (SSOP 20 pins)
P5.1 1 U 20 P5.0
P5.3/BZ1/PWM 2 19 P0.0/INT0
P1.0 3 18 VSS
P1.1 4 17 VDD
P1.2 5 16 P0.1
P1.3 6 15 RST/VPP/P0.2
P1.4 7 14 XIN
P1.5 8 13 XOUT/Fcpu
P1.6 9 12 P2.7
P1.7 10 11 P2.0
SN8P26042P
SN8P26042S
SN8P26042X

SN8P2604
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 12 Version1.1
1.4 PIN DESCRIPTIONS
PIN NAME TYPE DESCRIPTION
VDD, VSS P Power supply input pins for digital circuit.
P0.2/RST/VPP I, P
P0.2: Input only pin (Schmitt trigger) if disable external reset function.
P0.2 without build-in pull-up resister
RST: System reset input pin. Schmitt trigger structure, low active, normal stay to “high”.
VPP: OTP programming pin.
XIN I Oscillator input pin while external oscillator enable (crystal and RC).
XOUT/Fcpu I/O
XOUT: Oscillator output pin while external crystal enable.
Fcpu: Signal output pin while external RC mode enable.
P0.0/INT0 I/O
Port 0.0 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
INT0 trigger pin (Schmitt trigger).
P0.1/INT1 I/O
Port 0.1 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
INT1 trigger pin (Schmitt trigger).
TC1 event counter clock input pin.
P1.0~P1.1 I/O
Port 1.0, P1.1 bi-direction pin and open-drain pin. Schmitt trigger structure as input
mode.
Built-in pull-up resisters.
P1.2~P1.7 I/O
Port 1.2~P1.7 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
P2.0~P2.7 I/O
Bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
P5.0~P5.2, P5.4 I/O Port 5 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
P5.3/BZ1/PWM1 I/O
Port 5.3 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
TC1 ÷ 2 signal output pin for buzzer or PWM1 output pin.

SN8P2604
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 13 Version1.1
1.5 PIN CIRCUIT DIAGRAMS
Port 0, 1, 2, 5 structure:
Pull-Up
Pin
Output
Latch
PnM, PnUR
Input Bus
PnM
Output Bus
Port 1.0, P1.1 structure:
Pull-Up
Pin
Output
Latch
PnM, PnUR
Input Bus
PnM
Output Bus
P1OC Open-Drain
Port 0.2 structure:
Pin
Ext. Reset
Code Option
Int. Bus
Int. Rst

SN8P2604
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 14 Version1.1
2
2
2 CENTRAL PROCESSOR UNIT (CPU)
2.1 MEMORY MAP
2.1.1 PROGRAM MEMORY (ROM)
 4K words ROM
ROM
0000H Reset vector User reset vector
0001H Jump to user start address
0002H Jump to user start address
0003H General purpose area Jump to user start address
0004H
0005H
0006H
0007H
General purpose area
0008H Interrupt vector User interrupt vector
0009H User program
.
.
000FH
0010H
0011H
.
.
.
.
.
0FFBH
General purpose area
End of user program
0FFCH
0FFDH
0FFEH
0FFFH
Reserved

SN8P2604
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 15 Version1.1
2.1.1.1 RESET VECTOR (0000H)
A one-word vector address area is used to execute system reset.
 Power On Reset (NT0=1, NPD=0).
 Watchdog Reset (NT0=0, NPD=0).
 External Reset (NT0=1, NPD=1).
After power on reset, external reset or watchdog timer overflow reset, then the chip will restart the program from
address 0000h and all system registers will be set as default values. It is easy to know reset status from NT0, NPD
flags of PFLAG register. The following example shows the way to define the reset vector in the program memory.
 Example: Defining Reset Vector
ORG 0 ; 0000H
JMP START ; Jump to user program address.
…
ORG 10H
START: ; 0010H, The head of user program.
… ; User program
…
ENDP ; End of program

SN8P2604
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 16 Version1.1
2.1.1.2 INTERRUPT VECTOR (0008H)
A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program
counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt.
Users have to define the interrupt vector and the first instruction at ORG 8 must be “JMP” or “NOP”. The following
example shows the way to define the interrupt vector in the program memory.
 Note: ”PUSH”, “POP” instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is a
unique buffer and only one level.
 Note: The first instruction at ORG 8 must be “JMP” or “NOP”.
 Example: Defining Interrupt Vector. The interrupt service routine is following ORG 8.
.CODE
ORG 0 ; 0000H
JMP START ; Jump to user program address.
…
ORG 8 ; Interrupt vector.
NOP ; The first instruction at ORG 8.
PUSH ; Save ACC and PFLAG register to buffers.
…
…
POP ; Load ACC and PFLAG register from buffers.
RETI ; End of interrupt service routine
…
START: ; The head of user program.
… ; User program
…
JMP START ; End of user program
…
ENDP ; End of program

SN8P2604
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 17 Version1.1
 Example: Defining Interrupt Vector. The interrupt service routine is following user program.
.DATA ACCBUF DS 1 ; Define ACCBUF for store ACC data.
PFLAGBUF DS 1 ; Define PFLAGBUF for store PFLAG data.
.CODE
ORG 0 ; 0000H
JMP START ; Jump to user program address.
…
ORG 8 ; Interrupt vector.
JMP MY_IRQ ; 0008H, Jump to interrupt service routine address.
ORG 10H
START: ; 0010H, The head of user program.
… ; User program.
…
…
JMP START ; End of user program.
…
MY_IRQ: ;The head of interrupt service routine.
PUSH ; Save ACC and PFLAG register to buffers.
…
…
POP ; Load ACC and PFLAG register from buffers.
RETI ; End of interrupt service routine.
…
ENDP ; End of program.
 Note: It is easy to understand the rules of SONIX program from demo programs given above. These
points are as following:
1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.
2. The address 0008H is interrupt vector and the first instruction must be “NOP” or “JMP”.
3. User’s program is a loop routine for main purpose application.

SN8P2604
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 18 Version1.1
2.1.1.3 LOOK-UP TABLE DESCRIPTION
In the ROM’s data lookup function, Y register is pointed to middle byte address (bit 8~bit 15) and Z register is pointed
to low byte address (bit 0~bit 7) of ROM. After MOVC instruction executed, the low-byte data will be stored in ACC and
high-byte data stored in R register.
 Note: “B0MOV M, I” instruction doesn’t support “I=0xE6” and “I=0xE7”. In look-up table application,
users have to check Y,Z value not be “0xE6” and “0xE7”. To set ROM address of table start and avoid
Y,Z to be “0xE6” and “0xE7”.
 Example: To look up the ROM data located “TABLE1”.
B0MOV Y, #TABLE1$M ; To set lookup table1’s middle address
B0MOV Z, #TABLE1$L ; To set lookup table1’s low address.
MOVC ; To lookup data, R = 00H, ACC = 35H
; Increment the index address for next address.
INCMS Z ; Z+1
JMP @F ; Z is not overflow.
INCMS Y ; Z overflow (FFH 00), Y=Y+1
NOP ;
;
@@: MOVC ; To lookup data, R = 51H, ACC = 05H.
… ;
ORG 0x0100 ; Set TABLE1 start address is 0x0100 to avoid “B0MOV M, I”
instruction doesn’t support “I=0xE6” and “I=0xE7”.
TABLE1: DW 0035H ; To define a word (16 bits) data.
DW 5105H
DW 2012H
…
 Note: The Y register will not increase automatically when Z register crosses boundary from 0xFF to
0x00. Therefore, user must take care such situation to avoid loop-up table errors. If Z register
overflows, Y register must be added one. The following INC_YZ macro shows a simple method
to process Y and Z registers automatically.
 Example: INC_YZ macro.
INC_YZ MACRO
INCMS Z ; Z+1
JMP @F ; Not overflow
INCMS Y ; Y+1
NOP ; Not overflow
@@:
ENDM

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 Example: Modify above example by “INC_YZ” macro.
B0MOV Y, #TABLE1$M ; To set lookup table1’s middle address
B0MOV Z, #TABLE1$L ; To set lookup table1’s low address.
MOVC ; To lookup data, R = 00H, ACC = 35H
INC_YZ ; Increment the index address for next address.
;
@@: MOVC ; To lookup data, R = 51H, ACC = 05H.
… ;
ORG 0x0100 ; Set TABLE1 start address is 0x0100 to avoid “B0MOV M, I”
instruction doesn’t support “I=0xE6” and “I=0xE7”.
TABLE1: DW 0035H ; To define a word (16 bits) data.
DW 5105H
DW 2012H
…
The other example of loop-up table is to add Y or Z index register by accumulator. Please be careful if “carry” happen.
 Example: Increase Y and Z register by B0ADD/ADD instruction.
B0MOV Y, #TABLE1$M ; To set lookup table’s middle address.
B0MOV Z, #TABLE1$L ; To set lookup table’s low address.
B0MOV A, BUF ; Z = Z + BUF.
B0ADD Z, A
B0BTS1 FC ; Check the carry flag.
JMP GETDATA ; FC = 0
INCMS Y ; FC = 1. Y+1.
NOP
GETDATA: ;
MOVC ; To lookup data. If BUF = 0, data is 0x0035
; If BUF = 1, data is 0x5105
; If BUF = 2, data is 0x2012
…
ORG 0x0100 ; Set TABLE1 start address is 0x0100 to avoid “B0MOV M, I”
instruction doesn’t support “I=0xE6” and “I=0xE7”.
TABLE1: DW 0035H ; To define a word (16 bits) data.
DW 5105H
DW 2012H
…

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2.1.1.4 JUMP TABLE DESCRIPTION
The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC
value to get one new PCL. If PCL is overflow after PCL+ACC, PCH adds one automatically. The new program counter
(PC) points to a series jump instructions as a listing table. It is easy to make a multi-jump program depends on the
value of the accumulator (A).
 Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and
not change.
 Example: Jump table.
ORG 0X0100 ; The jump table is from the head of the ROM boundary
B0ADD PCL, A ; PCL = PCL + ACC, PCH + 1 when PCL overflow occurs.
JMP A0POINT ; ACC = 0, jump to A0POINT
JMP A1POINT ; ACC = 1, jump to A1POINT
JMP A2POINT ; ACC = 2, jump to A2POINT
JMP A3POINT ; ACC = 3, jump to A3POINT
SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump
table to the right position automatically. The side effect of this macro maybe wastes some ROM size.
 Example: If “jump table” crosses over ROM boundary will cause errors.
@JMP_A MACRO VAL
IF (($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00)
JMP ($ | 0XFF)
ORG ($ | 0XFF)
ENDIF
ADD PCL, A
ENDM
 Note: “VAL” is the number of the jump table listing number.