NEC V850E/CA2 JUPITER User manual

Preliminary User’s Manual
V850E/CA2TM JUPITER
32-/16-bit Romless Microcontroller
Hardware
µPD703128, µPD703129
Document No. U15839EE1V0UM00
Date Published August 2003
NEC Corporation 2003
Printed in Germany

2Preliminary User’s Manual U15839EE1V0UM00
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimatelydegradethedeviceoperation. Stepsmustbetakentostopgenerationofstaticelectricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulatorsthateasilybuildstaticelectricity. Semiconductordevicesmustbestoredandtransported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wriststrap. Semiconductordevicesmust notbetouchedwithbarehands. Similarprecautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
totheinput pins, it is possible that aninternalinputlevelmaybegenerated due to noise, etc., hence
causingmalfunction. CMOSdevicesbehave differentlythanBipolarorNMOSdevices. Inputlevels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

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Preliminary User’s Manual U15839EE1V0UM00
•The information in this document is current as of 18.08, 2003. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
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may appear in this document.
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No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual
property rights of NEC Electronics or others.
•Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation
of these circuits, software and information in the design of customer's equipment shall be done
under the full responsibility of customer. NEC Electronics no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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anti-disaster systems, anti-crime systems, safety equipment and medical equipment
(not specifically designed for life support).
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life support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is “Standard”unless otherwise expressly specified in
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Notes: 1. " NEC Electronics" as used in this statement means NEC Electronics Corporation and
also includes its majority-owned subsidiaries.
2. " NEC Electronics products" means any product developed or manufactured by or for
NEC Electronics (as defined above).
M8E 02.10

4Preliminary User’s Manual U15839EE1V0UM00
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: [phone]
800-366-9782
Fax: [phone]
800-729-9288
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5
Preliminary User’s Manual U15839EE1V0UM00
Preface
Readers This manual is intended for users who want to understand the functions of the
V850E/CA2 (nickname Jupiter).
Purpose This manual presents the hardware manual of V850E/CA2.
Organization This system specification describes the following sections:
•Pin function
•CPU function
•Internal peripheral function
Legend Symbols and notation are used as follows:
Weight in data notation : Left is high-order column, right is low order column
Active low notation : xxx (pin or signal name is over-scored) or
/xxx (slash before signal name)
Memory map address: : High order at high stage and low order at low stage
Note : Explanation of (Note) in the text
Caution : Item deserving extra attention
Remark : Supplementary explanation to the text
Numeric notation : Binary . . . XXXX or XXXB
Decimal . . . XXXX
Hexadecimal . . . XXXXH or 0x XXXX
Prefixes representing powers of 2 (address space, memory capacity)
K (kilo) : 210 = 1024
M (mega) : 220 = 10242= 1,048,576
G (giga) : 230 = 10243= 1,073,741,824

6Preliminary User’s Manual U15839EE1V0UM00

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Preliminary User’s Manual U15839EE1V0UM00
Table of Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.2 Device Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.3 Application Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.5 Pin Configuration (Top View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.6 Function Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.6.1 On-chip units. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Chapter 2 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.1 List of Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2 Description of Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.3 Types of Pin I/O Circuit and Connection of Unused Pins . . . . . . . . . . . . . . . . . . . . . . 51
Chapter 3 CPU Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.2 CPU Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.2.1 Program register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.2.2 System register set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.3 Operation Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.3.1 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.3.2 Operation mode specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.4 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
3.4.1 CPU address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.4.2 Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
3.4.3 Wrap-around of CPU address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.5 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
3.5.1 Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
3.5.2 Recommended use of address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.5.3 Peripheral I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.5.4 Programmable peripheral I/O registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.6 Specific Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.6.1 Command Register (PRCMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3.6.2 Peripheral Command Register (PHCMD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.6.3 Peripheral Status Register (PHS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
3.6.4 Internal peripheral function wait control register (VSWC). . . . . . . . . . . . . . . . . . . 107
Chapter 4 Bus Control Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.2 Bus Control Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.3 Memory Block Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.3.1 Chip Select Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.4 Programmable peripheral I/O registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.5 Bus Cycle Type Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.5.1 Bus cycle type configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.6 Bus Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.6.1 Number of access clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.6.2 Bus sizing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.6.3 Endian control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.7 Cache Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.7.1 Bus width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.8 Wait Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4.8.1 Programmable wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

8Preliminary User’s Manual U15839EE1V0UM00
4.8.2 External wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
4.8.3 Relationship between programmable wait and external wait . . . . . . . . . . . . . . . .133
4.9 Idle State Insertion Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
4.10 Bus Priority Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
4.11 Boundary Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
4.11.1 Program space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
4.11.2 Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Chapter 5 Memory Access Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.1 SRAM, External ROM, External I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.1.2 SRAM connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
5.1.3 SRAM, external ROM, external I/O access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.2 Page ROM Controller (ROMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.2.2 Page ROM connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
5.2.3 On-page/off-page judgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
5.2.4 Page ROM configuration register (PRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
5.2.5 Page ROM access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
Chapter 6 Instruction Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
6.2.1 Four Kbytes 2-way set-associative Instruction Cache . . . . . . . . . . . . . . . . . . . . . 157
6.3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.4 Instruction Cache Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
6.5 Instruction Cache Initialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
6.6 Operating Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Chapter 7 DMA Functions (DMA Controller). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
7.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
7.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
7.2.1 DMA source address registers H0 to H3 (DSAH0 to DSAH3) . . . . . . . . . . . . . . .170
7.2.2 DMA destination address registers H0 to H3 (DDAH0 to DDAH3). . . . . . . . . . . .172
7.2.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3). . . . . . . . . . . . . . . . . . . . . .174
7.2.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) . . . . . . . . . . . . . . . 175
7.2.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3). . . . . . . . . . . . . . . . . .177
7.2.6 DMA disable status register (DDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
7.2.7 DMA restart register (DRST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
7.2.8 DMA trigger factor register 0 (DTFR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
7.2.9 DMA trigger factor register 1 (DTFR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
7.2.10 DMA trigger factor register 2 (DTFR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
7.2.11 DMA trigger factor register 3 (DTFR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
7.3 Next Address Setting Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
7.4 DMA Bus States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
7.4.1 Types of bus states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
7.4.2 DMAC bus cycle state transition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
7.5 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.5.1 Single transfer mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
7.5.2 Single-step transfer mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
7.5.3 Line Transfer Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
7.5.4 Block transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
7.6 Transfer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
7.6.1 Two-cycle transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
7.7 Transfer Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
7.7.1 Transfer type and transfer object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
7.8 DMA Channel Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
7.9 DMA Transfer Start Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

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7.10 Forcible Interruption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
7.11 Forcible Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
7.12 DMA Transfer Completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.12.1 DMA transfer end interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.12.2 Terminal count output upon DMA transfer end. . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.13 Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Chapter 8 Interrupt/Exception Processing Function . . . . . . . . . . . . . . . . . . . . . . . . . 199
8.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
8.2 Non-Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
8.2.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
8.2.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
8.2.3 Non-maskable interrupt status flag (NP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
8.2.4 Edge Detection Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
8.3 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
8.3.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
8.3.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
8.3.3 Priorities of maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
8.3.4 Interrupt control register (xxIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
8.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3). . . . . . . . . . . . . . . . . . . . . . . . . . . 219
8.3.6 In-service priority register (ISPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
8.3.7 Maskable interrupt status flag (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
8.4 Noise Elimination Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
8.4.1 Analog Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
8.4.2 Interrupt Trigger Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
8.4.3 Interrupt Edge Detection Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
8.5 Software Exception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
8.5.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
8.5.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
8.5.3 Exception status flag (EP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
8.6 Exception Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
8.6.1 Illegal opcode definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
8.6.2 Debug trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
8.7 Multiple Interrupt Processing Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
8.8 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
8.9 Periods in Which Interrupts Are Not Acknowledged. . . . . . . . . . . . . . . . . . . . . . . . . 237
Chapter 9 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
9.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
9.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
9.3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
9.3.1 Clock Control Register (CKC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
9.3.2 Clock Generator Status Register (CGSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
9.3.3 Watchdog Timer Clock Control Register (WCC). . . . . . . . . . . . . . . . . . . . . . . . . . 244
9.3.4 Processor Clock Control Register (PCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
9.3.5 Reset Source Monitor Register (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
9.3.6 SSCG Frequency Modulation Control Register (SCFMC) . . . . . . . . . . . . . . . . . . 248
9.3.7 SSCG Frequency Control Register 0 (SCFC0). . . . . . . . . . . . . . . . . . . . . . . . . . . 249
9.3.8 SSCG Frequency Control Register 1 (SCFC1). . . . . . . . . . . . . . . . . . . . . . . . . . . 250
9.4 Power Saving Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
9.4.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
9.4.2 Power Save Modes Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
9.4.3 Power Saving Mode Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
9.4.4 HALT mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
9.4.5 IDLE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
9.4.6 WATCH mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
9.4.7 SUB WATCH mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
9.4.8 Software STOP mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

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9.5 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
9.5.1 Power Save Control Register (PSC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268
9.5.2 Power Save Mode Register (PSM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
Chapter 10 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
10.1 Timer C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
10.1.1 Features (Timer C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
10.1.2 Function overview (Timer C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
10.1.3 Basic configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
10.1.4 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
10.1.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
10.1.6 Sub Oscillator Calibration Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
10.1.7 Precautions Timer C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
10.2 Timer D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
10.2.1 Features Timer D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
10.2.2 Function overview Timer Dn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
10.2.3 Basic configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
10.2.4 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301
10.2.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302
10.2.6 Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
10.2.7 Precautions for Timer Dn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
10.3 Timer G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
10.3.1 Features of Timer G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
10.3.2 Function overview of each Timer Gn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
10.3.3 Basic configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
10.3.4 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
10.3.5 Output delay operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
10.3.6 Explanation of basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
10.3.7 Operation in Free-run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
10.3.8 Match and clear mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
10.3.9 Edge noise elimination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
10.3.10Precautions Timer Gn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
Chapter 11 Watch Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
11.1 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
11.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350
11.3 Watch Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
11.4 Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
11.4.1 Selection of the Watch Timer Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
11.4.2 Control of the watch timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
11.4.3 Operation as interval timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354
Chapter 12 Watchdog Timer Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
12.1 Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
12.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
12.3 Watchdog Timer Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
12.4 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
12.4.1 Operating as watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
Chapter 13 Serial Interface Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
13.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
13.2 Asynchronous Serial Interfaces UART5n (UART50, UART51) . . . . . . . . . . . . . . . . . 364
13.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
13.2.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
13.2.3 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
13.2.4 Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
13.2.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
13.2.6 Dedicated baud rate generators (BRG) of UART5n (n = 0, 1) . . . . . . . . . . . . . . .384

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13.2.7 Precautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
13.3 Clocked Serial Interfaces (CSI00 to CSI02). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
13.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
13.3.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
13.3.3 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
13.3.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
13.3.5 Output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
13.3.6 Dedicated baud rate generators 0, 1 (BRG0, BRG1) . . . . . . . . . . . . . . . . . . . . . . 423
Chapter 14 FCAN Interface Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
14.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
14.2 Outline of the FCAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
14.2.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
14.2.2 CAN memory and register layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
14.2.3 Clock structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
14.2.4 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
14.2.5 Time stamp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
14.2.6 Message handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
14.2.7 Mask handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
14.2.8 Remote frame handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
14.3 Control and Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
14.3.1 Bit set/clear function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
14.3.2 Common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
14.3.3 CAN interrupt pending registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
14.3.4 CAN message buffer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
14.3.5 CAN Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
14.4 Operating Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
14.4.1 Rules to be observed for correct baud rate settings. . . . . . . . . . . . . . . . . . . . . . . 509
14.4.2 Example for baudrate setting of CAN module. . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
14.4.3 Ensuring data consistency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
14.4.4 Operating states of the CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
14.4.5 Initialisation routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
Chapter 15 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
15.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
15.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
15.3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
15.3.1 Register format of A/D Converter Control Register. . . . . . . . . . . . . . . . . . . . . . . . 527
15.3.2 Input voltage and conversion results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
15.4 Interrupt Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
15.5 A/D Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
15.5.1 A/D converter basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
15.5.2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
15.6 A/D Converter Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
15.7 How to read the A/D Converter Characteristics Table. . . . . . . . . . . . . . . . . . . . . . . . 542
Chapter 16 Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
16.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
16.2 Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
16.3 Pin Functions of Each Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
16.3.1 Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
16.3.2 Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
16.3.3 Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
16.3.4 Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
16.3.5 Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
16.3.6 Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
16.3.7 Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
16.3.8 Port 7/8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573

12 Preliminary User’s Manual U15839EE1V0UM00
16.3.9 Port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .574
16.3.10Port AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .575
16.3.11Port CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .577
16.3.12Port CT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .579
16.3.13Port CM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .581
Chapter 17 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
17.1 Reset Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
17.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
17.3 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .583
17.4 Reset by RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
17.5 Reset by Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
17.6 Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
17.7 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
Appendix A List of Instruction Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
Appendix B Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601

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Preliminary User’s Manual U15839EE1V0UM00
List of Figures
Figure 1-1: V850E/CA2 Jupiter Pin Configuration ......................................................................... 27
Figure 1-2: V850E/CA2 Jupiter Block Diagram ............................................................................. 29
Figure 2-1: Pin I/O Circuits ............................................................................................................ 54
Figure 3-1: CPU Register Set........................................................................................................ 56
Figure 3-2: Program Counter (PC) ................................................................................................ 57
Figure 3-3: Interrupt Source Register (ECR) ................................................................................. 59
Figure 3-4: Program Status Word (PSW) ...................................................................................... 60
Figure 3-5: CPU Address Space ................................................................................................... 65
Figure 3-6: Image on Address Space............................................................................................ 66
Figure 3-7: Wrap-around of Program Space .................................................................................67
Figure 3-8: Wrap-around of Data Space........................................................................................ 67
Figure 3-9: Memory Map (µPD703128 (A)) ................................................................................... 68
Figure 3-10: Memory Map (µPD703129 (A), µPD703129 (A1))....................................................... 69
Figure 3-11: Internal RAM Area of µPD703129............................................................................... 73
Figure 3-12: Internal RAM Area of µPD703128............................................................................... 73
Figure 3-13: Internal Peripheral I/O Area......................................................................................... 74
Figure 3-14: Example Application of wrap-around (µPD703129) .................................................... 75
Figure 3-15: Programmable Peripheral I/O Register (Outline)......................................................... 83
Figure 3-16: Peripheral Area Selection Control Register (BPC) ..................................................... 84
Figure 3-17: Command Register (PRCMD) Format....................................................................... 104
Figure 3-18: Peripheral Command Register (PHCMD) Format..................................................... 105
Figure 3-19: Peripheral Status Register (PHS) Format ................................................................. 106
Figure 3-20: Internal peripheral function wait control register (VSWC) Format............................. 107
Figure 4-1: Memory Block Function............................................................................................. 110
Figure 4-2: Chip Area Select Control Registers 0, 1 (1/2) ........................................................... 111
Figure 4-3: Programmable Peripheral I/O Register (Outline)....................................................... 113
Figure 4-4: Peripheral Area Selection Control Register (BPC)....................................................114
Figure 4-5: Big Endian Addresses within Word ........................................................................... 117
Figure 4-6: Little Endian Addresses within Word......................................................................... 117
Figure 4-7: Example of Wait Insertion ......................................................................................... 133
Figure 5-1: Example of Connection to SRAM.............................................................................. 138
Figure 5-2: SRAM, External ROM, External I/O Access Timing (1/6).......................................... 139
Figure 5-3: Example of Page ROM Connections......................................................................... 146
Figure 5-4: On-Page/Off-Page Judgment during Page ROM Connection (1/2)........................... 147
Figure 5-5: Page ROM Configuration Register (PRC) ................................................................ 149
Figure 5-6: Page ROM Access Timing (1/4)................................................................................ 150
Figure 6-1: Instruction Cache Configuration................................................................................ 156
Figure 6-2: Configuration of 4 KB 2-Way Set-Associative Instruction Cache.............................. 157
Figure 6-3: Instruction Cache Control Register (ICC) ................................................................. 158
Figure 6-4: Instruction Cache Data Configuration Register (ICD) ............................................... 159
Figure 6-5: Instruction Cache Initial Register (ICI) ...................................................................... 159
Figure 6-6: Operation on Instruction Cache Hit ........................................................................... 160
Figure 6-7: Operation on Instruction Cache Miss ........................................................................ 161
Figure 6-8: Refill Sequence to Instruction Cache (16-bit Data Bus)............................................ 162
Figure 6-9: iCache Area Setting Example ................................................................................... 168
Figure 7-1: DMA Source Address Registers DSAH0 to DSAH3 (DSAH0 to DSAH3) ................. 170
Figure 7-2: DMA Source Address Registers DSAL0 to DSAL3 (DSAL0 to DSAL3).................... 171
Figure 7-3: DMA Destination Address Registers 0H to 3H (DDA0H to DDA3H)......................... 172
Figure 7-4: DMA Destination Address Registers L0 to L3 (DDAL0 to DDAL3)............................ 173
Figure 7-5: DMA Transfer Count Registers 0 to 3 (DBC0 to DBC3)............................................ 174
Figure 7-6: DMA Addressing Control Registers 0 to 3 (DADC0 to DADC3) (1/2)........................ 175
Figure 7-7: DMA Channel Control Registers 0 to 3 (DCHC0 to DCHC3).................................... 177
Figure 7-8: DMA Disable Status Register (DDIS)........................................................................ 178
Figure 7-9: DMA Restart Register (DRST) .................................................................................. 178
Figure 7-10: DMA Trigger Factor Registers 0 (DTFR0) ................................................................ 179

14 Preliminary User’s Manual U15839EE1V0UM00
Figure 7-11: DMA Trigger Factor Registers 1 (DTFR1) ................................................................180
Figure 7-12: DMA Trigger Factor Registers 2 (DTFR2) ................................................................181
Figure 7-13: DMA Trigger Factor Registers 3 (DTFR3) ................................................................182
Figure 7-14: Buffer Register Configuration....................................................................................183
Figure 7-15: DMAC Bus Cycle State Transition Diagram..............................................................186
Figure 7-16: Single Transfer Example 1........................................................................................187
Figure 7-17: Single Transfer Example 2........................................................................................187
Figure 7-18: Single Transfer Example 3........................................................................................188
Figure 7-19: Single Transfer Example 4........................................................................................188
Figure 7-20: Single-Step Transfer Example 1................................................................................189
Figure 7-21: Single-Step Transfer Example 2................................................................................189
Figure 7-22: Line Transfer Example 1 ...........................................................................................190
Figure 7-23: Line Transfer Example 2 ...........................................................................................190
Figure 7-24: Line Transfer Example 3 ...........................................................................................191
Figure 7-25: Line Transfer Example 4 ...........................................................................................191
Figure 7-26: Block Transfer Example ............................................................................................ 192
Figure 7-27: Example of Forcible Interruption of DMA Transfer.................................................... 195
Figure 7-28: DMA Transfer Forcible Termination Example 1 ........................................................196
Figure 7-29: DMA Transfer Forcible Termination Example 2 ........................................................197
Figure 8-1: Example of Non-Maskable Interrupt Request Acknowledgement Operation (1/2)....204
Figure 8-2: Processing Configuration of Non-Maskable Interrupt................................................206
Figure 8-3: RETI Instruction Processing......................................................................................207
Figure 8-4: Non-maskable Interrupt Status Flag (NP) ................................................................208
Figure 8-5: Interrupt Mode Register 3 (INTM3)............................................................................ 208
Figure 8-6: Maskable Interrupt Processing..................................................................................210
Figure 8-7: RETI Instruction Processing......................................................................................211
Figure 8-8: Example of Processing in Which Another Interrupt Request Is Issued
While an Interrupt Is Being Processed (1/2)..............................................................213
Figure 8-9: Example of Processing Interrupt Requests Simultaneously Generated....................215
Figure 8-10: Interrupt Control Register (xxIC)................................................................................ 216
Figure 8-11: Interrupt Mask Registers 0 to 3 (IMR0 to IMR3) .......................................................219
Figure 8-12: In-Service Priority Register (ISPR)............................................................................220
Figure 8-13: Maskable Interrupt Status Flag (ID) ..........................................................................220
Figure 8-14: Port Interrupt Input Circuit (P52, P53, P61, P62, P63, P64)......................................221
Figure 8-15: Timer G Input Circuit (P30, P35, P40, P45, P54, P55)..............................................221
Figure 8-16: NMI Input Circuit........................................................................................................ 221
Figure 8-17: Interrupt Mode Register 0 (IMTM0) .........................................................................223
Figure 8-18: Interrupt Mode Register 1 (IMTM1) .........................................................................224
Figure 8-19: Interrupt Mode Register 2 (IMTM2) .........................................................................225
Figure 8-20: Interrupt Mode Register 3 (IMTM3)........................................................................... 226
Figure 8-21: Software Exception Processing.................................................................................227
Figure 8-22: RETI Instruction Processing......................................................................................228
Figure 8-23: Exception Status Flag (EP) ......................................................................................229
Figure 8-24: Exception Trap Processing........................................................................................230
Figure 8-25: Restore Processing from Exception Trap.................................................................. 231
Figure 8-26: Debug Trap Processing.............................................................................................232
Figure 8-27: Restore Processing from Debug Trap.......................................................................233
Figure 8-28: Pipeline Operation at Interrupt Request Acknowledgment (Outline).........................236
Figure 9-1: Block Diagram of the Clock Generator......................................................................240
Figure 9-2: Clock Control Register (CKC) (1/2)...........................................................................241
Figure 9-3: Clock Generator Status Register (CGSTAT).............................................................243
Figure 9-4: Watchdog Timer Clock Control Register (WCC).......................................................244
Figure 9-5: Processor Clock Control Register (PCC) (1/2) ......................................................... 245
Figure 9-6: Reset Source Monitor Register (RSM)...................................................................... 247
Figure 9-7: SSCG Frequency Modulation Control Register (SCFMC).........................................248
Figure 9-8: SSCG Frequency Control Register 0 (SCFC0)......................................................... 249
Figure 9-9: SSCG Frequency Control Register 1 (SCFC1)......................................................... 250
Figure 9-10: Power Save Mode State Transition Diagram ............................................................252

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Preliminary User’s Manual U15839EE1V0UM00
Figure 9-11: Sub Watch mode released by RESET input ............................................................. 263
Figure 9-12: Sub Watch mode release by Watchdog reset, NMI, INT........................................... 264
Figure 9-13: STOP mode released by RESET input ..................................................................... 266
Figure 9-14: STOP mode release by Watchdog reset, NMI, INT................................................... 267
Figure 9-15: Power Save Control Register (PSC) ........................................................................ 268
Figure 9-16: Power Save Mode Register (PSM) .......................................................................... 270
Figure 10-1: Block Diagram of Timer C ......................................................................................... 273
Figure 10-2: Timer C counter (TMC0) .......................................................................................... 274
Figure 10-3: Capture/Compare Register 0 (CCC00) ..................................................................... 276
Figure 10-4: Capture/Compare Register 1 (CCC01) ..................................................................... 276
Figure 10-5: Timer C control Register 0 (TMCC00) (1/2) ............................................................. 278
Figure 10-6: Timer C control Register 1 (TMCC01) (1/2) ............................................................. 280
Figure 10-7: Valid Edge Selection Register (SESC0).................................................................... 282
Figure 10-8: Timing of basic operation of Timer C ........................................................................ 283
Figure 10-9: Timing of interrupt operation after overflow...............................................................284
Figure 10-10: Timing of capture for pulse cycle measurement (rising edge)................................... 285
Figure 10-11: Timing of capture for pulse width measurement (both edges) .................................. 286
Figure 10-12: Timing of cycle measurement operation ................................................................... 288
Figure 10-13: Timing of compare operation..................................................................................... 289
Figure 10-14: Timing of interval timer operation.............................................................................. 290
Figure 10-15: Timing of PWM output operation (overview) ............................................................. 291
Figure 10-16: Timing of PWM output operation (detail)................................................................... 292
Figure 10-17: Multiplexed Inputs for Timer C Sub Oscillator Calibration Function.......................... 294
Figure 10-18: Block Diagram of Timer Dn (n = 0, 1)........................................................................ 296
Figure 10-19: Timer Dn counter register (TMDn) (n = 0, 1) ........................................................... 298
Figure 10-20: Timer Dn Compare Register (CMDn) (n = 0, 1) ........................................................ 299
Figure 10-21: Timing of Timer Dn Operation................................................................................... 300
Figure 10-22: Timer Dn Control Register (TMCDn) (n = 0, 1) ........................................................ 301
Figure 10-23: Timing of Compare Operation (1/2)........................................................................... 302
Figure 10-24: Block Diagram of Timer Gn....................................................................................... 308
Figure 10-25: Timer Gn Counter 0 Value Registers TMGn0 ........................................................... 310
Figure 10-26: Timer Gn Counter 1 Value Registers TMGn1 ........................................................... 310
Figure 10-27: Timer Gn counter TMGn0 assigned Capture/Compare Register (GCCn0)............... 311
Figure 10-28: Timer Gn counter TMGn1 assigned Capture/Compare Register (GCCn5)............... 311
Figure 10-29: Timer Gn free assignable Capture/Compare Registers (GCCnm) (m = 1 to 4) ........312
Figure 10-30: Timer Gn Mode Register (TMGMn) (1/2) .............................................................. 313
Figure 10-31: Timer Gn Mode Register Low (TMGMnL) ............................................................... 315
Figure 10-32: Timer Gn Mode Register Low (TMGMnH) ............................................................... 315
Figure 10-33: Timer Gn Channel Mode Register (TMGCMn).......................................................... 316
Figure 10-34: Timer Gn Channel Mode Register (TMGCMnL)........................................................ 317
Figure 10-35: Timer Gn Channel Mode Register (TMGCMnH)....................................................... 317
Figure 10-36: Timer Gn Output Control Register (OCTLGn)........................................................... 318
Figure 10-37: Timer Gn Output Control Register Low (OCTLGnL) ................................................. 319
Figure 10-38: Timer Gn Output Control Register High (OCTLGnH)................................................ 319
Figure 10-39: Timer Gn Status Register (TMGSTn)........................................................................ 320
Figure 10-40: Timing of Output delay operation .............................................................................. 321
Figure 10-41: Timing when both edges of TIGn0 are valid (free run).............................................. 326
Figure 10-42: Timing of capture trigger edge detection (free run)................................................... 327
Figure 10-43: Timing of starting capture trigger edge detection...................................................... 328
Figure 10-44: Timing of compare mode (free run)........................................................................... 329
Figure 10-45: Timing when GCCn1 is rewritten during operation (free run).................................... 330
Figure 10-46: Timing of PWM operation (free run).......................................................................... 332
Figure 10-47: Timing when 0000H is set in GCCnm (free run)........................................................ 333
Figure 10-48: Timing when FFFFH is set in GCCnm (free run)....................................................... 333
Figure 10-49: Timing when GCCnm is rewritten during operation (free run)................................... 334
Figure 10-50: Timing when both edges of TIGm are valid (match and clear).................................. 336
Figure 10-51: Timing of compare operation (match and clear)........................................................ 338
Figure 10-52: Timing when GCCnm is rewritten during operation (match and clear)...................... 339

16 Preliminary User’s Manual U15839EE1V0UM00
Figure 10-53: Timing of PWM operation (match and clear).............................................................341
Figure 10-54: Timing when 0000H is set in GCCnm (match and clear) ..........................................342
Figure 10-55: Timing when the same value as set in GCCn0/GCCn5 is set in GCCnm
(match and clear)....................................................................................................... 343
Figure 10-56: Timing when the value of GCCnm exceeding GCCn0 or GCCn5
(match and clear)....................................................................................................... 344
Figure 10-57: Timing when GCCnm is rewritten during operation (match and clear)...................... 345
Figure 10-58: Timing of Edge detection noise elimination...............................................................346
Figure 11-1: Block Diagram of Watch Timer..................................................................................349
Figure 11-2: Watch Timer Mode Control Register (WTM) (1/2)..................................................... 350
Figure 11-3: Operation Timing of Watch Timer/Interval Timer....................................................... 355
Figure 12-1: Block Diagram of Watchdog Timer............................................................................357
Figure 12-2: Watchdog Timer Clock Selection Register (WDCS)..................................................359
Figure 12-3: Watchdog Timer Mode Register (WDTM) ................................................................360
Figure 12-4: Watchdog Timer Mode Register (WCMD) ................................................................361
Figure 12-5: Watchdog Timer Mode Register (WPHS) .................................................................361
Figure 13-1: Asynchronous Serial Interfaces Block Diagram ........................................................ 366
Figure 13-2: Asynchronous Serial Interface Mode Registers (ASIM0, ASIM1) (1/3)..................... 367
Figure 13-3: Asynchronous Serial Interface Status Registers (ASIS0, ASIS1) ............................. 370
Figure 13-4: Asynchronous Serial Interface Transmit Status Registers (ASIF0, ASIF1)...............371
Figure 13-5: Reception Buffer Registers (RXB0, RXB1) ...............................................................372
Figure 13-6: Transmission Buffer Registers (TXB0, TXB1)........................................................... 373
Figure 13-7: Asynchronous Serial Interface Transmit/Receive Data Format.................................375
Figure 13-8: Asynchronous Serial Interface Transmission Completion Interrupt Timing............... 376
Figure 13-9: Continuous Transmission Starting Procedure........................................................... 378
Figure 13-10: Continuous Transmission End Procedure.................................................................379
Figure 13-11: Asynchronous Serial Interface Reception Completion Interrupt Timing....................380
Figure 13-12: When Reception Error Interrupt Is Separated from INTSRn Interrupt
(ISRM Bit = 0)............................................................................................................381
Figure 13-13: When Reception Error Interrupt Is Included in INTSRn Interrupt
(ISRM Bit = 1)............................................................................................................381
Figure 13-14: Noise Filter Circuit..................................................................................................... 383
Figure 13-15: Timing of RXD5n Signal Judged as Noise ................................................................383
Figure 13-16: Baud Rate Generator (BRG) Configuration of UART5n (n = 0, 1) ............................384
Figure 13-17: Clock Select Registers (CHKSR0, CHKSR1)............................................................385
Figure 13-18: Baud Rate Generator Control Registers (BRGC0, BRGC1) .....................................386
Figure 13-19: Allowable Baud Rate Range During Reception......................................................... 389
Figure 13-20: Transfer Rate During Continuous Transmission .......................................................391
Figure 13-21: Block Diagram of Clocked Serial Interfaces..............................................................394
Figure 13-22: Clocked Serial Interface Mode Registers (CSIM0 to CSIM2).................................... 395
Figure 13-23: Clocked Serial Interface Clock Selection Registers (CSIC0 to CSIC2) (1/2) ............396
Figure 13-24: Clocked Serial Interface Reception Buffer Registers (SIRB0 to SIRB2)................... 398
Figure 13-25: Clocked Serial Interface Reception Buffer Registers Low (SIRBL0 to SIRBL2)........399
Figure 13-26: Clocked Serial Interface Read-Only Reception Buffer Registers
(SIRBE0 to SIRBE2).................................................................................................. 400
Figure 13-27: Clocked Serial Interface Read-Only Reception Buffer Registers Low
(SIRBEL0 to SIRBEL1)..............................................................................................401
Figure 13-28: Clocked Serial Interface Transmission Buffer Registers (SOTB0 to SOTB2)...........402
Figure 13-29: Clocked Serial Interface Transmission Buffer Registers Low
(SOTBL0 to SOTBL2)................................................................................................403
Figure 13-30: Clocked Serial Interface Initial Transmission Buffer Registers
(SOTBF0 to SOTBF2)...............................................................................................404
Figure 13-31: Clocked Serial Interface Initial Transmission Buffer Registers Low
(SOTBFL0 to SOTBFL2)...........................................................................................405
Figure 13-32: Serial I/O Shift Registers (SIO0 to SIO2) ..................................................................406
Figure 13-33: Serial I/O Shift Registers Low (SIOL0 to SIOL2).......................................................407
Figure 13-34: Timing Chart in single Transfer Mode (1/2)...............................................................409
Figure 13-35: Timing Chart According to Clock Phase Selection (1/2)............................................411

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Preliminary User’s Manual U15839EE1V0UM00
Figure 13-36: Timing Chart of Interrupt Request Signal Output in Delay Mode (1/2)...................... 413
Figure 13-37: Repeat Transfer (Receive-Only) Timing Chart.......................................................... 415
Figure 13-38: Repeat Transfer (Transmission/Reception) Timing Chart......................................... 417
Figure 13-39: Timing Chart of Next Transfer Reservation Period (1/2)........................................... 418
Figure 13-40: Transfer Request Clear and Register Access Contention.........................................420
Figure 13-41: Interrupt Request and Register Access Contention .................................................. 421
Figure 13-42: Baud Rate Generators 0, 1 (BRG0, BRG1) Block Diagram...................................... 423
Figure 13-43: Prescaler Mode Registers 0, 1 (PRSM0, PRSM1).................................................... 424
Figure 13-44: Prescaler Compare Registers 0, 1 (PRSCM0, PRSCM1).........................................425
Figure 14-1: Functional Blocks of the FCAN Interface .................................................................. 428
Figure 14-2: Memory Area of the FCAN System........................................................................... 429
Figure 14-3: Clock Structure of the FCAN System........................................................................ 438
Figure 14-4: FCAN Interrupt Bundling of V850E/CA2 ................................................................... 439
Figure 14-5: Time Stamp Capturing at Message Reception.......................................................... 441
Figure 14-6: Time Stamp Capturing at Message Transmission..................................................... 442
Figure 14-7: 16-Bit Data Write Operation for Specific Registers .................................................. 453
Figure 14-8: CAN Stop Register (CSTOP) ................................................................................... 454
Figure 14-9: CAN Main Clock Select Register (CGSC) (1/2)......................................................... 455
Figure 14-10: Configuration of FCAN System Main Clock............................................................... 456
Figure 14-11: Configuration of FCAN Global Time System Clock................................................... 456
Figure 14-12: CAN Global Status Register (CGST) (1/3) .............................................................. 457
Figure 14-13: CAN Global Interrupt Enable Register (CGIE) (1/2) ................................................. 460
Figure 14-14: CAN Timer Event Enable Register (CGTEN) .......................................................... 462
Figure 14-15: CAN Global Time System Counter and event generation......................................... 462
Figure 14-16: CAN Global Time System Counter (CGTSC) ........................................................... 463
Figure 14-17: CAN Message Search Start Register (CGMSS) ...................................................... 464
Figure 14-18: CAN Message Search Result Register (CGMSR) .................................................... 465
Figure 14-19: CAN Test Bus Register (CTBR) ............................................................................... 466
Figure 14-20: Internal CAN Test Bus Structure............................................................................... 466
Figure 14-21: CAN Interrupt Pending Registers (CCINTPL, CCINTPH) ........................................ 467
Figure 14-22: CAN Global Interrupt Pending Register (CGINTP) (1/2) ......................................... 468
Figure 14-23: CAN 1 to 4 Interrupt Pending Registers (C1INTP to C4INTP) (1/2) ....................... 470
Figure 14-24: Message Identifier Registers L00 to L31 and H00 to H31
(M_IDL00 to M_IDL31, M_IDH00 to M_IDH31) ....................................................... 472
Figure 14-25: Message Configuration Registers 00 to 31 (M_CONF00 to M_CONF31) (1/2) ....... 473
Figure 14-26: Message Status Registers 00 to 31 (M_STAT00 to M_STAT31) ............................. 475
Figure 14-27: Message Set/Clear Status Registers 00 to 31 (SC_STAT00 to SC_STAT31) .........477
Figure 14-28: Message Data Registers m0 to m7
(M_DATAm0 to M_DATAm7) (m = 00 to 31) (1/2) ................................................... 478
Figure 14-29: Message Data Length Code Registers 00 to 31 (M_DLC00 to M_DLC31) .............. 480
Figure 14-30: Message Control Registers 00 to 31 (M_CTRL00 to M_CTRL31) (1/2) ................... 481
Figure 14-31: Message Time Stamp Registers 00 to 31 (M_TIME00 to M_TIME31)...................... 483
Figure 14-32: Message Event Registers m0, m1, and m3
(M_EVTm0, M_EVTm1, M_EVTm2, M_EVTm3) (m = 00 to 31) .............................. 484
Figure 14-33: CAN 1 to 4 Mask 0 to 3 Registers L, H
(CxMASKL0 to CxMASKL3, CxMASKH0 to CxMASKH3) (x = 1 to 4) ................... 485
Figure 14-34: CAN 1 to 4 Control Registers (C1CTRL to C4CTRL) (1/5) ..................................... 487
Figure 14-35: CAN 1 to 4 Definition Registers (C1DEF to C4DEF) (1/4) ...................................... 492
Figure 14-36: CAN 1 to 4 Information Registers (C1LAST to C4LAST) ......................................... 496
Figure 14-37: CAN 1 to 4 Error Counter Registers (C1ERC to C4ERC) ........................................ 497
Figure 14-38: CAN 1 to 4 Interrupt Enable Registers (C1IE to C4IE) (1/3) ................................... 498
Figure 14-39: CAN 1 to 4 Bus Activity Registers (C1BA to C4BA) (1/2) ........................................ 501
Figure 14-40: CAN 1 to 4 Bit Rate Prescaler Registers (C1BRP to C4BRP) (1/2) ......................... 503
Figure 14-41: CAN Bus Bit Timing................................................................................................... 505
Figure 14-42: CAN 1 to 4 Synchronization Control Registers (C1SYNC to C4SYNC) (1/2)) .......... 506
Figure 14-43: CAN 1 to 4 Bus Diagnostic Information Registers (C1DINF to C4DINF) ................. 508
Figure 14-44: Sequential CAN Data Read by CPU ......................................................................... 512
Figure 14-45: State Transition Diagram for CAN Modules .............................................................. 514

18 Preliminary User’s Manual U15839EE1V0UM00
Figure 14-46: General Initialisation Sequence for the CAN Interface..............................................515
Figure 14-47: Initialisation Sequence for a CAN module.................................................................517
Figure 14-48: Setting CAN Module into Initialisation State..............................................................519
Figure 15-1: Block Diagram of A/D Converter ...............................................................................526
Figure 15-2: A/D Converter Mode Register (ADM) .......................................................................528
Figure 15-3: A/D Converter Register (ADS) ................................................................................. 530
Figure 15-4: A/D Conversion Result Register (ADCR) .................................................................531
Figure 15-5: A/D Conversion Result Register (ADCRL) ...............................................................531
Figure 15-6: A/D Conversion Result Register (ADCRH) ...............................................................532
Figure 15-7: Port Function Register (PORT7/PORT8) .................................................................533
Figure 15-8: Port Function Register 7 (PORT7) ...........................................................................534
Figure 15-9: Relation between Analog Input Voltage and A/D Conversion Result........................536
Figure 15-10: No write operation is made to ADM or ADS register
during A/D conversion operation...............................................................................538
Figure 15-11: ADCS bit is cleared (0) during A/D conversion operation..........................................539
Figure 15-12: A write operation is made to the ADS register during A/D conversion operation......540
Figure 15-13: Analog Input Pin Handling.........................................................................................541
Figure 15-14: Overall Error.............................................................................................................. 542
Figure 15-15: Quantization Error .....................................................................................................543
Figure 15-16: Zero-Scale Error........................................................................................................543
Figure 15-17: Full-Scale Error..........................................................................................................544
Figure 15-18: Nonlinearity Error.......................................................................................................544
Figure 16-1: Port Configuration......................................................................................................546
Figure 16-2: Type A Block Diagram............................................................................................... 551
Figure 16-3: Type B Block Diagram............................................................................................... 552
Figure 16-4: Type C Block Diagram............................................................................................... 553
Figure 16-5: Type D Block Diagram............................................................................................... 554
Figure 16-6: Type E Block Diagram............................................................................................... 555
Figure 16-7: Port 1 (P1) ............................................................................................................... 556
Figure 16-8: Port 1 Mode Register (PM1) ....................................................................................557
Figure 16-9: Port 1 Mode Control Register (PMC1) ......................................................................558
Figure 16-10: Port 2 (P2) ............................................................................................................... 559
Figure 16-11: Port 2 Mode Register (PM2) ....................................................................................560
Figure 16-12: Port 2 Mode Control Register (PMC2) .....................................................................561
Figure 16-13: Port 3 (P3) ............................................................................................................... 562
Figure 16-14: Port 3 Mode Register (PM3) ....................................................................................563
Figure 16-15: Port 3 Mode Control Register (PMC3) .....................................................................563
Figure 16-16: Port 4 (P4) ............................................................................................................... 564
Figure 16-17: Port 4 Mode Register (PM4) ....................................................................................565
Figure 16-18: Port 4 Mode Control Register (PMC4) .....................................................................565
Figure 16-19: Port 5 (P5) ............................................................................................................... 566
Figure 16-20: Port 5 Mode Register (PM5) ....................................................................................567
Figure 16-21: Port 5 Mode Control Register (PMC5) .....................................................................568
Figure 16-22: Port 6 (P6) ............................................................................................................... 569
Figure 16-23: Port 6 Mode Register (PM6) ....................................................................................570
Figure 16-24: Port 6 Mode Control Register (PMC6) ......................................................................571
Figure 16-25: Port Function Register 7 (P7) ...................................................................................572
Figure 16-26: Port Function Register 7/8 (P7/P8) ...........................................................................573
Figure 16-27: Port 9 (P9) ............................................................................................................... 574
Figure 16-28: Port 9 Mode Register (PM9) ....................................................................................574
Figure 16-29: Port AH (PAH) .........................................................................................................575
Figure 16-30: Port AH Mode Register (PMAH) .............................................................................. 576
Figure 16-31: Port AH Mode Control Register (PMCAH) ...............................................................576
Figure 16-32: Port CS (PCS) .........................................................................................................577
Figure 16-33: Port CS Mode Register (PMCS) ..............................................................................578
Figure 16-34: Port CS Mode Control Register (PMCCS) ...............................................................578
Figure 16-35: Port CT (PCT) ..........................................................................................................579
Figure 16-36: Port CT Mode Register (PMCT) ..............................................................................580

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Preliminary User’s Manual U15839EE1V0UM00
Figure 16-37: Port CT Mode Control Register (PMCCT) ............................................................... 580
Figure 16-38: Port CM (PCM) ........................................................................................................ 581
Figure 16-39: Port CM Mode Register (PMCM) ............................................................................. 582
Figure 16-40: Port CM Mode Control Register (PMCCM) ............................................................. 582
Figure 17-1: Reset signal acknowledgment................................................................................... 585
Figure 17-2: Reset at power-on..................................................................................................... 586
Figure A-1: How to Read Instruction Set List............................................................................... 589

20 Preliminary User’s Manual U15839EE1V0UM00