Cypress Traveo S6J32E Series User manual

S6J32E, S6J32F, S6J32G Series
32-bit Microcontroller TraveoDatasheet
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-10689 Rev *H Revised December 13, 2017
The S6J32E, S6J32F, and S6J32G series is an extension of the existing S6J3200 series with 4-MB Flash, 512-KB RAM, and
Ethernet RMII support.
The S6J3200 series microcontrollers are members of the 55-nm Traveo™family targeting Cluster and Head-Up Display (HUD).
They are built as a single-chip solution to drive a complete mid-range instrument cluster. They can control up to six gauges and
drive up to two Thin Film Transistor (TFT) displays with WVGA resolution (854 × 480 pixels each). For connecting a HUD, one
display output can be warped on-the-fly for the necessary correction of the windshield bulge. A powerful 2.5D graphics engine
enables the device to be used for many mid-range graphics applications.
Features
Key Features
240-MHz Arm®Cortex®R5F CPU
4-MB internal high-speed Flash memory, 512-KB RAM
Supports 2.7 V to 5.5 V and 2.7 V to 3.6 V I/O supply voltage
1.2-V core power supply
50-channel 12-bit SAR A/D converter with 1-Msps
conversion rate
Embedded 4-channel CAN FD controller
12-channel Multi-Function Serial (MFS) communication block
Optional Ethernet AVB with MII and RMII interface
Two-channel DDR HSSPI
Optional HyperBus™ interface
Optional Media-LB (MOST25) interface
Six-channel Stepper Motor Controller
Enhanced sound function for high quality
2D/2.5D graphics subsystem with video capture, 2-MB
VRAM, dual-display support, on-the-fly-warping
Optional embedded Secure Hardware Extension (SHE) with
AES-128 encryption and decryption
Flash memory retention time up to 20 years
ASIL-B support on ISO26262 specification
256-pin, 216-pin, and 208-pin TEQFP packages
Power domain control
Applications
Automotive cluster application
Classic Cluster Control
Head-Up Display

Document Number: 002-10689 Rev *H Page 2 of 166
S6J32E, S6J32F, S6J32G Series
Table of Contents
1. Overview............................................................................................................................................................................ 4
1.1 Microcontroller Support Information............................................................................................................................... 4
1.2 Related Documents ....................................................................................................................................................... 4
2. Function List ..................................................................................................................................................................... 5
2.1 Function List Table......................................................................................................................................................... 5
2.2 Optional Function........................................................................................................................................................... 7
2.2.1 Basic Option................................................................................................................................................................... 7
2.2.2 ID................................................................................................................................................................................... 9
2.2.3 Restriction.................................................................................................................................................................... 10
3. Product Description........................................................................................................................................................ 12
3.1 Overview...................................................................................................................................................................... 12
3.2 Product Description...................................................................................................................................................... 12
3.2.1 Ethernet ....................................................................................................................................................................... 17
4. Package and Pin Assignment........................................................................................................................................ 20
4.1 Pin Assignment............................................................................................................................................................ 20
4.1.1 TEQFP-208.................................................................................................................................................................. 21
4.1.2 TEQFP-216.................................................................................................................................................................. 22
4.1.3 TEQFP-256.................................................................................................................................................................. 23
4.2 Package Dimensions ................................................................................................................................................... 24
4.2.1 TEQFP-208.................................................................................................................................................................. 24
4.2.2 TEQFP-216.................................................................................................................................................................. 25
4.2.3 TEQFP-256.................................................................................................................................................................. 26
5. I/O Circuit Type ............................................................................................................................................................... 27
5.1 I/O Circuit Type............................................................................................................................................................ 27
6. Port Description.............................................................................................................................................................. 34
6.1 Port Description List..................................................................................................................................................... 34
6.2 Remark ........................................................................................................................................................................ 54
7. Precautions and Handling Devices ............................................................................................................................... 54
7.1 Handling Precautions................................................................................................................................................... 54
7.1.1 Precautions for Product Design ................................................................................................................................... 54
7.1.2 Precautions for Package Mounting.............................................................................................................................. 55
7.1.3 Precautions for Use Environment ................................................................................................................................ 56
7.2 Handling Devices......................................................................................................................................................... 57
8. Electric Characteristics.................................................................................................................................................. 59
8.1 Absolute Maximum Rating........................................................................................................................................... 59
8.2 Operation Assurance Condition................................................................................................................................... 63
8.3 DC Characteristics....................................................................................................................................................... 68
8.3.1 Port Function Characteristics....................................................................................................................................... 68
8.3.2 Power Supply Current.................................................................................................................................................. 74
8.4 AC Characteristics....................................................................................................................................................... 77
8.4.1 Source Clock Timing.................................................................................................................................................... 77
8.4.2 Sub Clock Timing......................................................................................................................................................... 78
8.4.3 Internal Clock Timing ................................................................................................................................................... 78
8.4.4 Reference voltages for AC characteristics of I/O cells................................................................................................. 82
8.4.5 Reset Input................................................................................................................................................................... 83
8.4.6 Power-On Conditions................................................................................................................................................... 84

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S6J32E, S6J32F, S6J32G Series
8.4.7 Multi-Function Serial .................................................................................................................................................... 87
8.4.8 Timer Input................................................................................................................................................................. 109
8.4.9 Trigger Input............................................................................................................................................................... 110
8.4.10 NMI Input ................................................................................................................................................................... 111
8.4.11 Low-Voltage Detection............................................................................................................................................... 111
8.4.12 High Current Output Slew Rate.................................................................................................................................. 117
8.4.13 Display Controller....................................................................................................................................................... 118
8.4.14 Video Capture............................................................................................................................................................ 121
8.4.15 FPD-Link (LVDS)....................................................................................................................................................... 122
8.4.16 DDR-HSSPI............................................................................................................................................................... 126
8.4.17 HyperBus................................................................................................................................................................... 130
8.4.18 Ethernet AVB............................................................................................................................................................. 134
8.4.19 MediaLB..................................................................................................................................................................... 137
8.4.20 Port Noise Filter......................................................................................................................................................... 138
8.5 A/D Converter............................................................................................................................................................ 145
8.5.1 Electrical Characteristics............................................................................................................................................ 145
8.5.2 Notes on A/D Converters........................................................................................................................................... 147
8.5.3 Glossary..................................................................................................................................................................... 147
8.5.4 Calibration Condition.................................................................................................................................................. 147
8.6 Audio DAC................................................................................................................................................................. 150
8.6.1 Electrical Characteristics............................................................................................................................................ 150
8.7 Flash Memory............................................................................................................................................................ 153
8.7.1 Electrical Characteristics............................................................................................................................................ 153
8.7.2 Notes ......................................................................................................................................................................... 153
9. Abbreviation.................................................................................................................................................................. 154
10.Ordering Information .................................................................................................................................................... 156
11.Appendix........................................................................................................................................................................ 157
11.1 Application 1: JTAG Tool Connection........................................................................................................................ 157
Sales, Solutions, and Legal Information........................................................................................................................... 166

Document Number: 002-10689 Rev *H Page 4 of 166
S6J32E, S6J32F, S6J32G Series
1. Overview
1.1 Microcontroller Support Information
http://www.cypress.com/products/cypress-traveo-family-32-bit-arm-cortex-r5-core-based-microcontrollers
1.2 Related Documents
The following table lists the related documents for the S6J32E, S6J32F, and S6J32G series.
Table 1-1 Related Documents
Document Type
Definition
Primary User
Document #
S6J3200 Series,
Datasheet
Specifies the function and its
characteristics quantitatively.
Investigator and hardware
engineer
002-05682
S6J32E, S6J32F,
S6J32G Series
Hardware Manual
Describes the function and
operation of the S6J3200 series.
Software engineer
002-12500
Traveo™Platform
Hardware Manual
Describes the function and
operation of the CPU core
platform.
Software engineer
002-04854
Supplementary
Datasheet
Supplementary information for
document, such as differences
with the previous revision.
Datasheet user
NA
Supplementary
Hardware manual
Supplementary information for
document, such as differences
with the previous revision.
Hardware manual user.
NA
Application notes
Explanation of the reference
software, sample application, the
reference board design, and so
on.
Software and hardware
engineer
AN209861 Getting Started with the
Traveo Family S6J3200 Series
For more application notes, visit
http://www.cypress.com
Notes:
−Refer to al l the documents for system development.
−The "primary user" is most likely the engineer who will find the document useful.
−The description of the datasheet and the S6J3200 hardware manual should precede the duplicated description of Traveo
platform hardware manual.
−The Traveo platform hardware manual is expected to be used as a dictionary of platform specification.
−Document code usually includes its revision.
−Information from the previous revision can be seen in the supplementary documents.

Document Number: 002-10689 Rev *H Page 5 of 166
S6J32E, S6J32F, S6J32G Series
2. Function List
2.1 Function List Table
The following table shows the functions implemented in the S6J32E, S6J32F, and S6J32G series.
Table 2-1 Function List
Function
Description
Remark
CPU core
Arm Cortex R5F
FPU
Available
(Double precision and Single precision)
PPU
Available
MPU
Available
TPU
Available
Endian
Little endian
Core clock frequency
Option
See 2.2.1 and AC
Characteristics.
HPM bus frequency
Option
See AC Characteristics
Resource clock frequency
Option
See AC Characteristics
Embedded CR oscillation
Slow clock:100 kHz, Fast clock: 4 MHz (Center frequency)
See AC Characteristics
PLL
PLL0, 1, 2, 3
SSCG PLL
SSCG0, 1, 2, 3
Clock supervisor
Available
DMA
16 ch
Boot-ROM
16 KB
JTAG
Available
Data cache
16 KB
Instruction cache
16 KB
Program FLASH
4160 KB
Work FLASH
112 KB
TC-RAM
128 KB
System-RAM
384 KB
Backup-RAM
16 KB
Security (SHE)
Option
See 2.2.1
Low latency interrupt
Available
Power domain
5 domains
Power supply
5 V ± 0.5 V, 3.3 V ± 0.3 V, 1.2 V ± 0.1 V
Embedded LDO power supply for 5.0 V
Available
Low-voltage detection of external power
supply
Available
Low-voltage detection of internal LDO
output
Available
Hardware watchdog timer
Available
Software watchdog timer
Available
Package
Option
See 2.2.1
AUTOSAR
AUTOSAR 4.0.3
GPIO
Option
See 2.2.3
Quad Position and Revolution Counter
2 ch
I/O timer
3 units x 8 ch
32-bit Reload timer
14 ch
Real time clock
Available
Automatic calibration
Sound generator
4 ch
Sound waveform generator
Option
1 unit x 5 outputs
See 2.2.1
Sound mixer
Option
1 unit x 10 inputs
See 2.2.1
Stereo audio DAC
Option
1 unit (L and R)
See 2.2.1
PCM-PWM
Option
1 unit (L and R)
See 2.2.1
Base timer
12 units (24ch)

Document Number: 002-10689 Rev *H Page 6 of 166
S6J32E, S6J32F, S6J32G Series
Function
Description
Remark
Free-run timer
12 ch
Input Capture Unit
12 units (24 channels of capture)
Output Compare Unit
12units (24 channels of compare match)
Stepping motor controller (SMC)
For 6 gauges
12-bit A/D converter
1 unit x 50 input ports (Max)
See 2.2.3
CRC
4 units
Programmable CRC
1 unit
Source clock timer
4 ch
NMI
Available
External interrupt
16 ch
Internal interrupt
512 vectors
I2S
2 ch
One only supports an
output as a function of the
sound system.
DDR HSSPI
2 ch
A type of Quad SPI
HyperBus (RPC2)
Option
See 2.2.1
Multi-function serial interface
12 ch
CAN-FD
4 ch
CAN-FD RAM (ECC supported)
16 KB/ch
Equivalent to 128 message buffers per CAN-FD channel
Ethernet AVB
1 ch
MII-Interface and RMII
Interface
Media-LB (MOST25)
1 ch
Indicator PWM
1 ch
MPU for AHB
1 unit
MPU for AXI
1 unit
Internal VRAM
2 MB
Graphic engine clock
200 MHz
Graphic AXI clock
200 MHz
Display clock
64 MHz (ch.0), 50 MHz(ch.1)
Display clock source
Graphic display controller clock or external clock
Target frame rate
60 fps
Number of display outputs
Maximum 2 outputs simultaneously
See 2.2.1
TTL output (RGB888)
2 ch
Display channel ch.0
Display channel ch.1
RSDS/TCON support
1 output
Display channel ch.0
FPD-Link (LVDS)
1 output, 350 Mbps (Max)
Display channel ch.0
Display channel ch.1
Video capture unit
1 ch
Video capture format
ITU656, YCbCr4:4:4, YCbCr4:2:2, RGB888, RGB666
2D Graphic engine
1 unit
2.5D support
Available
Vector drawing on 2D engine
Available
Warping
Available
Scale/Rotate/Blend
Available
2D Driver API
Cypress proprietary
Notes:
−The options are described in Section 2.2.
−The specifications related to the electric characteristics in the table only show the typical values. They do not necessarily
include the width of characteristics, errors, and so on. For details, refer to the electrical characteristics sections in this
document.
−Target resolution of graphics is WVGA 800 × 480, WQVGA 480 × 272.
−Target capture resolution of graphics is WVGA 800 × 480.

Document Number: 002-10689 Rev *H Page 7 of 166
S6J32E, S6J32F, S6J32G Series
2.2 Optional Function
2.2.1 Basic Option
The following figure shows the optional function and the part number relations of the combined S6J3200 and S6J32E, S6J32F,
S6J32G Series.
Figure 2-1: Option and Part Number
S 6 J 3 2 0 0 H A A x x x x x x x x
Ordering options 7 digit
Revision
Digit
M
2nd revision, fixed FL0023 1)
N
3rd revision, added alternative location for RXDVon P5_27, fixed FL0027 1)
Option
Digit SHE
Flash Chip
erase
SON
UOFF
TON
VOFF
Pin count
Digit Pin count
K 208 pin
L 216 pin
M 256 pin
Memorysize
Digit Program FLASH Work FLASH TC-RAM VRAM
E 4160KB 112KB 128KB 2048KB
Function
See the function digit table.
Product series
Digit Product type
2 Graphic SoC
Identifier: Automotive MCU
1) Please contact your Cypress sales representative to receive the customer information CI708-00001
2) controlled byChip erase enable marker MK_CEER
Description
Enabled
controlled by
MK_CEER 2)

Document Number: 002-10689 Rev *H Page 8 of 166
S6J32E, S6J32F, S6J32G Series
Table 2-2: Function Digit Table
Part Number
S6J32X
(X = function digit)
Function Digit
E
F
G
CPU Clock Maximum (MHz)
240
240
240
Graphics Clock Maximum (MHz)
200
200
200
Display Output Support (ch. no.)
0, 1
0, 1
0, 1
Video Capture Support (units)
1
1
1
Graphic Engine Type
2D
2D
2D
Hyper Bus Interface (ch. no.)
0, 1
0, 1
0, 1, 2
Sound System
OFF
ON
ON
Notes:
−This table only shows the relations between the optional function and the part numbers. That is, all products are not
necessarily available for orders. See the order number on the datasheet and confirm actual availability of products.
−The sound system is composed of the sound waveform generator, the sound mixer, the audio DAC, PCM-PWM, and I2S0.
−The CLK_CPU is assigned to the CPU clock. The CLK_CD3A0 is assigned to the graphic clock. They are defined in the Clock
Configuration chapter.

Document Number: 002-10689 Rev *H Page 9 of 166
S6J32E, S6J32F, S6J32G Series
2.2.2 ID
Each function digit has an ID and revision, which is defined in Figure 2-1.
Chip ID can be read from SYSC0_SYSIDR. For SYSC0_SYSIDR (see the Traveo™Platform hardware manual).
Function
Digit
Memory
Pin Count
Option
Revision
Chip ID
JTAG ID
E
E
K
S
M
0x10150001
0x101035CF
T
0x1010B5CF
U
0x101135CF
V
0x1011B5CF
L
S
0x101015CF
T
0x101095CF
U
0x101115CF
V
0x101195CF
F
K
S
0x101055CF
T
0x1010D5CF
U
0x101155CF
V
0x1011D5CF
L
S
0x101045CF
T
0x1010C5CF
U
0x101145CF
V
0x1011C5CF
G
K
S
0x101025CF
T
0x1010A5CF
U
0x101125CF
V
0x1011A5CF
L
S
0x101005CF
T
0x101085CF
U
0x101105CF
V
0x101185CF
M
S
0x101065CF
T
0x1010E5CF
U
0x101165CF
V
0x1011E5CF

Document Number: 002-10689 Rev *H Page 10 of 166
S6J32E, S6J32F, S6J32G Series
Function
Digit
Memory
Pin Count
Option
Revision
Chip ID
JTAG ID
E
E
K
S
N
0x10150002
0x201035CF
T
0x2010B5CF
U
0x201135CF
V
0x2011B5CF
L
S
0x201015CF
T
0x201095CF
U
0x201115CF
V
0x201195CF
F
K
S
0x201055CF
T
0x2010D5CF
U
0x201155CF
V
0x2011D5CF
L
S
0x201045CF
T
0x2010C5CF
U
0x201145CF
V
0x2011C5CF
G
K
S
0x201025CF
T
0x2010A5CF
U
0x201125CF
V
0x2011A5CF
L
S
0x201005CF
T
0x201085CF
U
0x201105CF
V
0x201185CF
M
S
0x201065CF
T
0x2010E5CF
U
0x201165CF
V
0x2011E5CF
Note:
−The JTAG-ID is stored in a memory in the PD2. It can only be read after device startup (VCC12 must be supplied and RSTX
must be released).
2.2.3 Restriction
Some functions have restrictions depending on package pin counts.

Document Number: 002-10689 Rev *H Page 11 of 166
S6J32E, S6J32F, S6J32G Series
Table 2-3: Pin Function Restrictions
Function
TEQFP-256
TEQFP-216
TEQFP-208
Analog input port
(12bit-ADC)
AN0 to AN49
(50 ports available)
AN0 to AN49
(50 ports available)
AN1 to AN3, AN5 to AN17,
AN20 to AN49
(46 ports )
GPIO
P0_00, P0_01, P0_02, P0_03,
P0_04, P0_05, P0_06, P0_07,
P0_08, P0_09, P0_10, P0_11,
P0_12, P0_13, P0_14, P0_15,
P0_16, P0_17, P0_18, P0_19,
P0_26, P0_27, P0_28, P0_30,
P0_31, P1_00, P1_01, P1_02,
P1_03, P1_04, P1_05, P1_06,
P1_07, P1_08, P1_09, P2_16,
P2_17, P2_19, P2_22, P2_24,
P2_25, P2_26, P2_27, P2_28,
P2_29, P2_30, P2_31, P3_00,
P3_01, P3_02, P3_03, P3_04,
P3_05, P3_06, P3_07, P3_08,
P3_09, P3_10, P3_11, P3_12,
P3_13, P3_14, P3_15, P3_16,
P3_17, P3_18, P3_19, P3_20,
P3_21, P3_22, P3_23, P3_24,
P3_25, P3_26, P3_27, P3_28,
P3_29, P3_30, P3_31, P4_00,
P4_01, P4_02, P4_03, P4_04,
P4_05, P4_06, P4_07, P4_08,
P4_09, P4_10, P4_11, P4_12,
P4_25, P4_26, P4_27, P4_28,
P4_29, P4_30, P4_31, P5_00,
P5_01, P5_02, P5_03, P5_04,
P5_05, P5_06, P5_07, P5_08,
P5_09, P5_10, P5_11, P5_12,
P5_13, P5_14, P5_15, P5_16,
P5_17, P5_18, P5_19, P5_20,
P5_21, P5_22, P5_27, P5_28,
P5_29, P5_30, P5_31, P6_00,
P6_01, P6_02, P6_03, P6_04,
P6_05, P6_06, P6_07, P6_08,
P6_09, P6_10, P6_11, P6_12,
P6_13, P6_14, P6_15, P6_16,
P6_17, P6_18, P6_19, P6_20,
P6_21, P6_22, P6_23, P6_24,
P6_25, P6_26
(154 ports)
P0_00, P0_01, P0_02,
P0_03, P0_04, P0_05,
P0_06, P0_07, P0_08,
P0_09, P0_10, P0_11,
P0_12, P0_13, P0_14,
P0_15, P0_16, P0_17,
P0_18, P0_19, P0_26,
P0_27, P0_28, P0_30,
P0_31, P1_00, P1_01,
P1_02, P1_03, P1_04,
P1_05, P1_06, P1_07,
P1_08, P1_09, P2_16,
P2_17, P2_19, P2_22,
P2_24, P2_25, P2_26,
P2_27, P2_28, P2_29,
P2_30, P2_31, P3_00,
P3_01, P3_02, P3_03,
P3_04, P3_05, P3_06,
P3_07, P3_08, P3_09,
P3_10, P3_11, P3_12,
P3_13, P3_14, P3_15,
P3_16, P3_17, P3_18,
P3_19, P3_20, P3_21,
P3_22, P3_23, P3_24,
P3_25, P3_26, P3_27,
P3_28, P3_29, P3_30,
P3_31, P4_00, P4_01,
P4_02, P4_03, P4_04,
P4_05, P4_06, P4_07,
P4_08, P4_09, P4_10,
P4_11, P4_12, P4_25,
P4_26, P4_27, P4_28,
P4_29, P4_30, P4_31,
P5_00, P5_01, P5_02,
P5_03, P5_04, P5_05,
P5_06, P5_07, P5_08,
P5_09, P5_10, P5_11,
P5_12, P5_13, P5_14,
P5_15, P5_16, P5_17,
P5_18, P5_19, P5_20,
P5_21, P5_22, P5_27,
P5_28, P5_29, P5_30,
P5_31, P6_00
(128 ports)
P0_00, P0_01, P0_04,
P0_05, P0_06, P0_07,
P0_08, P0_09, P0_10,
P0_11, P0_12, P0_13,
P0_14, P0_15, P0_16,
P0_17, P0_18, P0_19,
P0_26, P0_27, P0_28,
P0_30, P0_31, P1_00,
P1_01, P1_02, P1_03,
P1_04, P1_05, P1_06,
P1_07, P1_08, P1_09,
P2_16, P2_17, P2_19,
P2_22, P2_25, P2_26,
P2_27, P2_29, P2_30,
P2_31, P3_00, P3_01,
P3_02, P3_03, P3_04,
P3_05, P3_06, P3_07,
P3_08, P3_09, P3_12,
P3_13, P3_14, P3_15,
P3_16, P3_17, P3_18,
P3_21, P3_22, P3_23,
P3_24, P3_25, P3_26,
P3_27, P3_28, P3_29,
P3_30, P3_31, P4_00,
P4_01, P4_02, P4_03,
P4_04, P4_05, P4_06,
P4_07, P4_08, P4_09,
P4_10, P4_11, P4_12,
P4_25, P4_26, P4_27,
P4_28, P4_29, P4_30,
P4_31, P5_00, P5_01,
P5_02, P5_03, P5_04,
P5_05, P5_06, P5_07,
P5_08, P5_09, P5_10,
P5_11, P5_12, P5_13,
P5_14, P5_15, P5_16,
P5_17, P5_18, P5_19,
P5_20, P5_21, P5_22,
P5_27, P5_28, P5_29,
P5_30, P5_31, P6_00
(120 ports)
PPG triggered input
PPG0/1/2/3/4/5_TIN1,
PPG6/7/8/9/10/11_TIN
PPG0/1/2/3/4/5_TIN1,
PPG6/7/8/9/10/11_TIN
PPG6/7/8/9/10/11_TIN
Notes:
−See multiplexed functions on the pin assignment sheet.
−The optional restriction will be added without notification.
−The TEQFP-256 package option is under planning

Document Number: 002-10689 Rev *H Page 12 of 166
S6J32E, S6J32F, S6J32G Series
3. Product Description
3.1 Overview
This section explains the product features of the S6J3200 series. The description of this section should precede the duplicated
description on the platform manual.
3.2 Product Description
The following table describes the product features.
Table 3-1: Feature Description
Feature
Description
Technology
55-nm CMOS technology with embedded FLASH
Fully automotive qualified according to ISO/TS 16949 and AEC-Q100
Functional Safety
The product series has some functional safety features suited for ASIL-B application.
Peripherals
See function list.
Power Domain (PD)
Refer to the platform manual and the State Transition section for details.
The product series supports the power-off control of PD1, PD2 (including PD3 and 5), and PD6.
The power domain resets of PD3 and PD5 included in PD2 are not supported in the product series,
and "0" is always read from the reset factor flags of them.
This series does not support partial wakeup for PD6.
Debug and Trace
Refer to the platform manual for details.
−Standard 5-pin JTAG interface
−4k Word Embedded Trace Buffer
4-bit trace support for TEQFP package.
Full trace (dedicated 16-bit port) with special bond-out package (TEQFP-256) is planned.
System Control
Refer to the platform manual for details.
Main and sub oscillator is available.
−A wide range of 3.6 - 16MHz is available for main oscillator
−32 kHz is available for sub oscillator
Sub clock is enabled/disabled by register settings
Clock
Refer to the platform manual for details.
CLK_CLKO (Clock Output Function) is not supported.
Main Oscillation Stabilization Wait Time (at 4 MHz):8.19 ms (Initial value)
Embedded CR oscillation
Refer to the platform manual for details.
Stabilization time is as follows:
−5 µs for 4 MHz (Fast clock)
−20 µs for 100 kHz (Slow clock)
Clock Supervisor
Refer to the platform manual for details.
This product series does not support the clock supervisor output port. (Related register and internal
circuit is implemented.)
Reset
Refer to the platform manual for details.
The following resets are not mounted on this device.
−INITX
−SRSTX (and nSRST pin)
This product series does not support EX5VRST and writing EX5VRSTCNT bits in
SYSC0_SPECFGR has no effect.
Hardware Watchdog
Refer to the platform manual for details.
The hardware watchdog function stops during the PSS mode. In the related register of
HWDG_CFG, the bit ALLOWSTOPCLK is always read as 1 (HWDG_CFG.ALLOWSTOPCLK=1).
The product series does not support the Watchdog Counter Monitor Output port. (Related register
and internal circuit is implemented.)

Document Number: 002-10689 Rev *H Page 13 of 166
S6J32E, S6J32F, S6J32G Series
Feature
Description
Software Watchdog
Refer to the platform manual for details.
The product series does not support the Watchdog Counter Monitor Output port. (Related register
and internal circuit is implemented.)
Standby Mode
Refer to the platform manual for details.
Standby mode with 5-V single power supply is available.
Turning off the 3.3-V supply and the external 1.2-V supply in standby mode is available.
The long-term pulse of the indicator PWM can be outputted during RTC Standby mode.
PLL / SSCG PLL
Refer to the platform manual for details.
Use case assumption follows.
−PLL
➢Sound system clock
➢Sound frequency master clock
➢Peripherals
➢Display clock
➢Trace clock
−SSCG
➢CPU core
➢GDC core
➢HyperBus
➢DDR-HSSPI
This product supports down spread and center spread modes with the conditions defined in the
Internal Clock Timing section.
External Interrupts
Refer to the platform manual for details.
NMI
Refer to the platform manual for details.
1 NMI pin.
Memory Protection
MPU16 AHB: Refer to the platform manual for details.
MPU for AXI: ch.0 (Supervise Ethernet)
MPU for AHB: ch.1 (Supervise Media LB)
Additional MPU for graphic subsystem, MediaLB, and Ethernet AVB. These are described in the
MPU for AHB and MPU for AXI chapters in the hardware manual.
To configure Lock or Unlock for both MPUXn_UNLOCK and MPUHn_UNLOCK,
−Lock: 0x112ABB56
−Unlock: 0xACCABB56
Peripheral Protection
Refer to the platform manual for details.
Protected peripherals are described in the base address map.
Internal Memories
System RAM
Refer to the platform manual for details.
1 wait cycle is necessary for RAM read at over 160 MHz.
Do not insert wait cycles for RAM write.
Internal Memories
TCRAM
Refer to the platform manual for details.
Internal Memories
Backup RAM
16 KB
Backup RAM can only be operated in RUN mode (normal operation mode). In other modes, the
memory content should be retained, but it cannot be operated. SLEEP control for Backup RAM is
not supported and cannot be used.
Internal Memories
VRAM
ECC region is shared with the user region.
Memory size available for the user program is less when ECC is enabled.
User can define ECC enabled area and ECC disabled area.
Single error correction, double error detection (SECDED) ECC support per 32-bit word.

Document Number: 002-10689 Rev *H Page 14 of 166
S6J32E, S6J32F, S6J32G Series
Feature
Description
Embedded
Program/Work Flash
Memory
Embedded Program Flash can be accessed with 0-wait-cycle if CPU frequency is 80 MHz or less.
0-wait-cycle: 80 MHz or less.
1-wait-cycle: 160 MHz or less.
2-wait-cycle: more than 160 MHz.
Erase suspend is supported. Reading and writing to the other sectors are possible when Flash
Erase is suspended.
Serial Flash programming and Parallel Flash programming are supported.
Margin mode is not supported.
Internal Power Domains
PD1: Always ON
PD2: Cortex R5F platform/ GDC/ additional peripherals
PD4: Backup RAM
PD6: Peripherals
* The block diagram section of the TRM explains this in detail.
Power Supply
External 5 V, 3 V, 1.2 V is required.
Built-in LDO provides internal 1.2 V for Always On region (PD1).
External 1.2-V power supply control pin is supported.
External 3.3-V power supply should be controlled by GPIO.
There are constraints of power on/off sequence.
Low-voltage Detection
LVD for external voltage is supported.
LVD for internal voltage is supported.
See the specification of the detected level on the datasheet.
Low-voltage Detection for
RAM Retention (RVD)
RVD for RAM retention is effective only during the standby mode. That is, the function is available
only for the Backup RAM of 16 KB.
Resource inter-connect
The output signal of some resources can be inputted to the other resource.
I/O Ports
5-V GPIO
3-V GPIO
Multi input level and multi output drivability
Pull-up, pull-down function is available.
Resource input and output is multiplexed.
+B input is allowed many pins of the 3.3 V, 5 V, and 3.3 V/5 V I/O domains.
A/D Converter
12-bit resolution, 1 unit
50 channels of analog input for TEQFP-256 and TEQFP-216
46 channels of analog input for TEQFP-208
24 channels of them are shared with the SMC for TEQFP-256/216/208
External trigger and timer trigger are available.
The description of the A/D converter function should be referred in the S6J3200 hardware manual.
Do not refer to the description of another A/D converter function in the I/O port chapter of the
Traveo PF V3 hardware manual
CRC
Refer to the platform manual for details.
Programmable CRC
DMA support
Sound Generator
Produces sound/melody with varying frequency and amplitude for convenient duration
Square wave sound output
Automatic linear amplitude increment or decrement
Interrupt request generated when specified sound length ends
Sound Waveform
Generator
Sine waveform, saw-tooth waveform, and square waveform are generated with easy configuration
of the parameters, which specifies sound sources.
Fade-in and fade-out control for reverberation.

Document Number: 002-10689 Rev *H Page 15 of 166
S6J32E, S6J32F, S6J32G Series
Feature
Description
Sound Mixer
The input channels of 0 - 4 are reserved for the waveform generator.
Mixing different sampling frequency sounds.
Mixing internal sounds and external I2S input sounds.
Saturating addition function for keeping sound quality.
Cut a specific frequency data by digital filter.
LPF is supported by FIR filter.
Fade-in and Fade-out control.
PCM-PWM
Conversion of PCM audio streaming to pulse-width modulated signals.
Supports two output channels for stereo and mono data
Up to 16-bit output sample resolution
Support for half and full H-bridges
Audio DAC
The sound source of the fixed 48-kHz sampling frequency can be outputted.
1 unit, L/R channels support.
BTL connection is available.
I2S
2ch.
−I2S0 can output sound sources which are processed by Sound System.
−I2S1 can input sound sources which are processed by Sound System.
See the "Sound System Configuration" of the S6J3200 hardware manual in detail.
Base Timer
Refer to the platform manual for details.
A unit consists of a pair of 16-bit base timers. 12 units, that is, 24 channels of base timers are
available.
Reload Timer
Refer to the platform manual for details.
I/O Timer
Refer to the platform manual for details.
Quad Position & Revolution
Counter
(Up/Down Counter)
Refer to the platform manual for details.
Multi-functional Serial
(MFS)
Refer to the platform manual for details.
5 ports of MFS only support I2C.
Note
−Not all pins support I2C. Only pins which have the I2C I/O characteristics support it. See the datasheet in detail.
The I2C is not designed to be hot swappable.
The availability of chip select function can be seen at the Function Digit Table.
Chip Select Input is not supported.
CTS/RTS is not mounted (hardware flow control is not supported for this series.)
WUCR function is not supported for this product.
CAN-FD
Flexible data rate is supported.
16 KB/ch of message RAM is available.
The clock output from CAN pre-scaler is supplied to every CAN. ECC error generation function of
the message RAM is not supported for this device. Therefore, CAN FD ECC Error Insertion Control
Register (FDFECR) is not writeable.
CAN-FD rev 3.2 is used.
Refer to the platform manual for details
Real Time Clock (RTC)
with Auto-calibration
Refer to the platform manual for details.
DDR High Speed SPI
ch.0: HSSPI as a MCU peripheral
ch.1: HSSPI on graphic subsystem
Refer to the platform manual for details

Document Number: 002-10689 Rev *H Page 16 of 166
S6J32E, S6J32F, S6J32G Series
Feature
Description
HyperBus I/F
ch.0: HyperBus as a MCU peripheral
ch.1: HyperBus on graphic subsystem
ch.2: HyperBus on graphic subsystem
The following registers are not supported.
−Controller Status Register (HYPERBUSIn_CSR)
−Interrupt Enable Register (HYPERBUSIn_IEN)
−Interrupt Status Register (HYPERBUSIn_ISR)
−Write Protection Register (HYPERBUSIn_WPR)
−Test Register (HYPERBUSIn_TEST)
GPO signal can only be used for "Internal Control example by GPO" in this product, that is, it can
select using HyperBus of PF or using HyperBus of Graphic sub system.
See the "HyperBus Interface Port Configuration" of the S6J32E, S6J32F, S6J32G series hardware
manual in detail.
Stepper Motor Control
(SMC)
Each channel has 4 motor drivers with high output capability
External Interrupt Capture
Unit (EICU)
Refer to the platform manual for details.
Ethernet AVB
10/100 Mbps
MII-Interface and RMII-Interface
Supports audio-video bridging (AVB)
See Section 3.2.1 for details.
MediaLB
MOST25 (512FS)
3 wires
Maximum 15 ch is available.
SHE
Refer to the platform manual for details.
Source Clock Timer
Refer to the platform manual for details.
Graphics Subsystem
Variable setting of the GDC clock. (Asynchronous with CPU clock)
CPU can directly access VRAM.
Programmable panel timing controller with RGB888 and RSDS support.
Note:
−The description of the preliminary documentation will be changed without any notification.

Document Number: 002-10689 Rev *H Page 17 of 166
S6J32E, S6J32F, S6J32G Series
3.2.1 Ethernet
The following functions are not supported.
Functions
Remark
External FIFO Interface
Additional Low Latency TX FIFO Interface for DMA configurations
MAC Transmit Block
- half-duplex
- collision
- back_pressure
MAC Filtering Block
- external address match
- Wakeup On Lan
Energy Efficient Ethernet support
LPI Operation in Cadence IP
PHY Interface
- GMII
- SGMII
- TBI
10/100/1000 Operation
- 1000 M
SGMII Operation
Jumbo Frames
Physical Control Sub-Layer

Document Number: 002-10689 Rev *H Page 18 of 166
S6J32E, S6J32F, S6J32G Series
The following pin functions are required for MII-Interface and RMII-Interface:
Pin Function
MII-Interface
RMII Interface
RMII_RXERR
Not used
Used
RMII_REFCLK
Not used
Used
RMII_RX0
Not used
Used
RMII_RX1
Not used
Used
RMII_TXD0
Not used
Used
RMII_TXD1
Not used
Used
RXD0
Used
Not used
RXD1
Used
Not used
RXD2
Used
Not used
RXD3
Used
Not used
TXD0
Used
Not used
TXD1
Used
Not used
TXD2
Used
Not used
TXD3
Used
Not used
RXER
Used
Not used
RXDV
Used
Used (CRS_DV function)
RXCLK
Used
Not used
TXER
Used
Not used
TXEN
Used
Used
TXCLK
Used
Not used
MDC
Used
Used
MDIO
Used
Used

Document Number: 002-10689 Rev *H Page 19 of 166
S6J32E, S6J32F, S6J32G Series
3.2.2 RAM Guarantee
For the following reset factors, RAM Guarantee is not supported
Reset
Category
Reset Factor
Operation after Reset is Released
Waiting for
Stabilization
Mode
Evaluation
Security
Evaluation
Operation
Clock
RAM
Guarantee
Hardware
Reset
Extended internal power
supply low-voltage
detection reset
Flash
1.2-V external power
supply control
Yes
Yes
Fast CR
No
RSTX pin input reset
External power supply
low-voltage detection
reset
N/A
Yes
Yes
Fast CR
No

Document Number: 002-10689 Rev *H Page 20 of 166
S6J32E, S6J32F, S6J32G Series
4. Package and Pin Assignment
4.1 Pin Assignment
The characters next to the pin number in the pin assignment drawing specify the I/O circuit type described in Section 5.
Figure 4-1: Pin Number and I/O Circuit Type
I/O circuit type
Pin number
-
Z
Z
Z
Z
Z
208
207
206
205
204
203
- 1
- 2
A 3
A 4
○
The following port functions are only supported in certain revisions
Port Name
Description
Package Pin Number
Available at
revision
TEQFP-208
TEQFP-216
TEQFP-256
RXDV
Ethernet pin
34
34
34
N