Agilent Technologies 1664A User manual

Service Guide
Publication number 01664-97005
Second edition, January 2000
For Safety information, Warrantie , and Regulatory
information, ee the page at the end of the book.
 Copyright Agilent Technologie 1987–2000
All Right Re erved.
Agilent Technologies 1664A Logic
Analyzer

Agilent Technologies 1664A Logic Analyzer
The Agilent Technologie 1664A i a 50-MHz State/500-MHz Timing Logic Analyzer.
Features
Some of the main feature of the 1664A Logic Analyzer i a follow :
•32 data channels and 2 clock/data channels
•3. -inch disk drive
•Centronix (parallel) interface (with GPIB and RS-232C interfaces available as
options)
•Variable setup/hold time
•4 kbytes deep memory on all channels with 8 kbytes in half channel mode
•Marker measurements
•12 levels of trigger sequencing for state and 10 levels of sequential triggering for
timing
•100 MHz time and number-of-states tagging
•Full programmability (with optional interface)
Service Strategy
The ervice trategy for thi in trument i the replacement of defective a emblie .
Thi ervice guide contain information for finding a defective a embly by te ting
and ervicing the 1664A.
Thi logic analyzer can be returned to Agilent Technologie for all ervice work,
including trouble hooting. Contact your neare t Agilent Technologie Sale Office for
more detail .
ii

The Agilent Technologies 1664A Logic Analyzer
iii

In This Book
Thi book i the ervice guide for the 1664A Logic Analyzer and i divided into eight chapter .
Chapter 1 contain information about the logic analyzer and include acce orie ,
pecification and characteri tic , and equipment required for ervicing.
Chapter 2 tell how to prepare the logic analyzer for u e.
Chapter 3 give in truction on how to te t the performance of the logic analyzer.
Chapter 4 contain calibration in truction for the logic analyzer.
Chapter 5 contain elf-te t and flowchart for trouble hooting the logic analyzer.
Chapter 6 tell how to replace a emblie of the logic analyzer and how to return them to
Agilent Technologie .
Chapter 7 li t replaceable part , how an exploded view, and give ordering information.
Chapter 8 explain how the logic analyzer work and what the elf-te t are checking.
iv

Table of Contents
1 General Information
Acce orie 1–2
Specification 1–3
Characteri tic 1–3
Supplemental Characteri tic 1–4
Recommended Te t Equipment 1–8
2 Preparing for Use
To in pect the logic analyzer 2–2
Ferrite 2–3
To apply power 2–4
To operate the u er interface 2–4
To et the line voltage 2–4
To degau the di play 2–5
To clean the logic analyzer 2–5
To te t the logic analyzer 2–5
3 Testing Performance
To perform the elf-te t 3–3
To make the te t connector 3–6
To te t the thre hold accuracy 3–8
Set up the equipment 3–8
Set up the logic analyzer 3–9
Connect the logic analyzer 3–9
Te t the TTL thre hold 3–10
Te t the ECL thre hold 3–12
Te t the − U er thre hold 3–13
Te t the + U er thre hold 3–14
Te t the 0 V U er thre hold 3–15
Te t the next pod 3–16
To te t the glitch capture 3–17
Set up the equipment 3–17
Set up the logic analyzer 3–18
Connect the logic analyzer 3–18
Te t the glitch capture on the connected channel 3–20
Te t the next channel 3–22
To te t the ingle-clock, ingle-edge, tate acqui ition 3–23
Set up the equipment 3–23
Set up the logic analyzer 3–24
Connect the logic analyzer 3–26
Verify the te t ignal 3–27
Check the etup/hold combination 3–29
v

To te t the multiple-clock, multiple-edge, tate acqui ition 1–34
Set up the equipment 1–34
Set up the logic analyzer 1–35
Connect the logic analyzer 1–37
Verify the te t ignal 1–38
Check the etup/hold with ingle clock edge , multiple clock 1–40
To te t the ingle-clock, multiple-edge, tate acqui ition 1–45
Set up the equipment 1–45
Set up the logic analyzer 1–46
Connect the logic analyzer 1–48
Verify the te t ignal 1–49
Check the etup/hold combination 1–51
To te t the time interval accuracy 1–54
Set up the equipment 1–54
Set up the logic analyzer 1–55
Connect the logic analyzer 1–57
Acquire the data 1–58
Performance Te t Record 3–59
4 Calibrating an A justing
Logic analyzer calibration 4–2
Set up the equipment 4–2
To adju t the CRT monitor alignment 4–3
To adju t the CRT inten ity 4–5
5 Troubleshooting
To u e the flowchart 5–2
To check the power-up te t 5–15
To run the elf-te t 5–16
To te t the power upply voltage 5–21
To te t the CRT monitor ignal 5–23
To te t the keyboard ignal 5–24
To te t the di k drive voltage 5–25
To perform the BNC te t 5–27
To te t the logic analyzer probe cable 5–28
To te t the auxiliary power 5–32
6 Replacing Assemblies
To remove and replace the handle 6–5
To remove and replace the feet and tilt tand 6–5
To remove and replace the cover 6–5
To remove and replace the di k drive 6–6
To remove and replace the power upply 6–7
Contents
vi

To remove and replace the Main Circuit board 6–7
To remove and replace the witch actuator a embly 6–8
To remove and replace the rear panel a embly 6–9
To remove and replace the front panel and keyboard 6–10
To remove and replace the inten ity adju tment 6–10
To remove and replace the monitor 6–11
To remove and replace the handle plate 6–11
To remove and replace the fan 6–12
To remove and replace the line filter 6–12
To remove and replace the optional GPIB and RS-232C cable 6–13
To return a emblie 6–14
7 Replaceable Parts
Replaceable Part Ordering 7–2
Exploded View 7–3
Replaceable Part Li t 7–4
Power Cable and Plug Configuration 7–8
8 Theory of Operation
Block-Level Theory 8–3
The 1664A Logic Analyzer 8–3
The Logic Acqui ition Circuitry 8–6
Self-Te t De cription 8–9
Power-up Self-Te t 8–9
Sy tem Te t (Sy tem PV) 8–10
Analyzer Te t (Analy PV) 8–13
GPIB (Optional) 8–15
RS-232C(Optional) 8–16
Centronix 8–17
Contents
vii

Contents
viii

1
Acce orie 1-2
Specification 1-3
Characteri tic 1-3
Supplemental Characteri tic 1-4
Recommended Te t Equipment 1-8
General Information

General Information
Thi chapter li t the acce orie , the pecification and characteri tic , and the
recommended te t equipment.
Accessories
The following acce orie are upplied with the 1664A Logic Analyzer .
Accessories Supplie Part Number Qty
Probe tip a emblie 01650-61608 2
Probe cable 16550-61601 1
Grabber (20 per pack) 5090-4356 2
Probe ground (5 per pack) 5959-9334 2
U er’ Reference 01660-90904 1
Acce orie Pouch 01660-84501 1
HIL Mou e A2838A 1
Accessories Available
Other acce orie available for the 1664A Logic Analyzer are li ted in the Accessories for
Agilent Logic Analyzers brochure. The table below li t additional documentation that i
available from your neare t Agilent Technologie ale office for u e with your logic analyzer.
Accessories Available Part Number
Demo Training Kit E2433-60007
Programming Reference 01660-90933
Service Guide 01664-97005
1–2

Specifications
The pecification are the performance tandard again t which the product i te ted.
Maximum State Speed 50 MHz
Minimum State Clock Pul e Width*3.5 n
Minimum Ma ter to Ma ter Clock Time*20.0 n
Minimum Glitch Width* 3.5 n
Thre hold Accuracy ± (100 mV + 3% of
thre hold etting)
Setup/Hold Time:*
Single Clock, Single Edge 0.0/3.5 n through 3.5/0.0 n ,
adju table in 500-p increment
Single Clock, Multiple Edge 0.0/4.0 n through 4.0/0.0 n ,
adju table in 500-p increment
Multiple Clock , Multiple Edge 0.0/4.5 n through 4.5/0.0 n ,
adju table in 500-p increment
* Specified for an input ignal VH = -0.9 V, VL = -1.7 V, lew rate = 1 V/n , and thre hold = -1.3 V.
Characteristics
The e characteri tic are not pecification , but are included a additional information.
Full Channel Half Channel
Maximum State Clock Rate 50 MHz 50 MHz
Maximum Conventional Timing Rate 250 MHz 500 MHz
Maximum Tran itional Timing Rate 125 MHz 250 MHz
Maximum Timing with Glitch Rate N/A 125 MHz
Memory Depth 4K 8K*
Channel Count: 34 17
* For all mode except glitch.
General Information
Specifications
1–3

Supplemental Characteristics
Probes
Input Re i tance 100 kΩ, ± 2%
Input Capacitance ~ 8 pF
Minimum Voltage Swing 500 mV, peak-to-peak
Thre hold Range ± 6.0 V, adju table in 50-mV increment
State Analysis
State/Clock Qualifier 6
Time Tag Re olution*8 n or 0.1%, whichever i greater
Maximum Time Count
Between State 34 econd
Maximum State Tag Count*4.29 x 109
Timing Analysis
Sample Period Accuracy 0.01 % of ample period
Channel-to-Channel Skew 2 n , typical
Time Interval Accuracy ± [ ample period + channel-to-channel kew
+(0.01%)(time reading)]
Triggering
Sequencer Speed 125 MHz, maximum
State Sequence Level 12
Timing Sequence Level 10
Maximum Occurrence Counter
Value 1,048,575
Pattern Recognizer 10
Maximum Pattern Width 34 channel
Range Recognizer 2
Range Width 32 bit each
Timer 2
Timer Value Range 400 n to 500 econd
Glitch/Edge Recognizer 2 (timing only)
Maximum Glitch/Edge Width 34 channel
*Maximum tate clock rate with time or tate tag on i 50 MHz. When all pod are a igned to a tate or timing
machine, time or tate tag halve the memory depth.
General Information
Supplemental Characteristics
1–4

Measurement an Display Functions
Displaye Waveforms 24 line maximum, with crolling acro 96 waveform .
Measurement Functions
Run/Stop Functions Run tart acqui ition of data in pecified trace mode.
Stop In ingle trace mode or the fir t run of a repetitive acqui ition, Stop halt
acqui ition and di play the current acqui ition data. For ub equent run in repetitive
mode, Stop halt acqui ition of data and doe not change the current di play.
Trace Mo e Single mode acquire data once per trace pecification. Repetitive mode
repeat ingle mode acqui ition until Stop i pre ed or until the time interval between
two pecified pattern i le than or greater than a pecified value, or within or not within
a pecified range.
In icators
Activity In icators Provided in the Configuration and Format menu for identifying
high, low, or changing tate on the input .
Markers Two marker (X and O) are hown a vertical da hed line on the di play.
Trigger Di played a a vertical da hed line in the Timing Waveform di play and a line 0
in the State Li ting di play.
Data Entry/Display
Labels Channel may be grouped together and given a 6-character name. Up to
126 label in each analyzer may be a igned with up to 32 channel per label.
Display Mo es State li ting, State Waveform , Chart, Compare Li ting, Compare
Difference Li ting, Timing Waveform , and Timing Li ting . State Li ting and Timing
Waveform can be time-correlated on the ame di play .
Timing Waveform Pattern readout of timing waveform at X or O marker.
Bases Binary, Octal, Decimal, Hexadecimal, ASCII (di play only), Two’ Complement,
and U er-defined ymbol .
Symbols 1,000 maximum. Symbol can be downloaded over RS-232 or GPIB.
General Information
Supplemental Characteristics
1–5

Marker Functions
Time Interval The X and O marker mea ure the time interval between a point on a
timing waveform and the trigger, two point on the ame timing waveform, two point on
different waveform , or two tate (time tagging on).
Delta States (state analyzer only) The X and O marker mea ure the number of
tagged tate between one tate and trigger or between two tate .
Patterns The X and O marker can be u ed to locate the nth occurrence of a pecified
pattern from trigger, or from the beginning of data. The O marker can al o find the nth
occurrence of a pattern from the X marker.
Statistics X and O marker tati tic are calculated for repetitive acqui ition . Pattern
mu t be pecified for both marker , and tati tic are kept only when both pattern can be
found in an acqui ition. Stati tic are minimum X to O time, maximum X to O time,
average X to O time, and ratio of valid run to total run .
Auxiliary Power
Power Through Cable 1/3 amp at 5 V maximum per cable
Operating Environment
Temperature In trument, 0 °C to 55 °C (+32 °F to 131 °F).
Probe lead et and cable ,
0 °C to 65 °C (+32 °F to 149 °F).
Humidity In trument, probe lead et , and cable , up to
95% relative humidity at +40 °C (+122 °F).
Altitude To 4600 m (15,000 ft).
Vibration Operating: Random vibration 5 to 500 Hz,
10 minute per axi , ≈0.3 g (rm ).
Non-operating: Random vibration 5 to 500 Hz,
10 minute per axi , ≈ 2.41 g (rm );
and wept ine re onant earch, 5 to 500 Hz,
0.75 g (0-peak), 5 minute re onant dwell
at 4 re onance per axi .
Dimensions
General Information
Supplemental Characteristics
1–6

Pro uct Regulations
Safety IEC 348
UL 1244
CSA Standard C22.2 No.231 (Serie M-89)
EMC Thi product meet the requirement of the European
Communitie (EC) EMC Directive 89/336/EEC.
Emi ion EN55011/CSIPR 11 (ISM, Group1,Cla A equipment)
SABS RAA Act No. 24(1990)
Immunity EN50082-1 Code1Note 2
IEC 801-2 (ESD)4kV CD, 8kV AD 2
IEC 801-3 (Rad.) 3V/m 1
IEC 801-4 (EFT) 1kV 2
1Performance Code :
1 PASS - Normal operation , no effect.
2 PASS - Temporary degradation, elf recoverable.
3 PASS - Temporary degradation, operator intervention required.
4 FAIL - Not recoverable, component damage.
2Note : (None)
General Information
Supplemental Characteristics
1–7

Recommended Test Equipment
Equipment Required
Equipment Critical Specifications Recommended
Model/Part
Use*
Pulse Generator 100 MHz, 3.5 ns pulse width,
< 600 ps rise time Agilent 8131A Option 020 P,T
Digitizing Oscilloscope ≥6 GHz bandwidth, < 58 ps rise time Agilent 54121T P
Function Generator Accuracy ≤ (5)(10−6) ×frequency,
DC offset voltage ±6.3 V
Agilent 3325B Option 002 P
Digital Multimeter 0.1 mV resolution, 0.005% accuracy Agilent 3458A P
BNC-Banana Cable Agilent 11001-60001 P
BNC Tee BNC (m)(f)(f) Agilent 1250-0781 P
Cable BNC (m)(m) 48 inch > 2GHz bandwidth Agilent 8120-1840 P,T
SMA Coax Cable (Qty 3) 18 GHz bandwidth Agilent 8120-4948 P
Adapter (Qty 4) SMA(m)-BNC(f) Agilent 1250-1200 P, T
Adapter SMA(f)-BNC(m) Agilent 1250-2015 P
Coupler (Qty 4) BNC (m)(m) Agilent 1250-0216 P, T
20:1 Probes (Qty 2) Agilent 54006A P
BNC Test Connector, 17x2
(Qty 1)** P
BNC Test Connector, 6x2
(Qty 4)** P,T
Digitizing Oscilloscope > 100 MHz Bandwidth Agilent 54600A T
BNC Shorting Cap Agilent 1250-0074 T
BNC-Banana Adapter Agilent 1251-2277 T
Light Power Meter United Detector 351 A
Alignment Tool 8710-1300 A
*A = Adju tment P = Performance Te t T = Trouble hooting
**In truction for making the e te t connector are in chapter 3, "Te ting Performance."
General Information
Recommended Test Equipment
1–8

2
To in pect the logic analyzer 2-2
Ferrite 2-3
To apply power 2-4
To operate the u er interface 2-4
To et the line voltage 2-4
To degau the di play 2-5
To clean the logic analyzer 2-5
To te t the logic analyzer 2-5
Preparing for Use

Preparing For Use
Thi chapter give you in truction for preparing the logic analyzer for u e.
Power Requirements
The logic analyzer require a power ource of either 115 Vac or 230 Vac, –22 % to
+10 %, ingle pha e, 48 to 66 Hz, 200 Watt maximum power.
Operating Environment
The operating environment i li ted in chapter 1. Note the nonconden ing humidity
limitation. Conden ation within the in trument can cau e poor operation or
malfunction. Provide protection again t internal conden ation.
The logic analyzer will operate at all pecification within the temperature and
humidity range given in chapter 1. However, reliability i enhanced when operating
the logic analyzer within the following range :
•Temperature: +20 °C to +3 °C (+68 °F to +9 °F)
•Humidity: 20% to 80% noncondensing
Storage
Store or hip the logic analyzer in environment within the following limit :
•Temperature: -40 °C to + 7 °C
•Humidity: Up to 90% at 6 °C
•Altitude: Up to 1 ,300 meters ( 0,000 feet)
Protect the logic analyzer from temperature extreme which cau e conden ation on
the in trument.
To inspect the logic analyzer
1Inspect the shipping container for damage.
If the hipping container or cu hioning material i damaged, keep them until you have
checked the content of the hipment and checked the in trument mechanically and
electrically.
2Check the supplied accessories.
Acce orie upplied with the logic analyzer are li ted in "Acce orie " in chapter 1.
3Inspect the product for physical damage.
Check the logic analyzer and the upplied acce orie for obviou phy ical or mechanical
defect . If you find any defect , contact your neare t Agilent Technologie Sale Office.
Arrangement for repair or replacement are made, at Agilent Technologie ’ option, without
waiting for a claim ettlement.
2–2

Ferrites
Ferrite are included in the 1664A acce ory pouch for the logic analyzer cable. When
properly in talled, the ferrite reduce RFI emi ion from the logic analyzer.
In order to en ure compliance of the 1664A Logic Analyzer to the CISPR11 Cla A radio
frequency interference (RFI) limit , you mu t in tall the ferrite to ab orb radio frequency
energy.
Note: Adding or removing the ferrite will not affect the normal operation of the analyzer.
Ferrite In tallation In truction
U e the following tep to in tall the ferrite on the logic analyzer cable.
1Place the ferrite halves and spacer on the logic analyzer cable like a clamshell
around the whole cable. The ferrite should be 10 cm (about 4 in) from the the end of
the cable shell as shown.
2Insert the clamps onto the ends of the ferrites. The locking tab should fit cleanly in
the ferrite grooves.
When properly in talled, the ferrite hould appear on the logic analyzer cable a hown.
Preparing for Use
Ferrites
2–3

To apply power
CAUTION Electrostatic discharge can damage electronic components. Use grounded wriststraps and
mats when performing any service to the logic analyzer.
1Check that the line voltage selector, located on the rear panel, is on the correct
setting and the correct fuse is installed.
See al o, "To et the line voltage" on thi page.
2Connect the power cord to the instrument and to the power source.
Thi in trument i equipped with a three-wire power cable. When connected to an
appropriate ac power outlet, thi cable ground the in trument cabinet. The type of power
cable plug hipped with the in trument depend on the country of de tination. Refer to
chapter 7, "Replaceable Part ," for option number of available power cable and plug
configuration .
3Turn on the instrument power switch located on the front panel.
To operate the user interface
To select a field on the logic analyzer screen, use the arrow keys to highlight the
field, then press the Select key. For more information about the logic analyzer
interface, refer to the Agilent Technologies 1660 Series Logic Analyzer User’s
Reference.
To set the GPIB address or to configure for RS-232C, refer to the Agilent
Technologies 1660 Series Logic Analyzer User’s Reference.
To set the line voltage
When hipped from the factory, the line voltage elector i et and an appropriate fu e i
in talled for operating the in trument in the country of de tination. To operate the
in trument from a power ource other than the one et, perform the following tep .
Preparing for Use
To apply power
2–4