Aim ACXx429-3U-32 User manual

ACXx429-32 Hardware Manual
i
ACXx429-3U-32
ARINC429 32-Channel
Module
for PXI-Express / cPCI-Express (3U)
Hardware
Manual
V01.00 Rev. A
November
2015

ACXx429-32 Hardware Manual
i
ACXx429-3U-32
ARINC429 32-Channel Module
for
PXI-Express/cPCI-Express(3U)
V01.00 Rev. A
November 2015
AIM No:
60-127D6-16-0100-A
Hardware
Manual

ACXx429-32 Hardware Manual
ii
AIM
– Gesellschaft für angewandte Informatik und Mikroelektronik mbH
AIM GmbH
Sasbacher Str. 2
D
-79111 Freiburg / Germany
Phone
[phone]
Fax
[phone]
sales@aim
-online.com
AIM UK Office
Cressex Enterprise Centre, Lincoln Rd.
High Wycombe, Bucks. HP12 3RB / UK
Phone
[phone]
Fax
[phone]
[e-mail]
AIM GmbH – Munich Sales Office
Terofalstr. 23a
D
-80689 München / Germany
Phone
[phone]
Fax
[phone]
salesg
[e-mail]
AIM USA LLC
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Phone
267-982-2600
Fax
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[e-mail]
© AIM GmbH 2015
Notice: The information that is provided in this document is believed to be accurate.
No responsibility is assumed by AIM GmbH for its use. No license or rights are granted
by implication in connection therewith. Specifications are subject to change without
notice.

ACXx429-32 Hardware Manual
iii
DOCUMENT HISTORY
The following table defines the history of this document. Appendix A provides a more
comprehensive list of changes made with each version.
Version Cover Date Created by Description
V01.00 Rev. A 19.11.2015 S.Thota First Released Version

ACXx429-32 Hardware Manual
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ACXx429-32 Hardware Manual
v
TABLE OF CONTENTS
Section Title Page
1Introduction.............................................................................................................7
1.1 General....................................................................................................................................... 7
1.2 How This Manual is organized................................................................................................. 8
1.3 Applicable Documents.............................................................................................................. 8
1.3.1Industry Documents................................................................................................................ 8
1.3.2 Product Specific Documents................................................................................................... 8
2Installation...............................................................................................................9
2.1 Preparation and Precaution for Installation ........................................................................... 9
2.2 Installation Instructions............................................................................................................ 9
2.3 Connecting to other Devices ................................................................................................. 10
2.3.1 ACXx429-32 Frontpanel Connector Pinout .......................................................................... 11
2.4 Front Panel LEDs .................................................................................................................... 12
3Structure of the ACXx429 ....................................................................................13
3.1 PCI-Express bus and BIU-I/O FPGA...................................................................................... 14
3.1.1 Global RAM Interface and Arbitration................................................................................... 14
3.1.2 Boot up.................................................................................................................................. 14
3.2 Global RAM.............................................................................................................................. 14
3.3 BIU-Processors (BIP).............................................................................................................. 14
3.4 ARINC-429 Encoder ................................................................................................................ 15
3.5 ARINC-429 Decoder ................................................................................................................ 15
3.6 External Trigger Output.......................................................................................................... 15
3.7 IRIG- and Time Code Section................................................................................................. 16
3.7.1 Time Code Encoder/Decoder ............................................................................................... 16
3.7.2 Time Tag Methods................................................................................................................ 16
3.8 PXI / cPCI - Connector Pin Assignment................................................................................ 17
4PXI-Express Instrumentation Bus.......................................................................19
4.1 About the PXIe Standard........................................................................................................ 19
4.1.1 Backplane Trigger Lines....................................................................................................... 20
4.1.2 System Reference Clock (10MHz) ....................................................................................... 20
4.1.3 Star Trigger........................................................................................................................... 21
5Technical data.......................................................................................................23
6Notes .....................................................................................................................27
6.1 Acronyms................................................................................................................................. 27

ACXx429-32 Hardware Manual
vi
LIST OF FIGURES
Figure Title Page
Figure 2-1: Front Panel view..........................................................................................10
Figure 2-2: Status LED view..........................................................................................12
Figure 3-1: Block Diagram of ACXx429-3U-32..............................................................13
Figure 4-1: PXI architecture...........................................................................................19
LIST OF TABLES
Figure Title Page
Table 2.1: Pin assignment ACXx429-32........................................................................11
Table 2.2: Front Panel LED description.........................................................................12
Table 3.1: IRIG-B: Binary Coded Time Tag...................................................................16
Table 3.2 PXI XJ4 connector's pin-out...........................................................................17
Table 3.3: cPCI J1 connector's pin-out..........................................................................17

1. Introduction
ACXx429-32 Hardware Manual
7
1 INTRODUCTION
1.1 General
This document comprises the Hardware User’s Manual for the PXI ACXx429-3U-32
which implements 32 transmit and receive ARINC-429 channels, based on the PCI-
Express communication standard. The document covers the hardware installation,
board connections, technical data and a general description of the hardware
architecture. For programming information please refer to the documents listed in the
'Applicable Documents' section.
The ACXx429-3U-32 is a member of AIM’s new family of CompactPCI /PXI (3U)
modules for analysis, simulation, monitoring and testing of ARINC429 channels
providing 32 channels on a 3U module form factor.
Each channel is software configurable in runtime as a fixed amplitude Transmitter or
Receiver.
On the transmit channels, the ACXx429 acts as an autonomously operating bus traffic
simulator, supporting multiple modes of transmission sequencing. Full error injection
capabilities are available, whereby the error injection is programmable individually for
each channel and label. For special transmission operating modes the parity bit can be
used alternatively as an additional data bit. The rise and fall time of the bus signals are
individually programmable by software for each transmit channel.
For the receive channels, the ACXx429 provides an advanced monitor and analyser
function with unique on-board error detection, triggering and filtering capabilities.
Monitor and analyser functions are available concurrently and independent from each
other. The hardware architecture provides resources to guarantee that the performance
of one function is not affected by the current load of the other function. The rise and fall
times of the bus signals are individually programmable for each receive channel. To
adapt to different transmit speeds, the transmission rate can be varied in discrete steps
between approximately 90 and 120Kbits on the high speed bus and between 11.5 and
16.0 on the low speed lines.
The hardware architecture provides ample resources (i.e. processing capability and
memory) to guarantee, that all specified interface functions are available concurrently
and to full performance specifications.
The advanced architecture uses a special processor for the ARINC-429 stream. A
powerful Memory Arbiter is implemented in a Field Programmable Gate Array (FPGA).
This FPGA supports both, the interface to the application and driver software tasks
running on the host computer and assists the communication for data transfer. This
feature expands the capability of the ACXx429 module to that of a high level instrument.
To fulfill the real-time requirements of a typical avionic type databus system, a high
performance 32bit RISC processor (BIP) is implemented.

1. Introduction
ACXx429-32 Hardware Manual
8
A free-wheeling IRIG-B Time code Encoder/Decoder is implemented on the ACXx429 to
satisfy the requirements of 'multi-channel time tag synchronization' on the system level.
The IRIG-B compatible amplitude modulated sine wave output allows the
synchronization of any external module implementing IRIG-B time stamping.
The module can be installed in standard cPCI/PXI peripheral slot and cPCIe/PXIe (3U)
hybrid slots. If installed in a peripheral PXI or hybrid PXIe slot, 8 PXI Trigger OUT and a
PXI System Reference Clock (10MHz) based time tag mode are supported.
1.2 How This Manual is organized
This ACXx429 Hardware Manual is comprised of the following sections.
Section 1 - INTRODUCTION - contains an overview of this manual.
Section 2 - INSTALLATION - describes the steps required to install the ACXx429
device and connect the device to other external 429 interfaces, IRIG-B,
and trigger out.
Section 3 - STRUCTURE OF THE ACXX429 - describes the physical hardware
interfaces on the ACXx429 using a block diagram and a description of
each main component
Section 4 - PXI-EXPRESS INSTRUMENTATION BUS - describes the features of
the PXI Interface
Section 5 - TECHNICAL DATA - describes the technical specification of the
ACXx429.
1.3 Applicable Documents
The following documents shall be considered to be a part of this document to the extent
that they are referenced herein. In the event of conflict between the documents
referenced and the contents of this document, the contents of this document shall have
precedence.
1.3.1 Industry Documents
[1] PXI Express Hardware Specification – Rev. 1.0 – Aug. 22, 2005
[2] PXI Hardware Specification – Rev. 2.2 – September 22, 2004
1.3.2 Product Specific Documents
[3] AIM - Reference Manual ACXx429 Application Interface Library: detailed
description of the programming interface between the Host Carrier board and the
onboard driver software.

2. Installation
ACXx429-32 Hardware Manual
9
2 INSTALLATION
2.1 Preparation and Precaution for Installation
The ACXx429 features full PCI Plug and Play capability; therefore, there are no
jumpers or switches on the board that require modification by the user in order to
interface to the PCI bus.
It is recommended to use a wrist strap for any installations. If there is no wrist wrap
available, then touch a metal plate on your system to ground yourself and discharge any
static electricity during the installation work.
2.2 Installation Instructions
The following instructions describe how to install the ACXx429 module in your PXI/cPCI
system. Please follow the instructions carefully, to avoid any damage on the device.
To Install the ACXx429
1. Shutdown your system and all peripheral devices.
2. Unplug the power cord from the wall outlet. (Inserting or removing modules
with power applied may result in damage to module devices).
3. Find a free peripheral/hybrid expansion slot in your system.
4. Remove the slot bracket from the slot you have chosen and put it aside.
5. Make sure the injector/ejector handle is in its downward position.
6. Align the ACXx429 with the card guides on the top and bottom of the
peripheral expansion slot. Do not raise the injector/ejector handle as you
insert.
7. Hold the handle as you slowly slide the module into the chassis until the
handle catches on the injector/ejector rail.
8. Raise the injector/ejector handle until the module firmly seats into the
backplane receptacle connectors. The front panel of the ACXx429 should be
even with the front of the chassis.
9. Secure the card to the PXI/cPCI chassis tightening the two bracket-retaining
screws on the top and bottom of the front panel
10.Connect the system to the power source. Turn on the power of your system.

2. Installation
ACXx429-32 Hardware Manual
10
2.3 Connecting to other Devices
The connection to other devices is done via a SCSI-3 female connector.
The Frontpanel have 32 ARINC429 channels, IRIG IN/OUT and Trigger OUT.
The ACXx429-3U-32 implementation has the capability to share the I/O- pins. This
means each ARINC429 channel can be used as Transmit or Receive channel, but only
one operation mode is possible at one time. The pinout is listed below.
Figure 2-1: Front Panel view

2. Installation
ACXx429-32 Hardware Manual
11
2.3.1 ACXx429-32 Frontpanel Connector Pinout
68 pin SCSI-3 female connector, Downward Compatibility Mode
Pin
No.
Signal
Direction
Type
Pin No.
Signal
Direction
Type
1
TxRx_True_1
Bidir.
35
TxRx_Comp_1
Bidir.
2
TxRx_True_2
Bidir.
36
TxRx_Comp_2
Bidir.
3
TxRx_True_3
Bidir.
37
TxRx_Comp_3
Bidir.
4
TxRx_True_4
Bidir.
38
TxRx_Comp_4
Bidir.
5
TxRx_True_5
Bidir.
39
TxRx_Comp_5
Bidir.
6
TxRx_True_6
Bidir.
40
TxRx_Comp_6
Bidir.
7
TxRx_True_7
Bidir.
41
TxRx_Comp_7
Bidir.
8
TxRx_True_8
Bidir.
42
TxRx_Comp_8
Bidir.
9
TxRx_True_9
Bidir.
43
TxRx_Comp_9
Bidir.
10
TxRx_True_10
Bidir.
44
TxRx_Comp_10
Bidir.
11
TxRx_True_11
Bidir.
45
TxRx_Comp_11
Bidir.
12
TxRx_True_12
Bidir.
46
TxRx_Comp_12
Bidir.
13
TxRx_True_13
Bidir.
47
TxRx_Comp_13
Bidir.
14
TxRx_True_14
Bidir.
48
TxRx_Comp_14
Bidir.
15
TxRx_True_15
Bidir.
49
TxRx_Comp_15
Bidir.
16
TxRx_True_16
Bidir.
50
TxRx_Comp_16
Bidir.
17
TxRx_True_30
Bidir.
51
TxRx_Comp_30
Bidir.
18
TxRx_True_31
Bidir.
52
TxRx_Comp_31
Bidir.
19
TxRx_True_17
Bidir.
53
TxRx_Comp_17
Bidir.
20
TxRx_True_18
Bidir.
54
TxRx_Comp_18
Bidir.
21
TxRx_True_19
Bidir.
55
TxRx_Comp_19
Bidir.
22
TxRx_True_20
Bidir.
56
TxRx_Comp_20
Bidir.
23
TxRx_True_21
Bidir.
57
TxRx_Comp_21
Bidir.
24
TxRx_True_22
Bidir.
58
TxRx_Comp_22
Bidir.
25
TxRx_True_23
Bidir.
59
TxRx_Comp_23
Bidir.
26
TxRx_True_24
Bidir.
60
TxRx_Comp_24
Bidir.
27
TxRx_True_29
Bidir.
61
TxRx_Comp_29
Bidir.
28
GND
Pow.
62
TRIGGER_OUT
OUT
29
IRIG_IN
IN
63
IRIG_OUT
OUT
30
TxRx_True_25
Bidir.
64
TxRx_Comp_25
Bidir.
31
TxRx_True_26
Bidir.
65
TxRx_Comp_26
Bidir.
32
TxRx_True_27
Bidir.
66
TxRx_Comp_27
Bidir.
33
TxRx_True_28
Bidir.
67
TxRx_Comp_28
Bidir.
34
TxRx_True_32
Bidir.
68
TxRx_Comp_32
Bidir.
Table 2.1: Pin assignment ACXx429-32

2. Installation
ACXx429-32 Hardware Manual
12
2.4 Front Panel LEDs
Five sub-miniature LEDs, located at the front panel, indicate the module status. The
LEDs are located in a quadruple LED-Array on the physical interface daughterboard.
Figure 2-2: Status LED view
LED Name
Colour
Description
ACTIVITY
Green
LED flashes if data is transmitted on any channel.
FAIL
Red
LED illuminates if an error occurred during either one of the BIU self-
test.
RX-ERR
Red
LED flashes if an error on any channel is detected.
RX-ERR-LATCH
Red
LED illuminates if an error on any channel is detected (stored error).
PCI Activity
Blue
LED flashes if there is local (on board PCIe/PCI bus) activity
Table 2.2: Front Panel LED description

3. Structure of the ACXx429
ACXx429-32 Hardware Manual
13
3 STRUCTURE OF THE ACXX429
The structure of the ACXx429 is shown in Figure 3-1. The ACXx429 comprises the
following main sections:
•PCI bus and BIU-IO FPGA
•Global RAM
•BIU Processors Section (2-BIU’s)
•Physical I/O Interface with 32 ARINC-429 channels and Trigger out
•IRIG- Time Code Proc. with free-wheeling function and Sine Wave Output
•Boot-Up Flash
•PXI Instrumentation Bus
Figure 3-1: Block Diagram of ACXx429-3U-32

3. Structure of the ACXx429
ACXx429-32 Hardware Manual
14
3.1 PCI-Express bus and BIU-I/O FPGA
The new common FPGA architecture of AIM’s PCI family includes a complete PCI-
Express bus logic (which is translated to a legacy PCI interface using an external bridge
component) and the 2-BIU processors logic. This programmable device implements the
following features:
•PCI Express 1.1 compliant bus interface
•Global RAM interface and arbitration
•Boot function
•SPI controller for update programming
•ARINC-429 Encoder
•ARINC-429 Decoder
•IRIG Encoder and decoder support
•External Trigger Output
•PXI Instrumentation Bus Capabilities
3.1.1 Global RAM Interface and Arbitration
The common FPGA implements a Global RAM arbiter, which controls the Global RAM
access between both participants, the Host through the PCI-Express bus and the BIU
processor.
3.1.2 Boot up
To provide maximum flexibility and upgradeability, the FPGA device and the processors
are booted automatically from dedicated SPI-Flashes after power up.
3.2 Global RAM
The Global RAM is shared between both BIU processors (BIP) and the Host-Card Bus.
The arbitration is handled by the common FPGA. It has access to the common Global
RAM via a 32 bit wide data port.
3.3 BIU-Processors (BIP)
There are two physical BIU processors. Each BIP consists of an ultra-low power, high
performance 32bit RISC processor.

3. Structure of the ACXx429
ACXx429-32 Hardware Manual
15
3.4 ARINC-429 Encoder
The encoder converts the parallel data into a serial ARINC429 encoded data stream
and appends the parity and the gap bits. The programmable frame-time between two
labels can be set in the range from 0 up to 255 ARINC429 bits.
The encoder provides the following error injection capabilities:
•Gap Error (-1 bit)
•Bitcount Error (+/- 1 bit)
•Coding Error (fixed at bit position 12)
•Parity Error (if no special transmission mode is chosen)
3.5 ARINC-429 Decoder
The decoder converts the serial received data stream into a parallel data double word
and generates an additional 16 bit report for each received label. The decoder
measures the gap time between two labels for gap error detection and bus load traffic
detection.
The decoder provides the following error detection capabilities:
•Gap Error Detection
•Bit count Error Detection
•Coding Error Detection
•Parity Error Detection (if no special transmission mode is chosen)
3.6 External Trigger Output
One Trigger output is provided on ACXx429-3U-32 variant.
The Trigger output is TTL level compatible. Filter circuitry is provided at the trigger
output to cover Electromagnetic Compatibility (EMC) aspects.
Trigger output can be also set to be triggered via PXI Instrumentation Bus on the
backplane.

3. Structure of the ACXx429
ACXx429-32 Hardware Manual
16
3.7 IRIG- and Time Code Section
The main functions of the Time Code Processor (TCP) are:
•IRIG-B compatible Time Code Decoder function
•Time code Encoder – IRIG-B compatible Time Encoder function
3.7.1 Time Code Encoder/Decoder
The generated time code signal is an IRIG-B compatible sinusoidal waveform. The time
code information can be used for time-tagging and multi-channel synchronization. On
the ACXx429 a new generation IRIG-B section is implemented with a free-wheeling
IRIG functionality. If no external IRIG signal is detected, the TCP switches
automatically to the free-wheeling mode. Also, if an external IRIG-B signal is detected in
free-wheeling mode, the Time tag is automatically synchronized to this external IRIG-B
signal.
The time tag on the board is generated in the format explained in the following table:
Time Element
Number of bits
DAYS of Year
9
HOURS of Day
5
MINUTES of Hour
6
SECONDS of Minute
6
MICROSECONDS of Second
20
Summary
46 (6 Bytes, stored in two 32bit words)
Table 3.1: IRIG-B: Binary Coded Time Tag
3.7.2 Time Tag Methods
Besides the ARINC429 receive and transmit signals, the 68 pin SCSI-3 connector
comprises one Trigger output signal as well as the IRIG-B- input and output as listed at
all previous described Connector Pinout tables.
The IRIG-IN and IRIG-OUT signals shall be connected depending on the Time
synchronisation method used as shown below.
1. Single AIM-Module No External IRIG-B Source
No connection required
2. Multiple AIM-Modules with No Common Synchronization Requirement
No connection required
3. Single or Multiple AIM-Module(s) with External IRIG-B Source
Connect external IRIG-B source to IRIG-IN and GND of all modules
4. Multiple AIM-Modules with No External IRIG-B Source Internally
Synchronized.
Connect the IRIG-OUT signal and the GND of the module you have chosen as
the time master to all IRIG-IN signals (including the time master).

3. Structure of the ACXx429
ACXx429-32 Hardware Manual
17
3.8 PXI / cPCI - Connector Pin Assignment
To be able to connect a PXI card into a PXIe hybrid slot the couple J1+ XJ4 connectors
instead of the legacy J2 + J1 pair must be used, as explained in [1] and [2] and their
extensions. PXIe introduces the usage of the I/O pins on XJ4 as legacy PXI triggers,
Clock, Star and Local Bus signals. J1 carries the cPCI reserved pins locations for the
PCI communication bus.
XJ4 Connector
pin
Z
A
B
C
D
E
F
1
GND
GA4
GA3
GA2
GA1
GA0
GND
2
GND
RSV
RSV
RSV
RSV
RSV
GND
3
GND
RSV
RSV
RSV
GND
RSV
GND
4
GND
RSV
RSV
RSV
RSV
RSV
GND
5
GND
PXI_TRIG_3
PXI_TRIG_4
PXI_TRIG_5
GND
PXI_TRIG_6
GND
6
GND
PXI_TRIG_2
GND
RSV
PXI_STAR
PXI_CLK10
GND
7
GND
PXI_TRIG_1
PXI_TRIG_0
RSV
GND
PXI_TRIG_7
GND
8
GND
RSV
GND
RSV
PXI_LBL6
PXI_LBR6
GND
Table 3.2 PXI XJ4 connector's pin-out
Legacy PXI - J1 Connector
PIN
Z
A
B
C
D
E
F
25
GND
5V
REQ64#
ENUM#
3.3V
5V
GND
24
GND
AD[1]
5V
V(IO)
AD[0]
ACK64#
GND
23
GND
3.3V
AD[4]
AD[3]
5V
AD[2]
GND
22
GND
AD[7]
GND
3.3V
AD[6]
AD[5]
GND
21
GND
3.3V
AD[9]
AD[8]
M66EN
C/BE[0]#
GND
20
GND
AD[12]
GND
V(I/O)
AD[11]
AD[10]
GND
19
GND
3.3V
AD[15]
AD[14]
GND
AD[13]
GND
18
GND
SERR#
GND
3.3V
PAR
C/BE[1]#
GND
17
GND
3.3V
IPMB_SCL
IPMB_SDA
GND
PERR#
GND
16
GND
DEVSEL#
GND
V(I/O)
STOP#
LOCK#
GND
15
GND
3.3V
FRAME#
IRDY#
BD_SEL#
TRDY#
GND
12-14 Key Area
11
GND
AD[18]
AD[17]
AD[16]
GND
C/BE[2]#
GND
10
GND
AD[21]
GND
3.3V
AD[20]
AD[19]
GND
9
GND
C/BE[3]#
IDSEL
AD[23]
GND
AD[22]
GND
8
GND
AD[26]
GND
V(I/O)
AD[25]
AD[24]
GND
7
GND
AD[30]
AD[29]
AD[28]
GND
AD[27]
GND
6
GND
REQ#
GND
3.3V
CLK
AD[31]
GND
5
GND
RSV
RSV
RST#
GND
GNT#
GND
4
GND
IPMB_PWR
HEALTY#
V(I/O)
INTP
INTS
GND
3
GND
INTA#
INTB#
INTC#
5V
INTD#
GND
2
GND
TCK
5V
TMS
TDO
TDI
GND
1
GND
5V
-12V
TRST#
+12V
5V
GND
Table 3.3: cPCI J1 connector's pin-out
RSV: Reserved Pin
RED MARKED PINS on J1 are left unconnected, the corresponding features are not
implemented. BROWN MARKED Pins are pulled-up to set specific PCI features.

4. PXI-Express Instrumentation Bus
ACXx429-32 Hardware Manual
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