Aim APE-FDX-2 User manual

V01.00 Rev. A
June 2017
APE-FDX-2
10/100/1000Mbit
AFDX / ARINC664
Test and Simulation
Card Set for PCIe Bus
Hardware
Manual

APE-FDX-2 Hardware Manual
i
APE-FDX-2
10/100/1000Mbit
AFDX/ARINC664
Test and Simulation
Card Set for PCIe 2.0
V01.00 Rev. A
June 2017
AIM No.
60-151A0-16-0100-A
Hardware
Manual

APE-FDX-2 Hardware Manual
ii
AIM –Gesellschaft für angewandte Informatik und Mikroelektronik mbH
AIM GmbH
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Phone [phone]
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[email protected]
AIM UK Office
Cressex Enterprise Centre, Lincoln Rd.
High Wycombe, Bucks. HP12 3RB / UK
Phone [phone]
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[email protected]
AIM GmbH –Munich Sales Office
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Phone [phone]
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[email protected]
AIM USA LLC
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Suite 211 Trevose, PA 19053
Phone [phone]
Fax [phone]
[email protected]
© AIM GmbH 2017
Notice: The information that is provided in this document is believed to be accurate.
No responsibility is assumed by AIM GmbH for its use. No license or rights are granted
by implication in connection therewith. Specifications are subject to change without
notice.

APE-FDX-2 Hardware Manual
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DOCUMENT HISTORY
The following table defines the history of this document.
Version
Cover Date
Created by
Description
V01.00 A
13.06.2017
M. Maier / D. Bau
First release

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APE-FDX-2 Hardware Manual
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TABLE OF CONTENTS
Section Title Page
1Introduction ............................................................................................................1
1.1 General........................................................................................................................................1
1.2 How This Manual is Organized.................................................................................................2
1.3 Applicable Documents ..............................................................................................................2
1.3.1 Industry Documents.................................................................................................................2
1.3.2 Product Specific Documents....................................................................................................2
2Instalation ...............................................................................................................3
2.1 Preparation and Precaution for Installation ............................................................................3
2.2 Installation Instructions.............................................................................................................3
2.3 Connecting to Other Devices....................................................................................................4
2.3.1 AFDX Connection....................................................................................................................5
2.3.2 Trigger, Discrete and IRIG Connector.....................................................................................5
3Structure of the APE-FDX-2...................................................................................7
3.1 System on Chip (SoC) ...............................................................................................................9
3.1.1Ethernet MAC Features...........................................................................................................9
3.1.2 PCI-Express Bus and DMA Engine.........................................................................................9
3.1.3 IRIG- and Time Code Section................................................................................................10
3.1.3.1 IRIG-B Synchronization Unit.........................................................................................10
3.1.3.2 Timecode Encoder/Decoder .........................................................................................10
3.1.4 Application Specific Processor ..............................................................................................11
3.1.5 BIU Processor........................................................................................................................11
3.1.6 Memory Interface...................................................................................................................11
3.2 Gigabit Ethernet Phyter...........................................................................................................11
3.3 External Trigger Inputs and Outputs .....................................................................................12
3.4 User programmable Discrete I/O............................................................................................12
4Technical Data......................................................................................................15
5NOTES...................................................................................................................19
5.1 Acronyms..................................................................................................................................19
6Certificate of Volatility..........................................................................................21

APE-FDX-2 Hardware Manual
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LIST OF FIGURES
Table Title Page
Figure 2-1: Front panel View of APE-FDX-2....................................................................4
Figure 2-2: Pinout DSUB.................................................................................................6
Figure 3-1: APE-FDX-2 Block Diagram...........................................................................8
Figure 3-2: GPI/O APE-FDX-2 circuitry.........................................................................13
Figure 3-3: Discrete Protection with external resistor....................................................14
LIST OF TABLES
Figure Title Page
Table 2-1 Pin Assignment for AFDX................................................................................5
Table 2-2 Trigger, Discrete and IRIG Connector Pinout..................................................6
Table 3-1 Time Tag Format...........................................................................................10
.

1.Introduction
APE-FDX-2 Hardware Manual
1
1 INTRODUCTION
1.1 General
This document comprises the Hardware User’s Manual for the APE-FDX-2 PCIe Card.
The document covers the hardware installation, the board connections, the technical
data and a general description of the hardware architecture. For programming
information please refer to the according documents listed in the 'Applicable
Documents' section.
The APE-FDX-2 module is a member of AIM's family of advanced PCIe-Bus modules
for analysing, simulating, monitoring and testing of avionic Databus Systems.
The APE-FDX-2 module is used to simulate, monitor and inject protocol errors of AFDX
based network systems as well as common Ethernet networks with a data rate of
10/100/1000 Mbit/s. The implemented MAC features comprise two independent
transmitters and two independent receivers, each capable of transmitting or receiving
data at line rate concurrently. The transmitters feature multiple error injections and
timing possibilities with several start modes like start on IFG timing, start on absolute
timing, start on trigger events or grouping of frames to packets with packet group wait
timing. The receivers feature multiple error detection, time tagging of each received
frame with 100ns resolution, inter frame gap measurement with up to 40ns resolution
(1000Mbit: 8ns) and statistic features. Redundant operation of both ports is also
implemented with additional features like frame skew between both ports.
The hardware architecture provides ample resources (i.e. processing capability and up
to 3GByte of DDR3 memory) to guarantee, that all specified interface functions are
available concurrently and to full performance specifications.
The advanced architecture uses a SoC with integrated Dual-Core RISC processors,
tightly coupled to a large programmable logic. Core 1 of the Dual-Core processors is
running a Linux Operating system, supporting the Target Software application for high-
level protocol simulation and analysis. For fulfilling the real-time requirements of avionic
type networks, Core 2 is running a dedicated application for controlling the low-level
real-time functionality implemented within the programmable logic.
A freewheeling IRIG-B Time code Encoder/Decoder is implemented to satisfy the
requirements of 'multi-channel time tag synchronization' on the system level. The IRIG-
B compatible amplitude modulated sinewave output allows the synchronization of any
external module implementing IRIG-B time stamping.

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1.2 How This Manual is Organized
This APE-FDX-2 Hardware Manual is comprised of following sections.
Section 1 –Introduction - contains an overview of this manual.
Section 2 - Installation - describes the steps required to install the APE-FDX-2
device, and connect the device to other external interfaces including the
AFDX Network, IRIG-B, and triggers.
Section 3 - Structure of the APE-FDX-2 - describes the physical hardware
interfaces of the APE-FDX-2 using a block diagram and a description of
each main component
Section 4 - Technical Data - describes the technical specification of the
APE-FDX-2
1.3 Applicable Documents
The following documents shall be considered to be a part of this document to the extent
that they are referenced herein. In the event of conflict between the documents
referenced and the contents of this document, the contents of this document shall have
precedence.
1.3.1 Industry Documents
ARINC 664 - Aircraft Data Network - Part 7: Avionics Full Duplex Switched Ethernet
(AFDX) Network
PCI Express BUS Specification; PCI-SIG, Revision 2.0
1.3.2 Product Specific Documents
AIM - Reference Manual APE-FDX-2 Application Interface Library
Detailed description of the programming interface between the Host Carrier board and
the on-board driver software.