Aim APE-FDX-2 User manual

V01.00 Rev. A
June 2017
APE-FDX-2
10/100/1000Mbit
AFDX / ARINC664
Test and Simulation
Card Set for PCIe Bus
Hardware
Manual

APE-FDX-2 Hardware Manual
i
APE-FDX-2
10/100/1000Mbit
AFDX/ARINC664
Test and Simulation
Card Set for PCIe 2.0
V01.00 Rev. A
June 2017
AIM No.
60-151A0-16-0100-A
Hardware
Manual

APE-FDX-2 Hardware Manual
ii
AIM –Gesellschaft für angewandte Informatik und Mikroelektronik mbH
AIM GmbH
Sasbacher Str. 2
D-79111 Freiburg / Germany
Phone [phone]
Fax [phone]
[email protected]
AIM UK Office
Cressex Enterprise Centre, Lincoln Rd.
High Wycombe, Bucks. HP12 3RB / UK
Phone [phone]
Fax [phone]
[email protected]
AIM GmbH –Munich Sales Office
Terofalstr. 23a
D-80689 München / Germany
Phone [phone]
Fax [phone]
[email protected]
AIM USA LLC
Seven Neshaminy Interplex
Suite 211 Trevose, PA 19053
Phone [phone]
Fax [phone]
[email protected]
© AIM GmbH 2017
Notice: The information that is provided in this document is believed to be accurate.
No responsibility is assumed by AIM GmbH for its use. No license or rights are granted
by implication in connection therewith. Specifications are subject to change without
notice.

APE-FDX-2 Hardware Manual
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DOCUMENT HISTORY
The following table defines the history of this document.
Version
Cover Date
Created by
Description
V01.00 A
13.06.2017
M. Maier / D. Bau
First release

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THIS PAGE IS INTENTIONALLY LEFT BLANK

APE-FDX-2 Hardware Manual
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TABLE OF CONTENTS
Section Title Page
1Introduction ............................................................................................................1
1.1 General........................................................................................................................................1
1.2 How This Manual is Organized.................................................................................................2
1.3 Applicable Documents ..............................................................................................................2
1.3.1 Industry Documents.................................................................................................................2
1.3.2 Product Specific Documents....................................................................................................2
2Instalation ...............................................................................................................3
2.1 Preparation and Precaution for Installation ............................................................................3
2.2 Installation Instructions.............................................................................................................3
2.3 Connecting to Other Devices....................................................................................................4
2.3.1 AFDX Connection....................................................................................................................5
2.3.2 Trigger, Discrete and IRIG Connector.....................................................................................5
3Structure of the APE-FDX-2...................................................................................7
3.1 System on Chip (SoC) ...............................................................................................................9
3.1.1Ethernet MAC Features...........................................................................................................9
3.1.2 PCI-Express Bus and DMA Engine.........................................................................................9
3.1.3 IRIG- and Time Code Section................................................................................................10
3.1.3.1 IRIG-B Synchronization Unit.........................................................................................10
3.1.3.2 Timecode Encoder/Decoder .........................................................................................10
3.1.4 Application Specific Processor ..............................................................................................11
3.1.5 BIU Processor........................................................................................................................11
3.1.6 Memory Interface...................................................................................................................11
3.2 Gigabit Ethernet Phyter...........................................................................................................11
3.3 External Trigger Inputs and Outputs .....................................................................................12
3.4 User programmable Discrete I/O............................................................................................12
4Technical Data......................................................................................................15
5NOTES...................................................................................................................19
5.1 Acronyms..................................................................................................................................19
6Certificate of Volatility..........................................................................................21

APE-FDX-2 Hardware Manual
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LIST OF FIGURES
Table Title Page
Figure 2-1: Front panel View of APE-FDX-2....................................................................4
Figure 2-2: Pinout DSUB.................................................................................................6
Figure 3-1: APE-FDX-2 Block Diagram...........................................................................8
Figure 3-2: GPI/O APE-FDX-2 circuitry.........................................................................13
Figure 3-3: Discrete Protection with external resistor....................................................14
LIST OF TABLES
Figure Title Page
Table 2-1 Pin Assignment for AFDX................................................................................5
Table 2-2 Trigger, Discrete and IRIG Connector Pinout..................................................6
Table 3-1 Time Tag Format...........................................................................................10
.

1.Introduction
APE-FDX-2 Hardware Manual
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1 INTRODUCTION
1.1 General
This document comprises the Hardware User’s Manual for the APE-FDX-2 PCIe Card.
The document covers the hardware installation, the board connections, the technical
data and a general description of the hardware architecture. For programming
information please refer to the according documents listed in the 'Applicable
Documents' section.
The APE-FDX-2 module is a member of AIM's family of advanced PCIe-Bus modules
for analysing, simulating, monitoring and testing of avionic Databus Systems.
The APE-FDX-2 module is used to simulate, monitor and inject protocol errors of AFDX
based network systems as well as common Ethernet networks with a data rate of
10/100/1000 Mbit/s. The implemented MAC features comprise two independent
transmitters and two independent receivers, each capable of transmitting or receiving
data at line rate concurrently. The transmitters feature multiple error injections and
timing possibilities with several start modes like start on IFG timing, start on absolute
timing, start on trigger events or grouping of frames to packets with packet group wait
timing. The receivers feature multiple error detection, time tagging of each received
frame with 100ns resolution, inter frame gap measurement with up to 40ns resolution
(1000Mbit: 8ns) and statistic features. Redundant operation of both ports is also
implemented with additional features like frame skew between both ports.
The hardware architecture provides ample resources (i.e. processing capability and up
to 3GByte of DDR3 memory) to guarantee, that all specified interface functions are
available concurrently and to full performance specifications.
The advanced architecture uses a SoC with integrated Dual-Core RISC processors,
tightly coupled to a large programmable logic. Core 1 of the Dual-Core processors is
running a Linux Operating system, supporting the Target Software application for high-
level protocol simulation and analysis. For fulfilling the real-time requirements of avionic
type networks, Core 2 is running a dedicated application for controlling the low-level
real-time functionality implemented within the programmable logic.
A freewheeling IRIG-B Time code Encoder/Decoder is implemented to satisfy the
requirements of 'multi-channel time tag synchronization' on the system level. The IRIG-
B compatible amplitude modulated sinewave output allows the synchronization of any
external module implementing IRIG-B time stamping.

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1.2 How This Manual is Organized
This APE-FDX-2 Hardware Manual is comprised of following sections.
Section 1 –Introduction - contains an overview of this manual.
Section 2 - Installation - describes the steps required to install the APE-FDX-2
device, and connect the device to other external interfaces including the
AFDX Network, IRIG-B, and triggers.
Section 3 - Structure of the APE-FDX-2 - describes the physical hardware
interfaces of the APE-FDX-2 using a block diagram and a description of
each main component
Section 4 - Technical Data - describes the technical specification of the
APE-FDX-2
1.3 Applicable Documents
The following documents shall be considered to be a part of this document to the extent
that they are referenced herein. In the event of conflict between the documents
referenced and the contents of this document, the contents of this document shall have
precedence.
1.3.1 Industry Documents
ARINC 664 - Aircraft Data Network - Part 7: Avionics Full Duplex Switched Ethernet
(AFDX) Network
PCI Express BUS Specification; PCI-SIG, Revision 2.0
1.3.2 Product Specific Documents
AIM - Reference Manual APE-FDX-2 Application Interface Library
Detailed description of the programming interface between the Host Carrier board and
the on-board driver software.

2.Instalation
APE-FDX-2 Hardware Manual
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2 INSTALATION
2.1 Preparation and Precaution for Installation
The APE-FDX-2 features full PCIe Plug and Play capability, therefore, there are no
jumpers or switches on the board that require modification by the user in order to
interface to the PCIe bus.
It is recommended to use a wrist strap for any installations. If there is no wrist wrap
available, then touch a metal plate on your system to ground yourself and discharge any
static electricity during the installation work.
2.2 Installation Instructions
The following instructions tell how to install the APE-FDX-2 module in your system.
Please follow the instructions carefully, to avoid any damage on the device.
To Install the APE-FDX-2
1. Switch off your system and all peripheral devices.
2. Unplug the power cord from the wall outlet. (Inserting or removing
modules with power applied may result in damage to module devices).
3. Touch a metal plate on your system to ground yourself and discharge any
static electricity.
4. Remove the cover from your system.
5. Find a free peripheral slot in your system with suitable size for APE-FDX-2
card
Note: The APE-FDX-2 is a 1-Lane PCIe Card. This means, the card
mechanically fits at least in a 1-Lane PCIe Slot, but can also be plugged
into a slot with a higher lane count (e.g. 4-Lane, 8-Lane or 16-Lane).
Downward Compatibility to 1-Lane Host Slots depends on the Host Slot
mechanics, but is fully supported by the module.
Note: In some PC systems, there are PCIe Slots specially dedicated for
use as graphic adapter slot. These slots are not suitable to host the APE-
FDX-2 card.
6. Align the APE-FDX-2 card slot connector with the PCIe expansion slot and
gently lower the card into the free slot. Secure the card to the expansion
slot with the screw you removed from the metal plate.
7. Replace the cover of your system.
8. Connect the system to the power source. Turn on the power to your
system.

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2.3 Connecting to Other Devices
The external interfaces of the APE-FDX-2 consist of two RJ45 Ethernet connectors,
Trigger In/Out signal, Discrete IO signals, Ground as well as IRIG In/Out interface for
multi-channel time tag synchronization.
Green LED –Status
Good Link: Shows if one of the Ports has a valid Ethernet link.
Activity: Shows receive or transmit Port activity.
Red LED –Status
Failure: During board power up the Fail LED switches off if successfully booted.
Figure 2-1: Front panel View of APE-FDX-2
Ground
Discrete IO2
Discrete IO1
IRIG-Out
IRIG-In
RX Activity
Fail
Port 2
Port1
Discrete IO4
Trigger-Out2
Trigger-Out4
Trigger-In2
Trigger-In4
Trigger-Out1
Trigger-Out3
Trigger-In1
Trigger-In3
Discrete IO3
TX Activity
Good Link

2.Instalation
APE-FDX-2 Hardware Manual
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2.3.1 AFDX Connection
The AFDX connection is done via a standard RJ45 Ethernet connector located on the
Front panel of the APE-FDX-2 module.
2.3.2 Trigger, Discrete and IRIG Connector
For multi-channel time tag synchronization an input for the on-board IRIG-Decoder and
an output for inter-board synchronization is available. The output format is an AIM
specific IRIG coded signal.
The connector also provides four Trigger input/output signals, which can be used with
dedicated applications. Additional up to 4 users definable Discrete I/Os are placed on
the connector.
This connector is implemented by a 3 row 15pin, female HD-SUB Connector. Technical
Details about the Trigger and Discrete lines can be found later in this document.
Pin No.
Signal Description
10/100Mbit
Signal Description
1000Mbit
1
TX+
D1+
2
TX-
D1-
3
Rx+
D2+
4
N.C.
D3+
5
N.C.
D3-
6
Rx-
D2-
7
N.C.
D4+
8
N.C.
D4-
Table 2-1 Pin Assignment for AFDX

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The IRIG-IN and IRIG-OUT signals shall be connected depending on the time tag
method used as shown below.
1. Single AIM-Module no external IRIG-B source
No connection required
2. Multiple AIM-Modules with no common synchronization requirement
No connection required
3. Single or multiple AIM-Module(s) with external IRIG-B source
Connect external IRIG-B source to IRIG-IN and GND of all modules
4. Multiple AIM-Modules with no external IRIG-B source internally
synchronized.
Connect the IRIG-OUT signal and the GND of the module you have
chosen a as the time master to all IRIG-IN signals (including the time
master).
Pin No.
Signal
1
IRIG Input
2
IRIG Output
3
Discrete I/O 1
4
Discrete I/O 2
5
GND
6
Discrete I/O 3
7
Trigger Input 1
8
Trigger Output 1
9
Trigger Input 2
10
Trigger Output 2
11
Trigger Input 3
12
Trigger Output 3
13
Trigger Input 4
14
Trigger Output 4
15
Discrete I/O 4
Table 2-2 Trigger, Discrete and IRIG Connector Pinout
Figure 2-2: Pinout DSUB

3.Structure of the APE-FDX-2
APE-FDX-2 Hardware Manual
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3 STRUCTURE OF THE APE-FDX-2
The structure of the APE-FDX-2 board is shown in the block diagram on the next page.
The APE-FDX-2 comprises the following main sections:
System on a Chip design with
- Ethernet MAC
- PCIe2.0 Endpoint with DMA Engine
- IRIG-B Synchronisation Unit
- ASP Processor Core with Embedded Linux operating system
- BIU Processor
- Memory Interface
Physical IO-Interface
- Gigabit Ethernet PHY
Trigger IN / OUT
Discrete IO
QSPI Boot flash
I2C EEPROM

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Gigabit
Ethernet PHY
Gigabit
Ethernet PHY
RJ45
Transformer
RJ45
Transformer
Host
PCIe Endpoint
1 GB
Processor
RAM
PS Dual-
Core
PCIe 2.0 x1
Z015
Quartz &
Clock Buffer
IRIG
Maintenance
Connector
DMA
Data
Handler
NAND / QSPI
Boot Flash
Discretes
Trigger
IRIG
NOVRAM
2 GB
RX RAM
(optional)
ETH
MAC
ETH
MAC
Figure 3-1: APE-FDX-2 Block Diagram

3.Structure of the APE-FDX-2
APE-FDX-2 Hardware Manual
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3.1 System on Chip (SoC)
The main part of the design is implemented within a SoC of the latest generation. This
SoC contains a Dual-Core RISC Processor running at up to 800 MHz, dedicated
hardware interfaces like DDR3 RAM controller, a PCIe 2.0 Endpoint and several
programmable interfaces for communication and memory attachment.
Additionally, a large programmable logic is directly attached to the Processing System
within this SoC, so fast access from the processor to the programmable logic is
guaranteed.
3.1.1 Ethernet MAC Features
The Programmable Logic contains two fully independent AFDX- specific MAC´s. Each
can receive and transmit fully compliant AFDX frames.
The decoder in each MAC receives, analyses and stores data with a data rate of up to
1000 MBit per second. The gap between two frames is measured with a resolution of
8ns at 1000Mbit/s, 40ns at 100 MBit/s and 400ns at 10 MBit/s. Minimum possible gap
time is 48 ns in 1000Mbit operation mode, 480ns for 100Mbit and 4,8us for 10Mbit.
Each received message is checked for errors in the MAC header and the IP header and
for errors on the physical bus.
The transmitter operates fully independent from the receiver. The transmitter is capable
of generating data independent from the BIU Processor, time tag insertion as payload
and error generation. Additionally, each frame can be started on several events like
inter frame spacing, trigger events, absolute time or on packet group wait timing.
Redundant operation of receiver and transmitter is also supported with additional
features like individual frame skew between the two ports.
3.1.2 PCI-Express Bus and DMA Engine
The FPGA architecture of AIM´s family of PCI Express based modules includes as Host
Interface a 1-lane PCIe 2.0 endpoint that provide 500 Mbyte/s upstream and
downstream bandwidth, concurrently. This State-of-the-Art Interface is commonly used
in modern PC Systems and provides enough performance to reach the necessary
bandwidth for the two 1GBit Ethernet Interfaces.
The FPGA logic includes independent DMA units for each Transmitter and Receiver.
The DMA engine will transfer TX data from Host memory to On-Board memory and
Receiver data from On-Board memory to Host memory. This is done fully independent
from any processor interaction to ensure maximum performance.

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3.1.3 IRIG- and Time Code Section
The main functions of the Time Code Processor (TCP) are:
a. IRIG-B compatible Time Code Decoder function
b. Time Code Encoder –IRIG-B compatible Time Encoder function
3.1.3.1 IRIG-B Synchronization Unit
The supported IRIG Time Code Format is B122.
B Bit Rate =100Hz, Bit Time = 10ms,
Bits/Frame =100, Frame Time = 1000mS, Frame Rate = 1Hz
1 Modulation type=Sine wave Carrier, amplitude modulated
2 Carrier Frequency = 1kHz (1ms resolution)
2 BCD coded
The time code information can be used for time-tagging and multi-channel
synchronization.
3.1.3.2 Timecode Encoder/Decoder
On the APE-FDX-2 a freewheeling IRIG function is implemented. If no external IRIG
signal is detected, the IRIG Decoder switches automatically to the freewheeling
operation mode. If an external IRIG-B signal is detected in freewheeling mode, the Time
Tag is automatically synchronized to this external IRIG-B signal.
The time tag on the board is generated in the format shown below.
Time Element
Number of bits
DAYS of year
9
HOURS of Day
5
MINUTES of Hour
6
SECONDS of Minute
6
MICROSECONDS
of Second
20
100ns of Microsecond
4
Summary
50 (7 Bytes, stored in two 32bit words)
Table 3-1 Time Tag Format

3.Structure of the APE-FDX-2
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3.1.4 Application Specific Processor
Core 1 of the Dual Core Processor acts as Application Specific Processor and runs an
embedded Linux operating system.
The ASP performs the followed main tasks:
Setup of the SoC resources (DDR3 RAM, MMU, PCIe etc.)
Load Programmable Logic and starts second BIU core
Setup Receive and Transmit DMA machines in the PL
Relieve the Host system, fasten up the board and expands the capability of the
APE-FDX-2 module to a high level instrument.
3.1.5 BIU Processor
Core 2 of the Dual Core Processor is used as Bus Interface Processor (BIP) and
handles the real time critical control of the two AFDX ports.
The BIP performs the following tasks:
Execute a Frontend Selftest on Power Up
Service the AFDX-MAC to handle the bus traffic in real time
Support the ASP with Pre-Filtering and Analysis of received data
Support special transmit modes like redundant transmit or Simulation mode
3.1.6 Memory Interface
The SoC has a dedicated 1GByte DDR3 RAM directly attached to it, storing the
executable code and application specific data buffering. Due to its close attachment
over several AXI Bus Interfaces to the programmable logic, the access latency is
minimized.
For 1000Mbit Mode an additional 2GByte DDR3 RAM is available to extend the
recording capability. This memory is solely used by the MAC for storing receiver data.
3.2 Gigabit Ethernet Phyter
The Frontend Interface is realised using a Gigabit Ethernet Phyter of the latest
generation. Besides the Ethernet specific sender and receiver features, the Phyter offer
automatic MDI/MDIX crossover at all speeds of operation, different selftest features,
and a powerful frontend interface for reaching highest cable length.
In standard mode, the Auto negotiation is switched of, and the speed is user selectable
via software. If necessary the Auto negotiation can be switched on via software.

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3.3 External Trigger Inputs and Outputs
For external triggering, separate trigger input and trigger output lines are provided. Each
Trigger I/O can be mapped via software to a MAC or a dedicated functionality within the
MAC. Inputs can be used for example to start or stop the receiver, or to start the sender.
Outputs can be mapped for example to complex Filter and Trigger function blocks within
the PL / BIU Firmware and signal user definable events.
The minimum input trigger pulse length must be greater than 75 nanoseconds to be
detected. The trigger inputs are high active and their voltage level is of type TTL and is
+5.0V tolerant. Varistors on the Front IO are placed nearby connector to suppress
peaks of glitches (ESD sparks).
3.4 User programmable Discrete I/O
The APE-FDX-2 module provides four user definable discrete I/O signals. Discrete input
signals are always active whereas the discrete output signals are per default inactive.
An open collector circuitry is used for the discrete output with approximately 4V
provided by default. An external voltage from 0 to 35V can be supplied externally for
switching higher voltages.
Please Note:
The discrete outputs don’t provide a series resistor for over current protection. In case a
discrete input is used, make sure that the output-mode for that discrete is disabled,
before connecting an external voltage, otherwise a high short circuit current to GND can
damage the output transistor.