Allegro A8582 Quick start guide

Page 1 of 10 April 29, 2011
Demo Note for the A8582
Evaluation Board
4.7VIN – 40VIN, 3.3VOUT, 2.0A, 2MHz
Asynchronous Buck Regulator

Page 2 of 10 April 29, 2011
GENERAL SPECIFICATIONS
Specification Min Nom Max Units
Absolute Maximum Input Voltage –0.3 −40 Volts
Operating Input Voltage Range 4.7 12 36 Volts
VIN START Threshold, VIN rising −4.2 4.6 Volts
VIN STOP Threshold, VIN falling −3.8 4.2 Volts
Output Voltage (FB: 5.23K/16.5K, ±1%) 3.20 3.32 3.44 Volts
Steady-State Output Current (12VIN) −2.0 2.5 A
Pulse-by-pulse Current Limit @ 30% 2.6 −3.4 A
Enable/Synchronization Input –0.3 −5.5 Volts
OPERATING INSTRUCTIONS
Input Power Connection:
Connect a 12V power supply from Vin to GND that is capable of at least 2A. Once
operational, VIN can fall as low as 3.8VTYP (4.2VMAX) before the A8582 is reset.
Enable Input Connection:
Connect an Enable signal from EN/SYNC to GND. If the EN/SYNC input voltage is higher
than 1.8V the A8582 will be enabled. If the EN/SYNC input voltage is lower than 0.8V the
A8582 will be disabled. Also, EN/SYNC may be used to simultaneously enable the A8582 and
synchronize the PWM switching frequency by applying a square wave above 2.2MHz.
Note: Continuously applying more than 5.5V to the EN/SYNC pin may damage the A8582.
Output Load Connections:
Connect a load from VOUT to GND. The steady-state load current can be as high as 2.0A. Pulse-
by-pulse current limit and/or thermal shutdown will occur if the load is greater than 4.75A.
DEMO BOARD PICTURE

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DEMO BOARD SCHEMATIC
RFSET
11.5K
RZ
15.4K
0603
50V
Cboot
100nF
A1
C
2
SMA
D1
B340A
0603
CP
10pF
0603
CZ
820pF
RS1
16.5K
RS 2
5.23K
1206
16V
CO 2
Emp ty
IHLP2020BZER3R3M01
5.2mm x 5.5mm
LO
2.2uH
50V
1210
CI N 2
Emp ty
VOUTSW
TP1
Vin TP7 SW
TP2
GND
TP1 1
Vout
TP1 3
GND
VIN
EN/Sync
TP14 GND
TP15 GND
12Vin / 3.3Vout: RFB1 = 16. 5K, RFB2 = 5. 23K
15.4K, 820pF, 4.7pF: 120KHz BW, 72deg PM
A8582 Evaluation PCB
50V
8mm
C1
47uF
11.5K = 2MHz
TP6
CO MP
50V
1210
CI N 1
3.3uF
RF B1
16.5K
RFB2
5.23K
0603
CSS
22nF
TP3
EN/SYNC
xxV
8mm
CO 3
Emp ty
1206
16V
CO 1
10uF
RPU
100K
SW 15
Vi n
1SW 16
Vi n
2
BOOT 14 GND
5
FBX 10
Vi n
3
0
GND
12
E N/ SYNC
7
SS
4
FSET
8
COMP
11
NC
13
FB 9
POK 6
U1
A8582
TP9
FBX
TP1 0
FB
TP1 2
POK
TP4
SS
TP5
FSET
TP8
BOOT
TP16 GND
TP17 GND
0603
50V
CFBX
120pF
Bo d e
Emp ty Rsnub 4.7
0603
Csn u b
470pF
SW
RPD
Emp ty
RPD should be used if Vout > 5.5V
Rb o o t
Emp ty
Snubber on bottom of PCB
Note: C1 is an optional, bulk, electrolytic capacitor for general supply filtering
DEMO BOARD BILL-OF-MATERIALS

Page 4 of 10 April 29, 2011
DEMO BOARD PERFORMANCE

Page 5 of 10 April 29, 2011

Page 6 of 10 April 29, 2011
12Vin, 2.0A Load: 0dB at 140KHz, PM=59.8deg, GM=13.7dB
Iout
(A)
A8582
(deg C)
D1
(deg C)
Lo
(deg C)
0.25 31.3 31.0 29.5
0.5 34.8 35.4 32.5
1.0 39.9 42.9 37.2
1.5 44.9 50.6 42.8
2.0 50.9 58.6 49.3
2.5 57.7 67.8 57.3
Shorted Vout 30.0 34.9 29.0
Component Temperatures vs Load Current
12Vin, 3.3Vout, 2MHz, TAMB=25deg C
No Airflow (still air)

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Startup
12Vin, 2.2A (1.5Ω) load
CH1=Vout, CH2=COMP, CH3=EN, CH4=SS
Shutdown
12Vin, 2.2A (1.5Ω) load
CH1=Vout, CH2=COMP, CH3=EN, CH4=SS
Output Voltage Ripple
12Vin, 2.2A (1.5Ω) load
CH1=Vout (20mV/DIV)
Transient Response
12Vin, 0.4A to 1.5A (1.1A step)
CH1=Vout, CH2=COMP, CH4=Iout

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SWN Voltage at 12Vin, 150mA load
CH1=SWN (5V/DIV), 200ns/DIV
SWN Voltage at 12Vin, 2.2A load
CH1=SWN (5V/DIV), 200ns/DIV
Input Voltage Ripple at 12Vin, 2.2A load
CH1=Vin across CIN1 (50mV/DIV)
Output Shorted, Hiccup Mode Operation
CH1=Vout, CH2=COMP, CH3=SS, CH4=IL

Page 9 of 10 April 29, 2011
DEMO PCB LAYOUT:
Top Layer and Top Silk
Layer 2 and Top Silk

Page 10 of 10 April 29, 2011
Layer 3 and Top Silk
Bottom Layer and Top Silk