Altera Stratix III Instruction Manual

Altera Corporation 1
AN-469-1.1
Application Note 469
Stratix III Design Guidelines
Introduction Stratix®III devices are engineered for high-speed core performance and
high-speed I/O with the best signal integrity in the industry, combined
with low-static and dynamic-power consumption. The devices also offer
increased logic density, so you can integrate more of your product to
reduce cost and board space.
It is important to follow Altera recommendations throughout the design
process for high-density, high-performance Stratix III designs. Planning
the FPGA and system early in the design process is crucial to your
success. This document provides an easy-to-use set of guidelines and a
list of factors to consider in Stratix III designs, but does not include all the
details about the product. It includes pointers to other documentation
where you can find detailed specifications, device feature descriptions,
and additional guidelines. The material covers the Stratix III device
architecture as well as aspects of the Quartus®II software and third-party
tools that you might use in your design.
The guidelines presented in this document will help you improve
productivity and avoid common design pitfalls. The document discusses
various stages of the design flow in the order that each stage is typically
performed, as shown in Table 1. You can use the “Design Checklist,” on
page 65 to help verify that you have followed each of the guidelines.
Table 1. Summary of Design Flow Stages and Guideline Topics (Part 1 of 2)
Stages of Design Flow Guideline Topics
“Device Selection,” on page 2 Device information, determining device density, package
offerings, speed grade, core voltage, migration, and
HardCopy®ASICs
“Planning for Device Configuration,” on page 6 Configuration scheme overview, configuration features,
Quartus II settings, optional pins
“Early System Planning,” on page 12 Planning: design specifications, IP selection, on-chip
debugging, early power estimation
“Board Design Considerations,” on page 18 Power-up, power pins, configuration pins, signal integrity,
board-level verification
“I/O and Clock Planning,” on page 27 Pin assignments, early pin planning, I/O features and
connections, clock and PLL selection, SSN
“Design and Compilation,” on page 42 Synthesis tools, coding styles and recommendations, planning
for hierarchical or team-based design, SOPC Builder
May 2008, version 1.1

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Application Note 469: Stratix III Design Guidelines
fFor complete details about the Stratix III device architecture, refer to the
Stratix III Literature page. For the latest known issues related to
Stratix III FPGAs, refer to the Stratix III Device Family Errata Sheet and the
Knowledge Database.
Device Selection The first step in the Stratix III design process is to choose the device
family variant, device density, speed grade, package, and core voltage
that best suit your design needs. You should also consider whether you
want to target FPGA or ASIC migration devices. Before you begin
compiling a design in a third-party synthesis tool or the Quartus II
software, set the correct target device.
fFor information about the features available in each device density,
including logic, memory blocks, multipliers, and phase-locked loops
(PLLs), as well the various package offerings and I/O pin counts, refer to
the Stratix III Device Family Overview chapter in volume 1 of the Stratix III
Device Handbook.
Logic, Memory, and Multiplier Density
The Stratix III logic family (L) offers balanced logic, memory, and
multipliers to address a wide range of applications, while the enhanced
family (E) offers more memory and multipliers per logic and is ideal for
wireless, medical imaging, and military applications. Choose the device
family variant with the best resource balance for your design
requirements.
Stratix III devices offer a range of densities that provide different amounts
of device logic resources, including memory, multipliers, and adaptive
logic module (ALM) logic cells. Different device densities may also offer
different numbers of features such as PLLs. Determining the required
logic density can be a challenging part of the design planning process.
Devices with more logic resources can implement larger and potentially
more complex designs, but generally have a higher cost. Smaller devices
have lower static power utilization. Select a device that meets your design
needs with some safety margin, in case you want to add more logic later
in the design cycle, or to upgrade or expand your design. You might also
“Timing Closure and Verification,” on page 50 Device utilization, timing constraints and analysis, area and
timing optimization, verification
“Power Analysis and Optimization,” on page 57 Analysis tools, optimization techniques, thermal management
options
Table 1. Summary of Design Flow Stages and Guideline Topics (Part 2 of 2)
Stages of Design Flow Guideline Topics

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Application Note 469: Stratix III Design Guidelines
want additional space in the device to ease creating a design floorplan for
incremental or team-based design, as described in “Planning for
Hierarchical and Team-Based Design,” on page 47. Consider reserving
resources for debugging, as described in “Planning for On-Chip
Debugging,” on page 13. Stratix III devices support vertical migration
between certain device densities, which provides flexibility as described
in “Vertical Device Migration,” on page 3.
Many next-generation designs use a current design as a starting point. If
you have other designs that target an Altera device, you can use their
resource utilization as an estimate for your new design. Compile existing
designs in the Quartus II software with the Auto device selected by the
Fitter option in the Settings dialog box. Review the resource utilization to
find out which device density fits the design. Keep in mind that coding
style, device architecture, and the optimization options used in the
Quartus II software can significantly affect a design’s resource utilization
as well as timing performance. Refer to “Device Resource Utilization
Reports,” on page 51, for more information about determining resource
utilization.
To obtain resource utilization estimates for certain configurations of
Altera’s intellectual property (IP) designs, refer to the user guides for
Altera®megafunctions and IP MegaCores on the IP Megafunctions page
in the Literature section at www.altera.com. You can use these numbers
to help estimate the resource utilization of your design.
I/O Pin Count and Package Offering
Stratix III devices are available in space-saving FineLine®BGA packages
with various I/O pin counts. Certain package sizes support vertical
migration within different device densities, as described in “Vertical
Device Migration”. Determine the required number of I/O pins,
considering the design’s interface requirements with other system blocks.
You can compile any existing designs in the Quartus II software with the
Auto device selected by the Fitter option in the Settings dialog box to
determine how many input and output pins are used. Also consider
reserving pins for debugging, as described in “Planning for On-Chip
Debugging,” on page 13.
Vertical Device Migration
Stratix III devices support vertical migration within the same package,
which enables you to migrate to different density devices whose
dedicated pins, configuration pins, and power pins are the same for a
given package. This feature allows future upgrades or changes to your
design without any changes to the board layout, because you can replace
the Stratix III device on the board with a different density Stratix III

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Application Note 469: Stratix III Design Guidelines
device. You can migrate from the L logic family to the E enhanced family
without increasing the amount of logic available, which minimizes the
cost of vertical migration.
Determine whether you want the option of migrating your design to
another device density. Choose your device density and package to
accommodate any possible future device migration to allow flexibility
when the design nears completion. You should specify any potential
migration options in the Quartus II software at the beginning of your
design cycle. Selecting a migration device impacts the design’s pin
placement to ensure that your design is compatible with the selected
device(s). It is possible to add migration devices later in the design cycle,
but it requires extra effort to check pin assignments, and can require
design or board layout changes to fit into the new target device. It is easier
to consider these issues early in the design cycle than at the end, when the
design is near completion and ready for migration. To specify the target
migration devices, on the Assignments menu, click Device and in the
Settings dialog box, select Migration Devices.
As described in “Making FPGA Pin Assignments,” on page 28, the Pin
Migration view in the Quartus II Pin Planner highlights pins that change
function in the migration device when compared to the currently selected
device.
HardCopy III ASIC Migration
The HardCopy methodology allows you to seamlessly prototype your
system with Stratix III FPGAs and completely prepare your system for
production, prior to ASIC design handoff. Altera’s HardCopy Design
Center uses a proven turnkey process to implement the low-cost,
low-power, functionally-equivalent, pin-compatible HardCopy III ASIC.
The result is a drop-in replacement to the prototyping Stratix III FPGA on
your system board.
You can start your HardCopy III ASIC design by targeting your design to
an appropriate Stratix III FPGA and choosing the appropriate
HardCopy III ASIC companion in the latest version of the Quartus II
software.
You can migrate between the FPGA and ASIC revisions of your project
when the Quartus II software includes these devices.

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Application Note 469: Stratix III Design Guidelines
If you use a HardCopy device, review the HardCopy guidelines early in
the design cycle for any Quartus II software settings that should use or
other restrictions you should consider as you complete your design. For
example:
■HardCopy III devices use a 0.9-V core voltage (VCCL). So if you use a
1.1-V Stratix III device, your board design must accommodate a core
voltage change between devices.
■HardCopy devices do not support a 3.3-V VCCIO, so you should use
3.0-V or less in the Stratix III device as well.
■RAM cannot be initialized to a known value in the HardCopy ASIC
like in an FPGA. Therefore, if you plan to migrate to a HardCopy
device, your design must write RAM contents during device
operation instead of relying on memory initialization values.
■It is especially important to use complete timing constraints if you
want to migrate to a HardCopy device because of the rigorous
verification requirements for ASICs.
■Altera recommends adding the PLL reconfiguration megafunction to
your design so that you can change the PLL settings in-system on the
HardCopy III device.
fFor more information, refer to the Phase-Locked Loops
Reconfiguration Megafunction User Guide
(ALTPLL_RECONFIG).
In addition, review the HardCopy Readiness Report that is generated
during compilation when a HardCopy companion device is selected in
the Device Settings. This advises you about any incomplete I/O
assignments and provides recommendations for clock pin locations.
fFor more information and guidelines for HardCopy migrations, refer to
the HardCopy Series Handbook.
Speed Grade
The device speed grade affects the device timing performance and timing
closure, as well as power utilization. Stratix III devices are available in
three speed grades, –2, –3, and –4 (–2 is the fastest). Generally, the faster
devices have higher cost. As one way to help you determine which speed
grade your design requires, refer to the supported clock rates for specific
I/O interfaces.
fFor information about supported clock rates for memory interfaces using
I/O pins on different sides of the device in different device speed grades,
refer to the External Memory Interfaces in Stratix III Devices chapter in
volume 1 of the Stratix III Device Handbook.

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Application Note 469: Stratix III Design Guidelines
Some designers use the fastest speed grade during prototyping to reduce
compilation time (because less time is spent optimizing the design to
meet timing requirements), and then move to a slower speed grade for
production to reduce cost if the design meets its timing requirements.
The Quartus II software optimizes and analyzes your design using
different timing models for each speed grade. If you migrate to a device
with a different speed grade, you must perform timing analysis to ensure
that there are no timing violations resulting from changes in timing
performance.
Selectable Core Voltage
Selectable core voltage gives you the option of using a 0.9-V core voltage
which increases the static and dynamic power savings compared to the
standard 1.1-V core voltage. Designs requiring the highest performance
should use the 1.1-V core voltage, while designs requiring minimum
power consumption can use the 0.9-V core voltage. Choose the core
voltage along with the device and speed grade in the Quartus II software,
because the selectable core voltage affects the Stratix III fabric
performance. The Quartus II software uses timing and power models
specific to the selected core voltage to implement all timing-dependent
and power-dependent analysis, and optimization.
If you use the low-power voltage setting, ensure that the 0.9-V option is
available for your device density, package, and speed grade combination.
There is limited speed grade support with the 0.9-V option.
Planning for
Device
Configuration
Stratix III devices are based on SRAM cells, and you must download
configuration data to the Stratix III device each time the device powers up
because SRAM memory is volatile. Choosing your device configuration
method early allows system and board designers to determine what
companion devices, if any, are needed for your system. Your board layout
also depends on the configuration method you plan to use for the
programmable device, because different schemes require different
connections. For board design guidelines related to configuration pins,
refer to “Board Design Considerations,” on page 18.
In addition, Stratix III devices offer configuration data decompression to
save configuration memory space and time, design security using data
encryption to protect your designs, and real-time remote system
upgrades. Support for these configuration features varies depending on
your configuration scheme. Stratix III devices also include optional
configuration pins and a reconfiguration option that you should choose
up front and set up in the Quartus II software, so that you have all the
information required for your board and system design.

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Application Note 469: Stratix III Design Guidelines
This section includes the following topics:
■“Configuration Scheme Selection”
■“Configuration Features,” on page 9
■“Quartus II Configuration Settings,” on page 10
■“Configuration and Programming Files,” on page 11
fFor more information about configuration, refer to the Configuring
Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook.
For more information, refer to the Configuration Center. This web page
includes links to JTAG Configuration & ISP Troubleshooter and FPGA
Configuration Troubleshooter that you can use to help debug
configuration problems.
Configuration Scheme Selection
You can configure Stratix III devices using one of four configuration
schemes:
■Fast passive parallel (FPP)
■Fast active serial (AS)
■Passive serial (PS)
■Joint Test Action Group (JTAG)
Select the configuration scheme by driving the Stratix III device MSEL
pins either high or low.
fFor more information about the supported configuration schemes, refer
to the Stratix III Device Configuration Center. For complete information
about the Stratix III supported configuration schemes, how to execute
the required configuration schemes, and all of the necessary option pin
settings, including the MSEL pin settings, refer to the Configuring
Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook.
All configuration schemes use a configuration device, a download cable,
or an external controller (for example, a MAX®II device or
microprocessor).
Configuration Devices
You can use the Altera enhanced configuration devices (EPC) in the FPP
and PS configuration schemes. The Altera serial configuration devices
(EPCS) are used in the Fast AS configuration scheme. Check whether the
configuration device supports the configuration bitstream file size for
your Stratix III device. You can also use a MAX II device or a

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Application Note 469: Stratix III Design Guidelines
microprocessor with a flash memory configuration method, or use the
compression feature to reduce the configuration file size of large
Stratix III devices.
fFor information about enhanced configuration devices, refer to the
Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet and
the Altera Enhanced Configuration Devices chapters in volume 2 of the
Configuration Handbook. For information about serial configuration
devices, refer to the Serial Configuration Devices (EPCS1, EPCS4, EPCS16,
EPCS64, and EPCS128) Data Sheet in volume 2 of the Configuration
Handbook. This datasheet includes a table that lists serial configuration
device support for Stratix III devices. If the uncompressed file size is too
large for a specific device density, the table indicates that it includes the
compression feature to reduce the file size.
Serial configuration devices do not directly support the JTAG interface;
however, you can program the device with JTAG download cables using
the Serial FlashLoader (SFL) feature in the Quartus II software. This
feature uses the FPGA as a bridge between the JTAG interface and the
configuration device, allowing both devices to use the same JTAG
interface.
1This solution is slower than standard AS configuration schemes
because the SFL solution must configure the FPGA before
programming configuration devices.
fFor more details about the SFL, refer to AN 370: Using the Serial
FlashLoader with the Quartus II Software.
Download Cables
The Quartus II programmer supports configuring Stratix III devices
directly using PS or JTAG interfaces via Altera programming download
cables. You can download design changes directly to the device with
Altera download cables, making prototyping easy and enabling you to
make multiple design iterations in quick succession. You can use the same
download cable to program configuration devices on the board and use
JTAG debugging tools such as the SignalTap II Logic Analyzer.
fFor more information about how to use Altera’s current download
cables, refer to the following documents:
■ByteBlaster II Download Cable User Guide
■USB Blaster II USB Port Download Cable User Guide
■EthernetBlaster Communications Cable User Guide

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Application Note 469: Stratix III Design Guidelines
MAX II Parallel Flash Loader
If your system already contains common flash interface (CFI) flash
memory, you can utilize it for Stratix III device configuration storage as
well. The parallel flash loader (PFL) feature with MAX II devices allow
you to program CFI flash memory devices through the JTAG interface. It
also provides the logic to control configuration from the flash memory
device to the Stratix III device and supports compression to reduce the
size of your configuration data. Both PS and FPP configuration modes are
supported using this PFL feature. If you choose this configuration
method, you should check the list of supported flash devices early in your
system design cycle and plan accordingly.
fFor more information about PFL, refer to AN 386: Using the Parallel Flash
Loader with the Quartus II Software.
Configuration Features
This section describes Stratix III configuration features and how they
affect your design process: data compression, design security, and remote
system upgrades.
Data Compression
When you enable data compression, the Quartus II software generates
configuration files with compressed configuration data. This compressed
file reduces the storage requirements in the configuration device or flash
memory, and decreases the time needed to transmit the bitstream to the
Stratix III device. The time required by a Stratix III device to decompress
a configuration file is less than the time needed to transmit the
configuration data to the device. Stratix III devices support
decompression in the FPP (when using a MAX II device/microprocessor
+ flash), fast AS, and PS configuration schemes. The Stratix III
decompression feature is not available in the FPP (when using enhanced
configuration device) or JTAG configuration schemes.
fFor more information about data compression, refer to the Configuring
Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook.
Design Security Using Configuration Bitstream Encryption
The design security feature ensures that Stratix III designs are protected
from copying, reverse engineering, and tampering using configuration
bitstream encryption. The design security feature is available when
configuring Stratix III devices using the fast passive parallel (FPP)
configuration mode with an external host (such as a MAX II device or
microprocessor), or when using fast active serial (AS) or passive serial

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Application Note 469: Stratix III Design Guidelines
(PS) configuration schemes. The design security feature is also available
in remote update with fast AS configuration mode. The design security
feature is not available when you are configuring your Stratix III device
using FPP with an enhanced configuration device or JTAG configuration
schemes.
fFor more information about design security using configuration
bitstream encryption, refer to the Design Security in Stratix III Devices
chapter in volume 1 of the Stratix III Device Handbook.
Remote System Upgrades
Stratix III devices support remote update in the AS configuration scheme.
You can implement remote update in conjunction with real-time
decompression of configuration data if you need to save configuration
memory space in the serial configuration device with AS configuration.
To implement the remote system upgrade interface, you can use the
ALTREMOTE_UPDATE megafunction or instantiate a remote system
upgrade atom.
fFor more information about making remote system upgrades, refer to
the Remote System Upgrades with Stratix III Devices chapter in volume 1 of
the Stratix III Device Handbook. For more information about the
altremote_update megafunction, refer to the Remote Update Circuitry
Megafunction User Guide (ALTREMOTE_UPDATE).
Quartus II Configuration Settings
This section covers several configuration options that you can set in the
Quartus II software before you compile to generate configuration or
programming files. Your board and system design are affected by these
settings and pins.
Optional Configuration Pins
You can enable the following optional configuration pins on the General
tab of the Device and Pin Options dialog box:
■CLKUSR pin—The Enable user-supplied start-up clock (CLKUSR)
option enables you to select which clock source is used for
initialization, either the internal oscillator or an external clock
provided on the CLKUSR pin.

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Application Note 469: Stratix III Design Guidelines
■INIT_DONE pin—To check if the device has completed initialization
and is in user mode, you can monitor the INIT_DONE pin. Enable the
pin with the Enable INIT_DONE output option. The INIT_DONE
pin is an open-drain output and requires an external pull-up to
VCCPGM.
Restart Configuration after Error
You can enable the Auto-restart after configuration error option on the
General tab of the Device and Pin Options dialog box. With this option,
when a configuration error occurs, the device drives nSTATUS low, which
resets the device internally. The device releases its nSTATUS pin after a
reset time-out period. The nSTATUS pin requires an external 10-kΩ
pull-up resistor to VCCPGM, unless it is connected to an external
configuration device which provide an internal pull-up.
Configuration and Programming Files
This section presents information related to the configuration and
programming files used for the Stratix III device and any companion
devices.
fFor more information about programming file formats and using the
programmer, refer to the Quartus II Programmer chapter in volume 3 of
the Quartus II Handbook.
Programming Files
To store the Stratix III data in configuration devices, you can generate
additional files or convert the default SRAM Object File (.sof) data into a
different file format to program a configuration device. You can set up the
software to generate additional programming files during compilation in
the Device and Pin Options dialog box. To convert the .sof file, on the File
menu, click Convert Programming Files. Programmer Object Files (.pof)
and JTAG Indirect Configuration files (.jic) files are used with the
Quartus II Programmer to program configuration devices, while the
Hexout (.hexout), raw binary file (.rbf), Tabular Text File (.ttf), and .rpd
files are used with other programmers.
When working with multi-device configuration chains, combine each
device’s .sof file into one configuration file in the Convert Programming
Files dialog box. When you set up the single configuration file, list the
configuration files in the same order as the devices on the board.

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Application Note 469: Stratix III Design Guidelines
Estimating Configuration File Sizes
The uncompressed .rbf file size provides the approximate uncompressed
configuration file sizes for Stratix III devices. To calculate the amount of
storage space required for multiple device configuration, add the file size
of each device together.
Use the data on the uncompressed raw binary file sizes only to estimate
the file size before design compilation. Different configuration file
formats, such as Hexadecimal (.hex) or TTF format, have different file
sizes. However, for any specific version of the Quartus II software, any
design targeted for the same device has the same uncompressed
configuration file size.
Stratix III devices can receive a compressed configuration bitstream and
decompress this data in real-time, reducing storage requirements and
configuration time in active serial and passive serial schemes. If you are
using compression, the file size can vary after each compilation because
the compression ratio is dependent on the design.
Early System
Planning
In systems that contain a Stratix III device, the FPGA typically plays a
large role in the overall system and affects the rest of the system design.
Providing FPGA device information early in the design process, before
you have completed your design in the Quartus II software, enables
earlier planning for the system and board design. It is important to start
the design process by creating detailed design specifications. You must
decide important aspects of your FPGA that affect the system design,
including IP, and on-chip debugging methodologies. You can also
perform early power estimation to provide information to PCB board and
system designers before you have created any source code, or when you
have a preliminary version of the design. This section includes the
following topics:
■“Creating Design Specifications,” on page 12
■“IP Selection,” on page 13
■“Planning for On-Chip Debugging,” on page 13
■“Early Power Estimation,” on page 16
Creating Design Specifications
Before you create your logic design or complete your system design, you
should have detailed design specifications. The specifications define
what the system should do, specify the I/O interfaces for the FPGA, and
include a block diagram of basic design functions. Refer to “IP Selection”
for suggestions about including intellectual property blocks. Taking the
time to create these specifications will help improve design efficiency.

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Application Note 469: Stratix III Design Guidelines
Creating a test plan at this phase can also help you design for testability
and design for manufacturability. For example, do you want to perform
any built-in-self test functions to drive interfaces? If so, you could use a
UART interface with a Nios®II processor inside the FPGA device. You
might require the ability to validate all the design interfaces. Refer to
“Planning for On-Chip Debugging,” on page 13 for guidelines related to
analyzing and debugging the device after it is in the system.
If your design includes multiple designers, it is useful to consider a
common design directory structure. This eases the design integration
stages. “Planning for Hierarchical and Team-Based Design,” on page 47
provides more suggestions for team-based designs.
IP Selection
Altera and its third-party IP partners offer a large selection of off-the-shelf
IP cores optimized for Altera devices. You can easily implement these
parameterized blocks of IP in your design, reducing your system
implementation and verification time, and allowing you to concentrate
on adding proprietary value. IP selection often affects system design,
especially where the FPGA interfaces with other devices in the system.
Consider which I/O interfaces or other blocks in your system design can
be implemented using IP cores, and plan to incorporate these cores in
your FPGA design.
The OpenCore Plus feature available for many IP cores allows you to
program the FPGA to verify your design in hardware before you
purchase the IP license. The evaluation supports an untethered mode, in
which the design runs for a limited time, or a tethered mode. The tethered
mode requires an Altera serial JTAG cable connected between the JTAG
port on your board and a host computer running the Quartus II
Programmer for the duration of the hardware evaluation period. If you
plan to use the tethered mode, ensure that your board design supports
this mode of operation.
fFor descriptions of available IP cores, refer to the Intellectual Property
page under Products on Altera’s website.
Planning for On-Chip Debugging
On-chip debugging is an optional step in the design flow, and different
debugging tools work better for different systems and different
designers. Evaluate on-chip debugging options early in your design
process to ensure that your system board, Quartus II project, and design
are able to support the appropriate options. Planning can reduce time
spent debugging, and you will not have to make changes later to
accommodate your preferred debugging methodologies. Adding debug

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Application Note 469: Stratix III Design Guidelines
pins may not be enough, because of internal signal accessibility and I/O
pin accessibility on the device. First, select your preferred debugging
tool(s) described in“On-Chip Debugging Tools” and then refer to
“Planning Guidelines for Debugging Tools,” on page 15.
On-Chip Debugging Tools
The Quartus II portfolio of verification tools includes the following
in-system debugging features:
■SignalProbe incremental routing—This feature makes design
verification more efficient by quickly routing internal signals to I/O
pins without affecting the routing of the original design. Starting
with a fully routed design, you can select and route signals for
debugging to either previously reserved or currently unused I/O
pins.
■SignalTap®II Embedded Logic Analyzer—This logic analyzer helps
you debug an FPGA design by probing the state of internal and I/O
signals without the use of external equipment or extra I/O pins,
while the design is running at full speed in an FPGA device. Defining
custom trigger-condition logic provides greater accuracy and
improves the ability to isolate problems. The SignalTap II Embedded
Logic Analyzer does not require external probes or changes to the
design files to capture the state of the internal nodes or I/O pins in
the design; all captured signal data is stored in device memory until
you are ready to read and analyze the data. You can use this feature
with incremental compilation to save compilation time.
■Logic Analyzer Interface—This interface enables you to connect and
transmit internal FPGA signals to an external logic analyzer for
analysis, allowing you to take advantage of advanced features in
your external logic analyzer or mixed signal oscilloscope. You can
use this feature to connect a large set of internal device signals to a
small number of output pins for debugging purposes.
■In-System Memory Content Editor—This feature provides read and
write access to in-system FPGA memories and constants through the
JTAG interface, making it easy to test changes to memory content
and constant values in the FPGA while the device is functioning in
the system.
■In-System Sources and Probes—This feature sets up customized
register chains to drive or sample the instrumented nodes in your
logic design, providing an easy way to input simple virtual stimuli
and capture the current value of instrumented nodes. You can force
trigger conditions set up using the SignalTap II Logic Analyzer,
create simple test vectors to exercise your design without the use of
external test equipment, and dynamically control run-time control
signals with the JTAG chain.

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Application Note 469: Stratix III Design Guidelines
■Virtual JTAG Megafunction—The sld_virtual_jtag megafunction
enables you to build your own system-level debugging
infrastructure, including both processor-based debugging solutions
and debugging tools in software for system-level debugging. This
megafunction can be instantiated directly in your HDL code to
provide one or more transparent communication channels to access
parts of your FPGA design using the JTAG interface of the device.
fFor more information about these debugging tools, refer to the
sld_virtual_jtag Megafunction User Guide and Section V. In-System Design
Debugging in volume 3 of the Quartus II Handbook. The section overview
provides more information about choosing a debugging solution.
Planning Guidelines for Debugging Tools
If you intend to use any of the on-chip debugging tools, plan for the tools
when developing your system board, Quartus II project, and design, as
described in this section.
The SignalTap II logic analyzer works best for synchronous interfaces.
For debugging asynchronous interfaces, consider using SignalProbe or an
external logic analyzer to view the signals most accurately.
The SignalTap II Embedded Logic Analyzer, Logic Analyzer Interface,
In-System Memory Content Editor, In-System Sources and Probes, and
Virtual JTAG Megafunction all require JTAG connections to perform
in-system debugging. Plan your system and board with JTAG ports that
are available for debugging.
The JTAG debugging features also require a small amount of additional
logic resources to implement the JTAG hub logic. If you set up the
appropriate feature early in your design cycle, you can include these
device resources in your early resource estimations to prevent over-filling
the device with logic.
The SignalTap II Embedded Logic Analyzer uses device memory to
capture data during system operation. Consider reserving device
memory for use during debugging to ensure that you have enough
memory resources to take advantage of this debugging technique.
To use incremental debugging with the SignalTap II Embedded Logic
Analyzer, ensure that the Full incremental compilation option is on. This
option is on by default for projects created in the Quartus II software
version 6.1 or later, but is not turned on automatically for existing
projects. If incremental compilation is not turned on, you must recompile
the entire design when you want to add debugging functions, or when

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Application Note 469: Stratix III Design Guidelines
you make certain changes to SignalTap II settings. Using incremental
compilation with the SignalTap II Embedded Logic Analyzer greatly
reduces the compilation time required for debugging.
SignalProbe and the Logic Analyzer Interface require I/O pins for
debugging. Reserve I/O pins for debugging so you do not have to change
the design or board to accommodate debugging signals later. The Logic
Analyzer Interface can multiplex signals with design I/O pins if required.
Ensure that your board supports some kind of debugging mode, where
debugging signals do not affect system operation.
If you use an external logic analyzer or mixed signal oscilloscope,
incorporate a pin header or mictor connector for the analyzer.
If you use the Virtual JTAG megafunction for custom debugging
applications, you must instantiate it and incorporate it as part of the
design process.
The In-System Sources and Probes feature also requires that you
instantiate a megafunction in your HDL code. In addition, you have the
option to instantiate the SignalTap II Embedded Logic Analyzer as a
megafunction so you can connect it to nodes in your design manually and
ensure that the tapped node names are not changed during synthesis. You
can add the debugging block as a separate design partition for
incremental compilation to minimize recompilation times.
To use the In-System Memory Content Editor for RAM or ROM blocks or
the LPM_CONSTANT megafunction, turn on the Allow In-System
Memory Content Editor to capture and update content independently
of the system clock option when you create the memory block in the
MegaWizard®Plug-In Manager.
Early Power Estimation
FPGA power consumption is an important design consideration. Power
consumption must be estimated accurately to develop an appropriate
power budget and to design the power supplies, voltage regulators,
decoupling, heat sink, and cooling system. Power estimation and analysis
have two significant planning requirements:
■Thermal planning—The cooling solution sufficiently dissipates the
heat generated by the device. In particular, the computed junction
temperature must fall within normal device specifications.
■Power supply planning—Power supplies must provide adequate
current to support device operation.

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Application Note 469: Stratix III Design Guidelines
Power consumption in FPGA devices is dependent on the logic design.
This dependence can make power estimation challenging during the
early board specification and layout stages. The Altera PowerPlay Early
Power Estimator (EPE) spreadsheet allows you to estimate power
utilization before the design is complete by processing information about
the device and the device resources that will be used in the design, as well
as the operating frequency, toggle rates, and environmental
considerations. You can use the spreadsheet to calculate the device
junction temperature by entering the ambient temperature, along with
information about the heat sinks, air flow, and board thermal model. The
EPE then calculates the power, current estimates, and thermal analysis for
the design.
If you do not have an existing design, estimate the number of device
resources used in your design and enter it manually. The spreadsheet
accuracy depends on your inputs and your estimation of the device
resources. If this information changes (during or after your design is
complete), your power estimation results are less accurate. If you have an
existing design or a partially-completed compiled design, use the
Generate PowerPlay Early Power Estimator File command in the
Quartus II software to provide input to the spreadsheet.
The PowerPlay Early Power Estimator spreadsheet includes the Import
Data macro, which parses the information in the power estimation file
and transfers it into the spreadsheet. If you do not want to use the macro,
you can transfer the data into the Early Power Estimator spreadsheet
manually. You should enter additional resources to be used in the final
design manually if the existing Quartus II project represents only a
portion of your full design. You can edit the spreadsheet and add
additional device resources or adjust the parameters after importing the
power estimation file information.
When the design is complete, the PowerPlay Power Analyzer tool in the
Quartus II software provides an accurate estimation of power that
ensures that thermal and supply budgets are not violated. Refer to
“Power Analysis,” on page 57.
The PowerPlay Early Power Estimator spreadsheets and user guides for
each supported device family are available in the Devices section under
Support on the Altera website:
www.altera.com/support/devices/estimator/pow-powerplay.html
fFor more information about using the estimator spreadsheet, refer to the
PowerPlay Early Power Estimator User Guide For Stratix III FPGAs. For
more information about power estimation and analysis, refer to the
PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook.

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Application Note 469: Stratix III Design Guidelines
Board Design
Considerations
When designing the interfaces to the Stratix III device, various factors can
affect the printed circuit board (PCB) design. This section includes
important guidelines for the following topics:
■“Device Power-Up”
■“Power Pin Connections,” on page 19
■“Configuration Pin Connections,” on page 21
■“Board-Related Quartus II Settings,” on page 24
■“Signal Integrity Considerations,” on page 25
■“Board-Level Simulation and Advanced I/O Timing Analysis,” on
page 27
“I/O and Clock Planning,” on page 27 details the I/O signal connections
for the FPGA, which also affect the board design.
fFor more board design guidelines, refer to Altera’s Board Design
Guidelines Solution Center at:
www.altera.com/support/devices/board/brd-index.html. This
Solution Center points to application notes and other documentation
that can help you implement successful high-speed PCBs that integrate
Altera devices with other elements.
Device Power-Up
Stratix III devices offer hot socketing, which is also known as hot plug-in
or hot swap, and power sequencing support without the use of any
external devices. You can insert or remove a Stratix III device or a board
in a system during system operation without causing undesirable effects
to the running system bus or the board inserted into the system. The hot
socketing feature helps you use Stratix III devices on printed circuit
boards (PCBs) that contain a mixture of voltages.
The system can drive signals into the device I/O before and during
power-up. You can power-up or power-down the VCCIO, VCC, VCCPGM,
and VCCPD supplies in any sequence. The individual power supply
ramp-up and ramp-down rates can range from 50 μs to 100 ms. The
power ramp must be monotonic. In a hot socketing situation, the
Stratix III device’s output buffers are turned off during system power-up
or power-down. Also, the Stratix III device does not drive out until the
device is configured and working within recommended operating
conditions.
Hot socketing circuitry is not available on configuration pins
CONF_DONE, nCEO, and nSTATUS because they are required during
configuration. Therefore, it is expected behavior for these pins to drive
out during power-up and power-down sequences.

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Application Note 469: Stratix III Design Guidelines
When power is applied to a Stratix III device, a power-on-reset event
occurs if the power supply reaches the recommended operating range
within a certain period of time (specified as a maximum power supply
ramp time; tRAMP). The maximum power supply ramp time for Stratix III
devices is 100 ms, while the minimum power supply ramp time is 50 μs.
The power-on reset (POR) circuit keeps the FPGA in reset until the VCC,
VCCL, VCCPD, VCCPGM, and VCCPT power voltage levels monitored by the
circuitry have stabilized on power-up. After the device enters user mode,
the POR circuitry continues to monitor for brown-out conditions during
user mode. In Stratix III devices, a pin-selectable option (PORSEL) is
provided that allows you to select between a POR typical delay time of
12 ms or 100 ms. In both cases, you can extend the POR time by using an
external component to assert the nSTATUS pin low. Extending POR time
is required if the board cannot meet the maximum power ramp time
specifications, to ensure the device configures properly and enters user
mode.
fFor more information, refer to the Hot Socketing & Power-On Reset in
Stratix III Devices chapter in the Stratix III Device Handbook.
Although power sequencing is not a requirement for correct operation,
you should consider the power-up timing of each rail to prevent
problems with long-term device reliability when designing a
multi-rail-powered system. You can reduce the device in-rush current
with proper sequencing and voltage regulator design.
fFor more information, refer to AN 448: Stratix III Power Management
Design Guide.
Power Pin Connections
The Stratix III selectable core voltage gives you the option of using a
power-saving 0.9-V core voltage VCCL or the standard 1.1-V core voltage
VCCL. In either case, a 1.1-V supply is required for the PLL and periphery
power supplies VCC and VCCD_PLL. The voltages VCC_CLKIN, VCCA_PLL,
VCCPT, and VCCBAT require a 2.5-V supply. The VCCPGM pin powers the
configuration pins, and can be 1.8, 2.5, 3.0, or 3.3-V.
The I/O voltage VCCIO connections depend on the design’s I/O standards
and support 1.2, 1.5, 1.8, 2.5, 3.0, and 3.3-V. Note that the device output
pins do not meet the I/O standard specifications if the VCCIO level is out
of the recommended operating range for the I/O standard. The VCCPD
pin must be connected to 3.3-V for a 3.3-V VCCIO, 3.0-V for a 3.0-V VCCIO,
and 2.5-V for lower I/O voltages. Voltage reference (VREF) pins serve as
voltage references for certain I/O standards. The VREF pin is used mainly
for a voltage bias and does not source or sink much current. The

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Application Note 469: Stratix III Design Guidelines
maximum value of this current is 10 μA, and it is independent of the
number of I/O pins using a particular VREF pin as their reference
voltage. The voltage can be created with a regulator or a resistor divider
network. For more information about VCCIO voltages and VREF pins for
different I/O banks, refer to “Selectable I/O Standards and Flexible I/O
Banks,” on page 31.
When designing a board, check that all the power pins are connected
correctly, explore any unique requirements for FPGA power pins or other
power pins on your board, and determine which devices on your board
can share a power rail.
fFor a list of the supply voltages required for the Stratix III device and
their recommended operation conditions, refer to the DC & Switching
Characteristics of Stratix III Devices chapter in the Stratix III Device
Handbook. For more details about Stratix III I/O pins, refer to the
Stratix III Device Pinout Files at www.altera.com and the Stratix III Pin
Connection Guidelines.
In Stratix III devices, Altera suggests that you use a linear regulator to
power the VCCA_PLL and VCCPT power pins, because they power analog
circuitry. You can power the digital voltage rails by linear or switching
regulators depending on efficiency or cost considerations.
fFor recommendations about power management system design,
including details about power sequencing and power distribution
architecture, refer to AN 448: Stratix III Power Management Design Guide.
Decoupling Capacitors
Board decoupling becomes more significant to improve overall power
supply signal integrity with increased power supply requirements.
Stratix III devices include embedded on-package and on-die decoupling
capacitors to provide high-frequency decoupling that external PCB
decoupling capacitors and voltage regulator modules cannot support.
These low-inductance capacitors suppress power noise for excellent
signal integrity performance, and reduce the number of external PCB
decoupling capacitors, saving board space, reducing cost, and greatly
simplifying PCB design.
Altera has created an easy-to-use power distribution network (PDN)
design tool that optimizes the board-level PDN graphically. The purpose
of the board-level PDN is to distribute power and return currents from
the voltage regulating module (VRM) to the FPGA power supplies, and
support optimal transceiver signal integrity and FPGA performance.