Altera Stratix III Instruction Manual

Altera Corporation 1
AN-469-1.1
Application Note 469
Stratix III Design Guidelines
Introduction Stratix®III devices are engineered for high-speed core performance and
high-speed I/O with the best signal integrity in the industry, combined
with low-static and dynamic-power consumption. The devices also offer
increased logic density, so you can integrate more of your product to
reduce cost and board space.
It is important to follow Altera recommendations throughout the design
process for high-density, high-performance Stratix III designs. Planning
the FPGA and system early in the design process is crucial to your
success. This document provides an easy-to-use set of guidelines and a
list of factors to consider in Stratix III designs, but does not include all the
details about the product. It includes pointers to other documentation
where you can find detailed specifications, device feature descriptions,
and additional guidelines. The material covers the Stratix III device
architecture as well as aspects of the Quartus®II software and third-party
tools that you might use in your design.
The guidelines presented in this document will help you improve
productivity and avoid common design pitfalls. The document discusses
various stages of the design flow in the order that each stage is typically
performed, as shown in Table 1. You can use the “Design Checklist,” on
page 65 to help verify that you have followed each of the guidelines.
Table 1. Summary of Design Flow Stages and Guideline Topics (Part 1 of 2)
Stages of Design Flow Guideline Topics
“Device Selection,” on page 2 Device information, determining device density, package
offerings, speed grade, core voltage, migration, and
HardCopy®ASICs
“Planning for Device Configuration,” on page 6 Configuration scheme overview, configuration features,
Quartus II settings, optional pins
“Early System Planning,” on page 12 Planning: design specifications, IP selection, on-chip
debugging, early power estimation
“Board Design Considerations,” on page 18 Power-up, power pins, configuration pins, signal integrity,
board-level verification
“I/O and Clock Planning,” on page 27 Pin assignments, early pin planning, I/O features and
connections, clock and PLL selection, SSN
“Design and Compilation,” on page 42 Synthesis tools, coding styles and recommendations, planning
for hierarchical or team-based design, SOPC Builder
May 2008, version 1.1

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Application Note 469: Stratix III Design Guidelines
fFor complete details about the Stratix III device architecture, refer to the
Stratix III Literature page. For the latest known issues related to
Stratix III FPGAs, refer to the Stratix III Device Family Errata Sheet and the
Knowledge Database.
Device Selection The first step in the Stratix III design process is to choose the device
family variant, device density, speed grade, package, and core voltage
that best suit your design needs. You should also consider whether you
want to target FPGA or ASIC migration devices. Before you begin
compiling a design in a third-party synthesis tool or the Quartus II
software, set the correct target device.
fFor information about the features available in each device density,
including logic, memory blocks, multipliers, and phase-locked loops
(PLLs), as well the various package offerings and I/O pin counts, refer to
the Stratix III Device Family Overview chapter in volume 1 of the Stratix III
Device Handbook.
Logic, Memory, and Multiplier Density
The Stratix III logic family (L) offers balanced logic, memory, and
multipliers to address a wide range of applications, while the enhanced
family (E) offers more memory and multipliers per logic and is ideal for
wireless, medical imaging, and military applications. Choose the device
family variant with the best resource balance for your design
requirements.
Stratix III devices offer a range of densities that provide different amounts
of device logic resources, including memory, multipliers, and adaptive
logic module (ALM) logic cells. Different device densities may also offer
different numbers of features such as PLLs. Determining the required
logic density can be a challenging part of the design planning process.
Devices with more logic resources can implement larger and potentially
more complex designs, but generally have a higher cost. Smaller devices
have lower static power utilization. Select a device that meets your design
needs with some safety margin, in case you want to add more logic later
in the design cycle, or to upgrade or expand your design. You might also
“Timing Closure and Verification,” on page 50 Device utilization, timing constraints and analysis, area and
timing optimization, verification
“Power Analysis and Optimization,” on page 57 Analysis tools, optimization techniques, thermal management
options
Table 1. Summary of Design Flow Stages and Guideline Topics (Part 2 of 2)
Stages of Design Flow Guideline Topics

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Application Note 469: Stratix III Design Guidelines
want additional space in the device to ease creating a design floorplan for
incremental or team-based design, as described in “Planning for
Hierarchical and Team-Based Design,” on page 47. Consider reserving
resources for debugging, as described in “Planning for On-Chip
Debugging,” on page 13. Stratix III devices support vertical migration
between certain device densities, which provides flexibility as described
in “Vertical Device Migration,” on page 3.
Many next-generation designs use a current design as a starting point. If
you have other designs that target an Altera device, you can use their
resource utilization as an estimate for your new design. Compile existing
designs in the Quartus II software with the Auto device selected by the
Fitter option in the Settings dialog box. Review the resource utilization to
find out which device density fits the design. Keep in mind that coding
style, device architecture, and the optimization options used in the
Quartus II software can significantly affect a design’s resource utilization
as well as timing performance. Refer to “Device Resource Utilization
Reports,” on page 51, for more information about determining resource
utilization.
To obtain resource utilization estimates for certain configurations of
Altera’s intellectual property (IP) designs, refer to the user guides for
Altera®megafunctions and IP MegaCores on the IP Megafunctions page
in the Literature section at www.altera.com. You can use these numbers
to help estimate the resource utilization of your design.
I/O Pin Count and Package Offering
Stratix III devices are available in space-saving FineLine®BGA packages
with various I/O pin counts. Certain package sizes support vertical
migration within different device densities, as described in “Vertical
Device Migration”. Determine the required number of I/O pins,
considering the design’s interface requirements with other system blocks.
You can compile any existing designs in the Quartus II software with the
Auto device selected by the Fitter option in the Settings dialog box to
determine how many input and output pins are used. Also consider
reserving pins for debugging, as described in “Planning for On-Chip
Debugging,” on page 13.
Vertical Device Migration
Stratix III devices support vertical migration within the same package,
which enables you to migrate to different density devices whose
dedicated pins, configuration pins, and power pins are the same for a
given package. This feature allows future upgrades or changes to your
design without any changes to the board layout, because you can replace
the Stratix III device on the board with a different density Stratix III

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Application Note 469: Stratix III Design Guidelines
device. You can migrate from the L logic family to the E enhanced family
without increasing the amount of logic available, which minimizes the
cost of vertical migration.
Determine whether you want the option of migrating your design to
another device density. Choose your device density and package to
accommodate any possible future device migration to allow flexibility
when the design nears completion. You should specify any potential
migration options in the Quartus II software at the beginning of your
design cycle. Selecting a migration device impacts the design’s pin
placement to ensure that your design is compatible with the selected
device(s). It is possible to add migration devices later in the design cycle,
but it requires extra effort to check pin assignments, and can require
design or board layout changes to fit into the new target device. It is easier
to consider these issues early in the design cycle than at the end, when the
design is near completion and ready for migration. To specify the target
migration devices, on the Assignments menu, click Device and in the
Settings dialog box, select Migration Devices.
As described in “Making FPGA Pin Assignments,” on page 28, the Pin
Migration view in the Quartus II Pin Planner highlights pins that change
function in the migration device when compared to the currently selected
device.
HardCopy III ASIC Migration
The HardCopy methodology allows you to seamlessly prototype your
system with Stratix III FPGAs and completely prepare your system for
production, prior to ASIC design handoff. Altera’s HardCopy Design
Center uses a proven turnkey process to implement the low-cost,
low-power, functionally-equivalent, pin-compatible HardCopy III ASIC.
The result is a drop-in replacement to the prototyping Stratix III FPGA on
your system board.
You can start your HardCopy III ASIC design by targeting your design to
an appropriate Stratix III FPGA and choosing the appropriate
HardCopy III ASIC companion in the latest version of the Quartus II
software.
You can migrate between the FPGA and ASIC revisions of your project
when the Quartus II software includes these devices.

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Application Note 469: Stratix III Design Guidelines
If you use a HardCopy device, review the HardCopy guidelines early in
the design cycle for any Quartus II software settings that should use or
other restrictions you should consider as you complete your design. For
example:
■HardCopy III devices use a 0.9-V core voltage (VCCL). So if you use a
1.1-V Stratix III device, your board design must accommodate a core
voltage change between devices.
■HardCopy devices do not support a 3.3-V VCCIO, so you should use
3.0-V or less in the Stratix III device as well.
■RAM cannot be initialized to a known value in the HardCopy ASIC
like in an FPGA. Therefore, if you plan to migrate to a HardCopy
device, your design must write RAM contents during device
operation instead of relying on memory initialization values.
■It is especially important to use complete timing constraints if you
want to migrate to a HardCopy device because of the rigorous
verification requirements for ASICs.
■Altera recommends adding the PLL reconfiguration megafunction to
your design so that you can change the PLL settings in-system on the
HardCopy III device.
fFor more information, refer to the Phase-Locked Loops
Reconfiguration Megafunction User Guide
(ALTPLL_RECONFIG).
In addition, review the HardCopy Readiness Report that is generated
during compilation when a HardCopy companion device is selected in
the Device Settings. This advises you about any incomplete I/O
assignments and provides recommendations for clock pin locations.
fFor more information and guidelines for HardCopy migrations, refer to
the HardCopy Series Handbook.
Speed Grade
The device speed grade affects the device timing performance and timing
closure, as well as power utilization. Stratix III devices are available in
three speed grades, –2, –3, and –4 (–2 is the fastest). Generally, the faster
devices have higher cost. As one way to help you determine which speed
grade your design requires, refer to the supported clock rates for specific
I/O interfaces.
fFor information about supported clock rates for memory interfaces using
I/O pins on different sides of the device in different device speed grades,
refer to the External Memory Interfaces in Stratix III Devices chapter in
volume 1 of the Stratix III Device Handbook.

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Application Note 469: Stratix III Design Guidelines
Some designers use the fastest speed grade during prototyping to reduce
compilation time (because less time is spent optimizing the design to
meet timing requirements), and then move to a slower speed grade for
production to reduce cost if the design meets its timing requirements.
The Quartus II software optimizes and analyzes your design using
different timing models for each speed grade. If you migrate to a device
with a different speed grade, you must perform timing analysis to ensure
that there are no timing violations resulting from changes in timing
performance.
Selectable Core Voltage
Selectable core voltage gives you the option of using a 0.9-V core voltage
which increases the static and dynamic power savings compared to the
standard 1.1-V core voltage. Designs requiring the highest performance
should use the 1.1-V core voltage, while designs requiring minimum
power consumption can use the 0.9-V core voltage. Choose the core
voltage along with the device and speed grade in the Quartus II software,
because the selectable core voltage affects the Stratix III fabric
performance. The Quartus II software uses timing and power models
specific to the selected core voltage to implement all timing-dependent
and power-dependent analysis, and optimization.
If you use the low-power voltage setting, ensure that the 0.9-V option is
available for your device density, package, and speed grade combination.
There is limited speed grade support with the 0.9-V option.
Planning for
Device
Configuration
Stratix III devices are based on SRAM cells, and you must download
configuration data to the Stratix III device each time the device powers up
because SRAM memory is volatile. Choosing your device configuration
method early allows system and board designers to determine what
companion devices, if any, are needed for your system. Your board layout
also depends on the configuration method you plan to use for the
programmable device, because different schemes require different
connections. For board design guidelines related to configuration pins,
refer to “Board Design Considerations,” on page 18.
In addition, Stratix III devices offer configuration data decompression to
save configuration memory space and time, design security using data
encryption to protect your designs, and real-time remote system
upgrades. Support for these configuration features varies depending on
your configuration scheme. Stratix III devices also include optional
configuration pins and a reconfiguration option that you should choose
up front and set up in the Quartus II software, so that you have all the
information required for your board and system design.

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Application Note 469: Stratix III Design Guidelines
This section includes the following topics:
■“Configuration Scheme Selection”
■“Configuration Features,” on page 9
■“Quartus II Configuration Settings,” on page 10
■“Configuration and Programming Files,” on page 11
fFor more information about configuration, refer to the Configuring
Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook.
For more information, refer to the Configuration Center. This web page
includes links to JTAG Configuration & ISP Troubleshooter and FPGA
Configuration Troubleshooter that you can use to help debug
configuration problems.
Configuration Scheme Selection
You can configure Stratix III devices using one of four configuration
schemes:
■Fast passive parallel (FPP)
■Fast active serial (AS)
■Passive serial (PS)
■Joint Test Action Group (JTAG)
Select the configuration scheme by driving the Stratix III device MSEL
pins either high or low.
fFor more information about the supported configuration schemes, refer
to the Stratix III Device Configuration Center. For complete information
about the Stratix III supported configuration schemes, how to execute
the required configuration schemes, and all of the necessary option pin
settings, including the MSEL pin settings, refer to the Configuring
Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook.
All configuration schemes use a configuration device, a download cable,
or an external controller (for example, a MAX®II device or
microprocessor).
Configuration Devices
You can use the Altera enhanced configuration devices (EPC) in the FPP
and PS configuration schemes. The Altera serial configuration devices
(EPCS) are used in the Fast AS configuration scheme. Check whether the
configuration device supports the configuration bitstream file size for
your Stratix III device. You can also use a MAX II device or a

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Application Note 469: Stratix III Design Guidelines
microprocessor with a flash memory configuration method, or use the
compression feature to reduce the configuration file size of large
Stratix III devices.
fFor information about enhanced configuration devices, refer to the
Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet and
the Altera Enhanced Configuration Devices chapters in volume 2 of the
Configuration Handbook. For information about serial configuration
devices, refer to the Serial Configuration Devices (EPCS1, EPCS4, EPCS16,
EPCS64, and EPCS128) Data Sheet in volume 2 of the Configuration
Handbook. This datasheet includes a table that lists serial configuration
device support for Stratix III devices. If the uncompressed file size is too
large for a specific device density, the table indicates that it includes the
compression feature to reduce the file size.
Serial configuration devices do not directly support the JTAG interface;
however, you can program the device with JTAG download cables using
the Serial FlashLoader (SFL) feature in the Quartus II software. This
feature uses the FPGA as a bridge between the JTAG interface and the
configuration device, allowing both devices to use the same JTAG
interface.
1This solution is slower than standard AS configuration schemes
because the SFL solution must configure the FPGA before
programming configuration devices.
fFor more details about the SFL, refer to AN 370: Using the Serial
FlashLoader with the Quartus II Software.
Download Cables
The Quartus II programmer supports configuring Stratix III devices
directly using PS or JTAG interfaces via Altera programming download
cables. You can download design changes directly to the device with
Altera download cables, making prototyping easy and enabling you to
make multiple design iterations in quick succession. You can use the same
download cable to program configuration devices on the board and use
JTAG debugging tools such as the SignalTap II Logic Analyzer.
fFor more information about how to use Altera’s current download
cables, refer to the following documents:
■ByteBlaster II Download Cable User Guide
■USB Blaster II USB Port Download Cable User Guide
■EthernetBlaster Communications Cable User Guide

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Application Note 469: Stratix III Design Guidelines
MAX II Parallel Flash Loader
If your system already contains common flash interface (CFI) flash
memory, you can utilize it for Stratix III device configuration storage as
well. The parallel flash loader (PFL) feature with MAX II devices allow
you to program CFI flash memory devices through the JTAG interface. It
also provides the logic to control configuration from the flash memory
device to the Stratix III device and supports compression to reduce the
size of your configuration data. Both PS and FPP configuration modes are
supported using this PFL feature. If you choose this configuration
method, you should check the list of supported flash devices early in your
system design cycle and plan accordingly.
fFor more information about PFL, refer to AN 386: Using the Parallel Flash
Loader with the Quartus II Software.
Configuration Features
This section describes Stratix III configuration features and how they
affect your design process: data compression, design security, and remote
system upgrades.
Data Compression
When you enable data compression, the Quartus II software generates
configuration files with compressed configuration data. This compressed
file reduces the storage requirements in the configuration device or flash
memory, and decreases the time needed to transmit the bitstream to the
Stratix III device. The time required by a Stratix III device to decompress
a configuration file is less than the time needed to transmit the
configuration data to the device. Stratix III devices support
decompression in the FPP (when using a MAX II device/microprocessor
+ flash), fast AS, and PS configuration schemes. The Stratix III
decompression feature is not available in the FPP (when using enhanced
configuration device) or JTAG configuration schemes.
fFor more information about data compression, refer to the Configuring
Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook.
Design Security Using Configuration Bitstream Encryption
The design security feature ensures that Stratix III designs are protected
from copying, reverse engineering, and tampering using configuration
bitstream encryption. The design security feature is available when
configuring Stratix III devices using the fast passive parallel (FPP)
configuration mode with an external host (such as a MAX II device or
microprocessor), or when using fast active serial (AS) or passive serial

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Application Note 469: Stratix III Design Guidelines
(PS) configuration schemes. The design security feature is also available
in remote update with fast AS configuration mode. The design security
feature is not available when you are configuring your Stratix III device
using FPP with an enhanced configuration device or JTAG configuration
schemes.
fFor more information about design security using configuration
bitstream encryption, refer to the Design Security in Stratix III Devices
chapter in volume 1 of the Stratix III Device Handbook.
Remote System Upgrades
Stratix III devices support remote update in the AS configuration scheme.
You can implement remote update in conjunction with real-time
decompression of configuration data if you need to save configuration
memory space in the serial configuration device with AS configuration.
To implement the remote system upgrade interface, you can use the
ALTREMOTE_UPDATE megafunction or instantiate a remote system
upgrade atom.
fFor more information about making remote system upgrades, refer to
the Remote System Upgrades with Stratix III Devices chapter in volume 1 of
the Stratix III Device Handbook. For more information about the
altremote_update megafunction, refer to the Remote Update Circuitry
Megafunction User Guide (ALTREMOTE_UPDATE).
Quartus II Configuration Settings
This section covers several configuration options that you can set in the
Quartus II software before you compile to generate configuration or
programming files. Your board and system design are affected by these
settings and pins.
Optional Configuration Pins
You can enable the following optional configuration pins on the General
tab of the Device and Pin Options dialog box:
■CLKUSR pin—The Enable user-supplied start-up clock (CLKUSR)
option enables you to select which clock source is used for
initialization, either the internal oscillator or an external clock
provided on the CLKUSR pin.