Epson S1C31W65 User manual

Rev. 1.1
CMOS 32-BIT SINGLE CHIP MICROCONTROLLER
S1C31W65
Technical Manual

©
SEIKO EPSON CORPORATION 2021 , All rights reserved.
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(Rev. e1.0, 2021.9)

PREFACE
S1C31W65 TECHNICAL MANUAL Seiko Epson Corporation i
(Rev. 1.1)
Preface
This is a technical manual for designers and programmers who develop a product using the S1C31W65. This
document describes the functions of the IC, embedded peripheral circuit operations, and their control methods.
Notational conventions and symbols in this manual
Register address
Peripheral circuit chapters do not provide control register addresses. Refer to “Peripheral Circuit Area” in
the “Memory and Bus” chapter or “List of Peripheral Circuit Control Registers” in the Appendix.
Register and control bit names
In this manual, the register and control bit names are described as shown below to distinguish from signal
and pin names.
XXX register: Represents a register including its all bits.
XXX.YYY bit: Represents the one control bit YYY in the XXX register.
XXX.ZZZ[1:0] bits: Represents the two control bits ZZZ1 and ZZZ0 in the XXX register.
Register table contents and symbols
Initial: Value set at initialization
Reset: Initialization condition. The initialization condition depends on the reset group (H0, H1, or S0).
For more information on the reset groups, refer to “Initialization Conditions (Reset Groups)” in the
“Power Supply, Reset, and Clocks” chapter.
R/W: R = Read only bit
W = Write only bit
WP = Write only bit with a write protection using the SYSPROT.PROT[15:0] bits
R/W = Read/write bit
R/WP = Read/write bit with a write protection using the SYSPROT.PROT[15:0] bits
Control bit read/write values
This manual describes control bit values in a hexadecimal notation except for one-bit values (and except
when decimal or binary notation is required in terms of explanation). The values are described as shown
below according to the control bit width.
1 bit: 0 or 1
2 to 4 bits: 0x0 to 0xf
5 to 8 bits: 0x00 to 0xff
9 to 12 bits: 0x000 to 0xfff
13 to 16 bits: 0x0000 to 0xffff
Decimal: 0 to 9999...
Binary: 0b0000... to 0b1111...
Channel number
Multiple channels may be implemented in some peripheral circuits (e.g., 16-bit timer, etc.). The peripheral
circuit chapters use ‘n’ as the value that represents the channel number in the register and pin names regard-
less of the number of channel actually implemented. Normally, the descriptions are applied to all channels.
If there is a channel that has different functions from others, the channel number is specified clearly.
Example) T16_nCTL register of the 16-bit timer
If one channel is implemented (Ch.0 only): T16_nCTL = T16_0CTL only
If two channels are implemented (Ch.0 and Ch.1): T16_nCTL = T16_0CTL and T16_1CTL
For the number of channels implemented in the peripheral circuits of this IC, refer to “Features” in the
“Overview” chapter.
Low power mode
This manual describes the low power modes as HALT mode and SLEEP mode. These terms refer to sleep
mode and deep sleep mode in the Cortex®-M0+ processor, respectively.

CONTENTS
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– Contents –
Preface......................................................................................................................................i
Notational conventions and symbols in this manual ................................................................i
1 Overview........................................................................................................................1-1
1.1 Features .......................................................................................................................... 1-1
1.2 Block Diagram................................................................................................................. 1-3
1.3 Pins ................................................................................................................................. 1-4
1.3.1 Pin Configuration Diagram................................................................................ 1-4
1.3.2 Pin Descriptions................................................................................................ 1-5
2 Power Supply, Reset, and Clocks ...............................................................................2-1
2.1 Power Generator (PWGA) ............................................................................................... 2-1
2.1.1 Overview ........................................................................................................... 2-1
2.1.2 Pins................................................................................................................... 2-1
2.1.3 VD1 Regulator Operation Mode......................................................................... 2-2
2.1.4 VD1 Regulator Voltage Mode............................................................................. 2-2
2.2 System Reset Controller (SRC)....................................................................................... 2-3
2.2.1 Overview ........................................................................................................... 2-3
2.2.2 Input Pin............................................................................................................ 2-4
2.2.3 Reset Sources .................................................................................................. 2-4
2.2.4 Reset Request Flag .......................................................................................... 2-5
2.2.5 #RESET Pin Input Control................................................................................. 2-5
2.2.6 Initialization Conditions (Reset Groups)............................................................ 2-6
2.3 Clock Generator (CLG).................................................................................................... 2-7
2.3.1 Overview ........................................................................................................... 2-7
2.3.2 Input/Output Pins ............................................................................................. 2-8
2.3.3 Clock Sources .................................................................................................. 2-8
2.3.4 Operations ....................................................................................................... 2-11
2.4 Operating Mode ............................................................................................................. 2-16
2.4.1 Initial Boot Sequence....................................................................................... 2-16
2.4.2 Transition between Operating Modes.............................................................. 2-16
2.5 Interrupts........................................................................................................................ 2-18
2.6 Control Registers ........................................................................................................... 2-18
PWGA Control Register............................................................................................................ 2-18
SRC Reset Request Flag Register ........................................................................................... 2-19
SRC #RESET Port Control Register......................................................................................... 2-19
CLG System Clock Control Register........................................................................................ 2-20
CLG Oscillation Control Register ............................................................................................. 2-21
CLG IOSC Control Register ..................................................................................................... 2-22
CLG OSC1 Control Register .................................................................................................... 2-23
CLG OSC3 Control Register .................................................................................................... 2-24
CLG Interrupt Flag Register ..................................................................................................... 2-25
CLG Interrupt Enable Register ................................................................................................. 2-26
CLG FOUT Control Register..................................................................................................... 2-26
CLG Oscillation Frequency Trimming Register 1 ..................................................................... 2-27
CLG Oscillation Frequency Trimming Register 2 ..................................................................... 2-28
3 CPU and Debugger ......................................................................................................3-1
3.1 Overview ......................................................................................................................... 3-1
3.2 CPU................................................................................................................................. 3-1
3.3 Debugger ........................................................................................................................ 3-1
3.3.1 List of Debugger Input/Output Pins.................................................................. 3-1
3.3.2 External Connection ......................................................................................... 3-1

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3.4 Reference Documents .................................................................................................... 3-2
4 Memory and Bus ..........................................................................................................4-1
4.1 Overview ......................................................................................................................... 4-1
4.2 Bus Access Cycle ........................................................................................................... 4-2
4.3 Flash Memory ................................................................................................................. 4-2
4.3.1 Flash Memory Pin ............................................................................................. 4-2
4.3.2 Flash Bus Access Cycle Setting....................................................................... 4-2
4.3.3 Flash Programming........................................................................................... 4-2
4.4 RAM ................................................................................................................................ 4-3
4.5 Display Data RAM ........................................................................................................... 4-3
4.6 Peripheral Circuit Control Registers................................................................................ 4-3
4.6.1 System-Protect Function.................................................................................. 4-9
4.7 Control Registers ............................................................................................................ 4-9
System Protect Register ........................................................................................................... 4-9
FLASHC Flash Read Cycle Register ........................................................................................ 4-10
5 Interrupt.........................................................................................................................5-1
5.1 Overview ......................................................................................................................... 5-1
5.2 Vector Table .................................................................................................................... 5-1
5.2.1 Vector Table Offset Address (VTOR)................................................................. 5-3
5.2.2 Priority of Interrupts .......................................................................................... 5-3
5.3 Peripheral Circuit Interrupt Control ................................................................................. 5-3
5.4 NMI.................................................................................................................................. 5-3
6 DMA Controller (DMAC)...............................................................................................6-1
6.1 Overview ......................................................................................................................... 6-1
6.2 Operations ...................................................................................................................... 6-2
6.2.1 Initialization ....................................................................................................... 6-2
6.3 Priority............................................................................................................................. 6-2
6.4 Data Structure................................................................................................................. 6-2
6.4.1 Transfer Source End Pointer............................................................................. 6-3
6.4.2 Transfer Destination End Pointer ...................................................................... 6-3
6.4.3 Control Data...................................................................................................... 6-4
6.5 DMA Transfer Mode ........................................................................................................ 6-5
6.5.1 Basic Transfer ................................................................................................... 6-5
6.5.2 Auto-Request Transfer...................................................................................... 6-5
6.5.3 Ping-Pong Transfer ........................................................................................... 6-6
6.5.4 Memory Scatter-Gather Transfer ...................................................................... 6-7
6.5.5 Peripheral Scatter-Gather Transfer ................................................................... 6-8
6.6 DMA Transfer Cycle ........................................................................................................ 6-9
6.7 Interrupts......................................................................................................................... 6-9
6.8 Control Registers ........................................................................................................... 6-10
DMAC Status Register ............................................................................................................. 6-10
DMAC Configuration Register.................................................................................................. 6-10
DMAC Control Data Base Pointer Register.............................................................................. 6-11
DMAC Alternate Control Data Base Pointer Register .............................................................. 6-11
DMAC Software Request Register........................................................................................... 6-11
DMAC Request Mask Set Register .......................................................................................... 6-11
DMAC Request Mask Clear Register ....................................................................................... 6-12
DMAC Enable Set Register ...................................................................................................... 6-12
DMAC Enable Clear Register ................................................................................................... 6-12
DMAC Primary-Alternate Set Register ..................................................................................... 6-12
DMAC Primary-Alternate Clear Register .................................................................................. 6-13

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DMAC Priority Set Register...................................................................................................... 6-13
DMAC Priority Clear Register................................................................................................... 6-13
DMAC Error Interrupt Flag Register ......................................................................................... 6-13
DMAC Transfer Completion Interrupt Flag Register................................................................. 6-14
DMAC Transfer Completion Interrupt Enable Set Register ...................................................... 6-14
DMAC Transfer Completion Interrupt Enable Clear Register ................................................... 6-14
DMAC Error Interrupt Enable Set Register............................................................................... 6-14
DMAC Error Interrupt Enable Clear Register............................................................................ 6-15
7 I/O Ports (PPORT).........................................................................................................7-1
7.1 Overview ......................................................................................................................... 7-1
7.2 I/O Cell Structure and Functions..................................................................................... 7-2
7.2.1 Schmitt Input .................................................................................................... 7-2
7.2.2 Over Voltage Tolerant Fail-Safe Type I/O Cell................................................... 7-2
7.2.3 Pull-Up/Pull-Down ............................................................................................ 7-2
7.2.4 CMOS Output and High Impedance State ....................................................... 7-3
7.3 Clock Settings................................................................................................................. 7-3
7.3.1 PPORT Operating Clock................................................................................... 7-3
7.3.2 Clock Supply in SLEEP Mode .......................................................................... 7-3
7.3.3 Clock Supply During Debugging ...................................................................... 7-3
7.4 Operations ...................................................................................................................... 7-3
7.4.1 Initialization ....................................................................................................... 7-3
7.4.2 Port Input/Output Control................................................................................. 7-5
7.5 Interrupts......................................................................................................................... 7-6
7.6 Control Registers ............................................................................................................ 7-6
PxPort Data Register................................................................................................................ 7-6
PxPort Enable Register ............................................................................................................ 7-7
PxPort Pull-up/down Control Register..................................................................................... 7-7
PxPort Interrupt Flag Register.................................................................................................. 7-8
PxPort Interrupt Control Register............................................................................................. 7-8
PxPort Chattering Filter Enable Register.................................................................................. 7-8
PxPort Mode Select Register ................................................................................................... 7-8
PxPort Function Select Register .............................................................................................. 7-9
P Port Clock Control Register ................................................................................................... 7-9
P Port Interrupt Flag Group Register........................................................................................ 7-10
7.7 Control Register and Port Function Configuration of this IC ......................................... 7-11
7.7.1 P0 Port Group.................................................................................................. 7-11
7.7.2 P1 Port Group.................................................................................................. 7-12
7.7.3 P2 Port Group.................................................................................................. 7-13
7.7.4 P3 Port Group.................................................................................................. 7-14
7.7.5 P4 Port Group.................................................................................................. 7-15
7.7.6 P5 Port Group.................................................................................................. 7-16
7.7.7 P6 Port Group.................................................................................................. 7-17
7.7.8 Pd Port Group.................................................................................................. 7-18
7.7.9 Common Registers between Port Groups....................................................... 7-19
8 Universal Port Multiplexer (UPMUX)...........................................................................8-1
8.1 Overview ......................................................................................................................... 8-1
8.2 Peripheral Circuit I/O Function Assignment.................................................................... 8-1
8.3 Control Registers ............................................................................................................ 8-2
Pxy–xz Universal Port Multiplexer Setting Register................................................................... 8-2
9 Watchdog Timer (WDT2)..............................................................................................9-1
9.1 Overview ......................................................................................................................... 9-1
9.2 Clock Settings................................................................................................................. 9-1

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9.2.1 WDT2 Operating Clock..................................................................................... 9-1
9.2.2 Clock Supply in DEBUG Mode......................................................................... 9-1
9.3 Operations ...................................................................................................................... 9-2
9.3.1 WDT2 Control ................................................................................................... 9-2
9.3.2 Operations in HALT and SLEEP Modes............................................................ 9-3
9.4 Control Registers ............................................................................................................ 9-3
WDT2 Clock Control Register ................................................................................................... 9-3
WDT2 Control Register ............................................................................................................. 9-4
WDT2 Counter Compare Match Register ................................................................................. 9-5
10 Real-Time Clock (RTCA) ...........................................................................................10-1
10.1 Overview ...................................................................................................................... 10-1
10.2 Output Pin and External Connection ........................................................................... 10-1
10.2.1 Output Pin...................................................................................................... 10-1
10.3 Clock Settings.............................................................................................................. 10-2
10.3.1 RTCA Operating Clock .................................................................................. 10-2
10.3.2 Theoretical Regulation Function.................................................................... 10-2
10.4 Operations ................................................................................................................... 10-3
10.4.1 RTCA Control ................................................................................................ 10-3
10.4.2 Real-Time Clock Counter Operations............................................................ 10-4
10.4.3 Stopwatch Control......................................................................................... 10-4
10.4.4 Stopwatch Count-up Pattern ........................................................................ 10-4
10.5 Interrupts...................................................................................................................... 10-5
10.6 Control Registers ......................................................................................................... 10-6
RTCA Control Register (Low Byte) ........................................................................................... 10-6
RTCA Control Register (High Byte) .......................................................................................... 10-7
RTCA Second Alarm Register .................................................................................................. 10-7
RTCA Hour/Minute Alarm Register .......................................................................................... 10-8
RTCA Stopwatch Control Register........................................................................................... 10-8
RTCA Second/1Hz Register..................................................................................................... 10-9
RTCA Hour/Minute Register.................................................................................................... 10-10
RTCA Month/Day Register...................................................................................................... 10-11
RTCA Year/Week Register....................................................................................................... 10-11
RTCA Interrupt Flag Register .................................................................................................. 10-12
RTCA Interrupt Enable Register .............................................................................................. 10-13
11 Supply Voltage Detector (SVD4)...............................................................................11-1
11.1 Overview ...................................................................................................................... 11-1
11.2 Input Pins and External Connection ............................................................................ 11-2
11.2.1 Input Pins....................................................................................................... 11-2
11.2.2 External Connection ...................................................................................... 11-2
11.3 Clock Settings.............................................................................................................. 11-2
11.3.1 SVD4 Operating Clock................................................................................... 11-2
11.3.2 Clock Supply in SLEEP Mode ....................................................................... 11-2
11.3.3 Clock Supply in DEBUG Mode...................................................................... 11-3
11.4 Operations ................................................................................................................... 11-3
11.4.1 SVD4 Control ................................................................................................. 11-3
11.4.2 SVD4 Operations ........................................................................................... 11-4
11.5 SVD4 Interrupt and Reset ............................................................................................ 11-4
11.5.1 SVD4 Interrupt ............................................................................................... 11-4
11.5.2 SVD Reset...................................................................................................... 11-5
11.6 Control Registers ......................................................................................................... 11-5
SVD4 Ch.nClock Control Register .......................................................................................... 11-5
SVD4 Ch.nControl Register..................................................................................................... 11-6

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SVD4 Ch.nStatus and Interrupt Flag Register......................................................................... 11-7
SVD4 Ch.nInterrupt Enable Register....................................................................................... 11-8
12 16-bit Timers (T16).....................................................................................................12-1
12.1 Overview ...................................................................................................................... 12-1
12.2 Input Pin....................................................................................................................... 12-1
12.3 Clock Settings.............................................................................................................. 12-2
12.3.1 T16 Operating Clock...................................................................................... 12-2
12.3.2 Clock Supply in SLEEP Mode ....................................................................... 12-2
12.3.3 Clock Supply During Debugging ................................................................... 12-2
12.3.4 Event Counter Clock...................................................................................... 12-2
12.4 Operations ................................................................................................................... 12-2
12.4.1 Initialization .................................................................................................... 12-2
12.4.2 Counter Underflow ........................................................................................ 12-3
12.4.3 Operations in Repeat Mode........................................................................... 12-3
12.4.4 Operations in One-shot Mode ....................................................................... 12-3
12.4.5 Counter Value Read....................................................................................... 12-4
12.5 Interrupt........................................................................................................................ 12-4
12.6 Control Registers ......................................................................................................... 12-4
T16 Ch.nClock Control Register ............................................................................................. 12-4
T16 Ch.nMode Register .......................................................................................................... 12-5
T16 Ch.nControl Register........................................................................................................ 12-5
T16 Ch.nReload Data Register................................................................................................ 12-6
T16 Ch.nCounter Data Register .............................................................................................. 12-6
T16 Ch.nInterrupt Flag Register .............................................................................................. 12-6
T16 Ch.nInterrupt Enable Register.......................................................................................... 12-7
13 UART (UART3)............................................................................................................13-1
13.1 Overview ...................................................................................................................... 13-1
13.2 Input/Output Pins and External Connections .............................................................. 13-2
13.2.1 List of Input/Output Pins................................................................................ 13-2
13.2.2 External Connections .................................................................................... 13-2
13.2.3 Input Pin Pull-Up Function............................................................................. 13-2
13.2.4 Output Pin Open-Drain Output Function ...................................................... 13-2
13.2.5 Input/Output Signal Inverting Function.......................................................... 13-2
13.3 Clock Settings.............................................................................................................. 13-2
13.3.1 UART3 Operating Clock ................................................................................ 13-2
13.3.2 Clock Supply in SLEEP Mode ....................................................................... 13-3
13.3.3 Clock Supply During Debugging ................................................................... 13-3
13.3.4 Baud Rate Generator..................................................................................... 13-3
13.4 Data Format ................................................................................................................. 13-3
13.5 Operations ................................................................................................................... 13-4
13.5.1 Initialization .................................................................................................... 13-4
13.5.2 Data Transmission ......................................................................................... 13-5
13.5.3 Data Reception .............................................................................................. 13-6
13.5.4 IrDA Interface................................................................................................. 13-7
13.5.5 Carrier Modulation ......................................................................................... 13-8
13.6 Receive Errors.............................................................................................................. 13-9
13.6.1 Framing Error ................................................................................................. 13-9
13.6.2 Parity Error..................................................................................................... 13-9
13.6.3 Overrun Error ................................................................................................. 13-9
13.7 Interrupts..................................................................................................................... 13-10
13.8 DMA Transfer Requests .............................................................................................. 13-10
13.9 Control Registers ........................................................................................................ 13-11

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UART3 Ch.nClock Control Register ....................................................................................... 13-11
UART3 Ch.nMode Register.................................................................................................... 13-11
UART3 Ch.nBaud–Rate Register ........................................................................................... 13-13
UART3 Ch.nControl Register ................................................................................................. 13-13
UART3 Ch.nTransmit Data Register ....................................................................................... 13-14
UART3 Ch.nReceive Data Register........................................................................................ 13-14
UART3 Ch.nStatus and Interrupt Flag Register ..................................................................... 13-14
UART3 Ch.nInterrupt Enable Register.................................................................................... 13-15
UART3 Ch.nTransmit Buffer Empty DMA Request Enable Register ...................................... 13-16
UART3 Ch.nReceive Buffer One Byte Full DMA Request Enable Register............................ 13-16
UART3 Ch.nCarrier Waveform Register ................................................................................. 13-16
14 Synchronous Serial Interface (SPIA)........................................................................14-1
14.1 Overview ...................................................................................................................... 14-1
14.2 Input/Output Pins and External Connections .............................................................. 14-2
14.2.1 List of Input/Output Pins................................................................................ 14-2
14.2.2 External Connections .................................................................................... 14-2
14.2.3 Pin Functions in Master Mode and Slave Mode............................................ 14-3
14.2.4 Input Pin Pull-Up/Pull-Down Function .......................................................... 14-3
14.3 Clock Settings.............................................................................................................. 14-3
14.3.1 SPIA Operating Clock.................................................................................... 14-3
14.3.2 Clock Supply During Debugging ................................................................... 14-4
14.3.3 SPI Clock (SPICLKn) Phase and Polarity ...................................................... 14-4
14.4 Data Format ................................................................................................................. 14-5
14.5 Operations ................................................................................................................... 14-5
14.5.1 Initialization .................................................................................................... 14-5
14.5.2 Data Transmission in Master Mode ............................................................... 14-6
14.5.3 Data Reception in Master Mode.................................................................... 14-8
14.5.4 Terminating Data Transfer in Master Mode................................................... 14-10
14.5.5 Data Transfer in Slave Mode......................................................................... 14-10
14.5.6 Terminating Data Transfer in Slave Mode ..................................................... 14-11
14.6 Interrupts..................................................................................................................... 14-12
14.7 DMA Transfer Requests .............................................................................................. 14-13
14.8 Control Registers ........................................................................................................ 14-13
SPIA Ch.nMode Register ....................................................................................................... 14-13
SPIA Ch.nControl Register..................................................................................................... 14-14
SPIA Ch.nTransmit Data Register .......................................................................................... 14-15
SPIA Ch.nReceive Data Register ........................................................................................... 14-15
SPIA Ch.nInterrupt Flag Register ........................................................................................... 14-15
SPIA Ch.nInterrupt Enable Register ....................................................................................... 14-16
SPIA Ch.nTransmit Buffer Empty DMA Request Enable Register.......................................... 14-16
SPIA Ch.nReceive Buffer Full DMA Request Enable Register ............................................... 14-16
15 I2C (I2C).......................................................................................................................15-1
15.1 Overview ...................................................................................................................... 15-1
15.2 Input/Output Pins and External Connections .............................................................. 15-2
15.2.1 List of Input/Output Pins................................................................................ 15-2
15.2.2 External Connections .................................................................................... 15-2
15.3 Clock Settings.............................................................................................................. 15-3
15.3.1 I2C Operating Clock ...................................................................................... 15-3
15.3.2 Clock Supply During Debugging ................................................................... 15-3
15.3.3 Baud Rate Generator..................................................................................... 15-3
15.4 Operations ................................................................................................................... 15-4
15.4.1 Initialization .................................................................................................... 15-4
15.4.2 Data Transmission in Master Mode ............................................................... 15-5

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15.4.3 Data Reception in Master Mode.................................................................... 15-7
15.4.4 10-bit Addressing in Master Mode ............................................................... 15-10
15.4.5 Data Transmission in Slave Mode................................................................. 15-11
15.4.6 Data Reception in Slave Mode ..................................................................... 15-13
15.4.7 Slave Operations in 10-bit Address Mode.................................................... 15-15
15.4.8 Automatic Bus Clearing Operation ............................................................... 15-15
15.4.9 Error Detection.............................................................................................. 15-16
15.5 Interrupts..................................................................................................................... 15-17
15.6 DMA Transfer Requests .............................................................................................. 15-18
15.7 Control Registers ........................................................................................................ 15-18
I2C Ch.nClock Control Register............................................................................................. 15-18
I2C Ch.nMode Register.......................................................................................................... 15-19
I2C Ch.nBaud-Rate Register.................................................................................................. 15-19
I2C Ch.nOwn Address Register ............................................................................................. 15-20
I2C Ch.nControl Register ....................................................................................................... 15-20
I2C Ch.nTransmit Data Register............................................................................................. 15-21
I2C Ch.nReceive Data Register.............................................................................................. 15-21
I2C Ch.nStatus and Interrupt Flag Register ........................................................................... 15-22
I2C Ch.nInterrupt Enable Register ......................................................................................... 15-23
I2C Ch.nTransmit Buffer Empty DMA Request Enable Register............................................ 15-24
I2C Ch.nReceive Buffer Full DMA Request Enable Register.................................................. 15-24
16 16-bit PWM Timers (T16B) ........................................................................................16-1
16.1 Overview ...................................................................................................................... 16-1
16.2 Input/Output Pins......................................................................................................... 16-2
16.3 Clock Settings.............................................................................................................. 16-3
16.3.1 T16B Operating Clock ................................................................................... 16-3
16.3.2 Clock Supply in SLEEP Mode ....................................................................... 16-3
16.3.3 Clock Supply During Debugging ................................................................... 16-3
16.3.4 Event Counter Clock...................................................................................... 16-3
16.4 Operations ................................................................................................................... 16-4
16.4.1 Initialization .................................................................................................... 16-4
16.4.2 Counter Block Operations ............................................................................. 16-5
16.4.3 Comparator/Capture Block Operations......................................................... 16-8
16.4.4 TOUT Output Control ................................................................................... 16-17
16.5 Interrupt....................................................................................................................... 16-23
16.6 DMA Transfer Requests .............................................................................................. 16-23
16.7 Control Registers ........................................................................................................ 16-23
T16B Ch.nClock Control Register.......................................................................................... 16-23
T16B Ch.nCounter Control Register ...................................................................................... 16-24
T16B Ch.nMax Counter Data Register................................................................................... 16-25
T16B Ch.nTimer Counter Data Register................................................................................. 16-25
T16B Ch.nCounter Status Register........................................................................................ 16-26
T16B Ch.nInterrupt Flag Register........................................................................................... 16-27
T16B Ch.nInterrupt Enable Register ...................................................................................... 16-28
T16B Ch.nComparator/Capture mControl Register.............................................................. 16-29
T16B Ch.nCompare/Capture mData Register....................................................................... 16-31
T16B Ch.nCounter Max/Zero DMA Request Enable Register ............................................... 16-32
T16B Ch.nCompare/Capture mDMA Request Enable Register............................................ 16-32
17 Sound Generator (SNDA) ..........................................................................................17-1
17.1 Overview ...................................................................................................................... 17-1
17.2 Output Pins and External Connections........................................................................ 17-2
17.2.1 List of Output Pins ......................................................................................... 17-2
17.2.2 Output Pin Drive Mode .................................................................................. 17-2

CONTENTS
S1C31W65 TECHNICAL MANUAL Seiko Epson Corporation ix
(Rev. 1.1)
17.2.3 External Connections .................................................................................... 17-2
17.3 Clock Settings.............................................................................................................. 17-3
17.3.1 SNDA Operating Clock.................................................................................. 17-3
17.3.2 Clock Supply in SLEEP Mode ....................................................................... 17-3
17.3.3 Clock Supply in DEBUG Mode...................................................................... 17-3
17.4 Operations ................................................................................................................... 17-3
17.4.1 Initialization .................................................................................................... 17-3
17.4.2 Buzzer Output in Normal Buzzer Mode......................................................... 17-3
17.4.3 Buzzer Output in One-shot Buzzer Mode...................................................... 17-6
17.4.4 Output in Melody Mode................................................................................. 17-7
17.5 Interrupts...................................................................................................................... 17-9
17.6 DMA Transfer Requests .............................................................................................. 17-10
17.7 Control Registers ........................................................................................................ 17-10
SNDA Clock Control Register ................................................................................................. 17-10
SNDA Select Register ............................................................................................................. 17-11
SNDA Control Register............................................................................................................ 17-12
SNDA Data Register................................................................................................................ 17-12
SNDA Interrupt Flag Register.................................................................................................. 17-13
SNDA Interrupt Enable Register.............................................................................................. 17-13
SNDA Sound Buffer Empty DMA Request Enable Register ................................................... 17-14
18 IR Remote Controller (REMC3) ................................................................................18-1
18.1 Overview ...................................................................................................................... 18-1
18.2 Output Pins and External Connections........................................................................ 18-1
18.2.1 List of Output Pins ......................................................................................... 18-1
18.2.2 External Connections .................................................................................... 18-2
18.3 Clock Settings.............................................................................................................. 18-2
18.3.1 REMC3 Operating Clock ............................................................................... 18-2
18.3.2 Clock Supply in SLEEP Mode ....................................................................... 18-2
18.3.3 Clock Supply During Debugging ................................................................... 18-2
18.4 Operations ................................................................................................................... 18-2
18.4.1 Initialization .................................................................................................... 18-2
18.4.2 Data Transmission Procedures...................................................................... 18-3
18.4.3 REMO Output Waveform ............................................................................... 18-3
18.4.4 Continuous Data Transmission and Compare Buffers................................... 18-5
18.5 Interrupts...................................................................................................................... 18-6
18.6 Application Example: Driving EL Lamp........................................................................ 18-7
18.7 Control Registers ......................................................................................................... 18-7
REMC3 Clock Control Register................................................................................................ 18-7
REMC3 Data Bit Counter Control Register .............................................................................. 18-8
REMC3 Data Bit Counter Register........................................................................................... 18-9
REMC3 Data Bit Active Pulse Length Register....................................................................... 18-10
REMC3 Data Bit Length Register............................................................................................ 18-10
REMC3 Status and Interrupt Flag Register............................................................................. 18-10
REMC3 Interrupt Enable Register ........................................................................................... 18-11
REMC3 Carrier Waveform Register......................................................................................... 18-11
REMC3 Carrier Modulation Control Register .......................................................................... 18-11
19 12-bit A/D Converter (ADC12A)................................................................................19-1
19.1 Overview ...................................................................................................................... 19-1
19.2 Input Pins and External Connections........................................................................... 19-2
19.2.1 List of Input Pins............................................................................................ 19-2
19.2.2 External Connections .................................................................................... 19-2
19.3 Clock Settings.............................................................................................................. 19-2

CONTENTS
xSeiko Epson Corporation S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)
19.3.1 ADC12A Operating Clock.............................................................................. 19-2
19.3.2 Sampling Time............................................................................................... 19-2
19.4 Operations ................................................................................................................... 19-3
19.4.1 Initialization .................................................................................................... 19-3
19.4.2 Conversion Start Trigger Source.................................................................... 19-3
19.4.3 Conversion Mode and Analog Input Pin Settings.......................................... 19-4
19.4.4 A/D Conversion Operations and Control Procedures.................................... 19-4
19.5 Interrupts...................................................................................................................... 19-6
19.6 DMA Transfer Requests ............................................................................................... 19-6
19.7 Control Registers ......................................................................................................... 19-7
ADC12A Ch.nControl Register ................................................................................................ 19-7
ADC12A Ch.nTrigger/Analog Input Select Register ................................................................ 19-8
ADC12A Ch.nConfiguration Register ...................................................................................... 19-9
ADC12A Ch.nInterrupt Flag Register ..................................................................................... 19-10
ADC12A Ch.nInterrupt Enable Register ................................................................................. 19-10
ADC12A Ch.nDMA Request Enable Register m.................................................................... 19-11
ADC12A Ch.nResult Register................................................................................................. 19-11
20 Temperature Sensor/Reference Voltage Generator (TSRVR)................................20-1
20.1 Overview ...................................................................................................................... 20-1
20.2 Output Pin and External Connections ......................................................................... 20-1
20.2.1 Output Pin...................................................................................................... 20-1
20.2.2 External Connections .................................................................................... 20-2
20.3 Operations ................................................................................................................... 20-2
20.3.1 Reference Voltage Setting ............................................................................. 20-2
20.3.2 Temperature Sensor Setting .......................................................................... 20-2
20.4 Control Registers ......................................................................................................... 20-3
TSRVR Ch.nTemperature Sensor Control Register ................................................................. 20-3
TSRVR Ch.nReference Voltage Generator Control Register................................................... 20-3
21 LCD Driver (LCD8D) ..................................................................................................21-1
21.1 Overview ...................................................................................................................... 21-1
21.2 Output Pins and External Connections........................................................................ 21-2
21.2.1 List of Output Pins ......................................................................................... 21-2
21.2.2 External Connections .................................................................................... 21-2
21.3 Clock Settings.............................................................................................................. 21-3
21.3.1 LCD8D Operating Clock ................................................................................ 21-3
21.3.2 Clock Supply in SLEEP Mode ....................................................................... 21-3
21.3.3 Clock Supply in DEBUG Mode...................................................................... 21-3
21.3.4 Frame Frequency........................................................................................... 21-3
21.4 LCD Power Supply....................................................................................................... 21-4
21.4.1 Internal Generation Mode .............................................................................. 21-4
21.4.2 External Voltage Application Mode 1............................................................. 21-4
21.4.3 External Voltage Application Mode 2 ............................................................ 21-5
21.4.4 External Voltage Application Mode 3 ............................................................ 21-5
21.4.5 LCD Power Supply Circuit Settings............................................................... 21-6
21.5 Operations ................................................................................................................... 21-6
21.5.1 Initialization .................................................................................................... 21-6
21.5.2 Display On/Off ............................................................................................... 21-7
21.5.3 Inverted Display ............................................................................................. 21-7
21.5.4 Drive Duty Switching ..................................................................................... 21-7
21.5.5 Drive Waveforms............................................................................................ 21-8
21.5.6 Partial Common Output Drive....................................................................... 21-17
21.5.7 n-Segment-Line Inverse AC Drive ................................................................ 21-17

CONTENTS
S1C31W65 TECHNICAL MANUAL Seiko Epson Corporation xi
(Rev. 1.1)
21.6 Display Data RAM ....................................................................................................... 21-17
21.6.1 Display Area Selection.................................................................................. 21-17
21.6.2 Segment Pin Assignment ............................................................................. 21-18
21.6.3 Common Pin Assignment ............................................................................. 21-18
21.7 Interrupt....................................................................................................................... 21-20
21.8 Control Registers ........................................................................................................ 21-20
LCD8D Clock Control Register ............................................................................................... 21-20
LCD8D Control Register.......................................................................................................... 21-21
LCD8D Timing Control Register 1........................................................................................... 21-21
LCD8D Timing Control Register 2........................................................................................... 21-22
LCD8D Power Control Register .............................................................................................. 21-22
LCD8D Display Control Register............................................................................................. 21-24
LCD8D COM Pin Control Register 0 ....................................................................................... 21-24
LCD8D Interrupt Flag Register ................................................................................................ 21-25
LCD8D Interrupt Enable Register............................................................................................ 21-25
22 R/F Converter (RFC)..................................................................................................22-1
22.1 Overview ...................................................................................................................... 22-1
22.2 Input/Output Pins and External Connections .............................................................. 22-2
22.2.1 List of Input/Output Pins................................................................................ 22-2
22.2.2 External Connections .................................................................................... 22-2
22.3 Clock Settings.............................................................................................................. 22-3
22.3.1 RFC Operating Clock..................................................................................... 22-3
22.3.2 Clock Supply in SLEEP Mode ....................................................................... 22-3
22.3.3 Clock Supply in DEBUG Mode...................................................................... 22-3
22.4 Operations ................................................................................................................... 22-3
22.4.1 Initialization .................................................................................................... 22-3
22.4.2 Operating Modes........................................................................................... 22-4
22.4.3 RFC Counters ................................................................................................ 22-4
22.4.4 Converting Operations and Control Procedure ............................................. 22-5
22.4.5 CR Oscillation Frequency Monitoring Function............................................. 22-7
22.5 Interrupts...................................................................................................................... 22-7
22.6 Control Registers ......................................................................................................... 22-8
RFC Ch.nClock Control Register ............................................................................................ 22-8
RFC Ch.nControl Register....................................................................................................... 22-8
RFC Ch.nOscillation Trigger Register...................................................................................... 22-9
RFC Ch.nMeasurement Counter Low and High Registers .................................................... 22-10
RFC Ch.nTime Base Counter Low and High Registers ......................................................... 22-10
RFC Ch.nInterrupt Flag Register............................................................................................ 22-11
RFC Ch.nInterrupt Enable Register........................................................................................ 22-11
23 Electrical Characteristics .........................................................................................23-1
23.1 Absolute Maximum Ratings ......................................................................................... 23-1
23.2 Recommended Operating Conditions ......................................................................... 23-1
23.3 Current Consumption................................................................................................... 23-2
23.4 System Reset Controller (SRC) Characteristics........................................................... 23-4
23.5 Clock Generator (CLG) Characteristics........................................................................ 23-5
23.6 Flash Memory Characteristics ..................................................................................... 23-7
23.7 Input/Output Port (PPORT) Characteristics ................................................................. 23-8
23.8 Supply Voltage Detector (SVD4) Characteristics ......................................................... 23-9
23.9 UART (UART3) Characteristics ................................................................................... 23-11
23.10 Synchronous Serial Interface (SPIA) Characteristics ................................................ 23-12
23.11 I2C (I2C) Characteristics............................................................................................ 23-14
23.12 LCD Driver (LCD8D) Characteristics ......................................................................... 23-14

CONTENTS
xii Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)
23.13 R/F Converter (RFC) Characteristics......................................................................... 23-19
23.14 12-bit A/D Converter (ADC12A) Characteristics ....................................................... 23-21
23.15 Temperature Sensor/Reference Voltage Generator (TSRVR) Characteristics........... 23-22
24 Basic External Connection Diagram .......................................................................24-1
25 Package......................................................................................................................25-1
Appendix A List of Peripheral Circuit Control Registers ......................................... AP-A-1
0x4000 0000 System Register (SYS)............................................ AP-A-1
0x4000 0020 Power Generator (PWGA) ....................................... AP-A-1
0x4000 0040–0x4000 0050 Clock Generator (CLG) ........................................... AP-A-1
0x4000 0060–0x4000 0062 System Reset Controller (SRC)............................... AP-A-2
0x4000 00a0–0x4000 00a4 Watchdog Timer (WDT2)......................................... AP-A-3
0x4000 00c0–0x4000 00d2 Real-time Clock (RTCA) .......................................... AP-A-3
0x4000 0100–0x4000 0106 Supply Voltage Detector (SVD4) Ch.0..................... AP-A-5
0x4000 0140–0x4000 014c 16-bit Timer (T16) Ch.0 ........................................... AP-A-5
0x4000 01b0 Flash Controller (FLASHC)...................................... AP-A-5
0x4000 0200–0x4000 02e2 I/O Ports (PPORT)................................................... AP-A-6
0x4000 0300–0x4000 031e Universal Port Multiplexer (UPMUX) ...................... AP-A-10
0x4000 0380–0x4000 0394 UART (UART3) Ch.0............................................... AP-A-12
0x4000 03a0–0x4000 03ac 16-bit Timer (T16) Ch.1 .......................................... AP-A-13
0x4000 03b0–0x4000 03be Synchronous Serial Interface (SPIA) Ch.0 ............. AP-A-13
0x4000 03c0–0x4000 03d6 I2C (I2C) Ch.0 ......................................................... AP-A-14
0x4000 0400–0x4000 042c 16-bit PWM Timer (T16B) Ch.0.............................. AP-A-15
0x4000 0440–0x4000 046c 16-bit PWM Timer (T16B) Ch.1.............................. AP-A-18
0x4000 0480–0x4000 048c 16-bit Timer (T16) Ch.3 .......................................... AP-A-20
0x4000 04a0–0x4000 04ac 16-bit Timer (T16) Ch.4 .......................................... AP-A-20
0x4000 04c0–0x4000 04cc 16-bit Timer (T16) Ch.5 .......................................... AP-A-21
0x4000 0600–0x4000 0614 UART (UART3) Ch.1............................................... AP-A-21
0x4000 0660–0x4000 066c 16-bit Timer (T16) Ch.6 .......................................... AP-A-23
0x4000 0670–0x4000 067e Synchronous Serial Interface (SPIA) Ch.1 ............. AP-A-23
0x4000 0680–0x4000 068c 16-bit Timer (T16) Ch.2 .......................................... AP-A-24
0x4000 06c0–0x4000 06d6 I2C (I2C) Ch.1 ......................................................... AP-A-25
0x4000 0700–0x4000 070c Sound Generator (SNDA)....................................... AP-A-26
0x4000 0720–0x4000 0732 IR Remote Controller (REMC3) .............................. AP-A-26
0x4000 0740–0x4000 076c 16-bit PWM Timer (T16B) Ch.2.............................. AP-A-27
0x4000 0780–0x4000 078c 16-bit Timer (T16) Ch.7 .......................................... AP-A-30
0x4000 07a0–0x4000 07bc 12-bit A/D Converter (ADC12A) Ch.0 .................... AP-A-30
0x4000 07c0–0x4000 07c2 Temperature Sensor/
Reference Voltage Generator (TSRVR) Ch.0.......... AP-A-31
0x4000 0800–0x4000 0812 LCD Driver (LCD8D)............................................... AP-A-32
0x4000 0840–0x4000 0850 R/F Converter (RFC) Ch.0...................................... AP-A-33
0x4000 1000–0x4000 2014 DMA Controller (DMAC)......................................... AP-A-33
Appendix B Power Saving .......................................................................................... AP-B-1
B.1 Operating Status Configuration Examples for Power Saving...................................... AP-B-1
B.2 Other Power Saving Methods ..................................................................................... AP-B-2
Appendix C Mounting Precautions............................................................................ AP-C-1
Appendix D Measures Against Noise ........................................................................ AP-D-1
Revision History

1 OVERVIEW
S1C31W65 TECHNICAL MANUAL Seiko Epson Corporation 1-1
(Rev. 1.1)
1 Overview
The S1C31W65 is a 32-bit MCU with an Arm®Cortex®-M0+ processor included that features low-power operation. It
incorporates a lot of serial interface circuits and is suitable for various kinds of battery-driven controller applications.
1.1 Features
Table 1.1.1 Features
Model S1C31W65
CPU
CPU Arm®32-bit RISC processor Cortex®-M0+
Other Serial-wire debug ports (SW-DP) and a micro trace buffer (MTB) included
Embedded Flash memory
Capacity 128K bytes (for both instructions and data)
Erase/program count 1,000 times (min.) *When being programmed by the dedicated flash loader
Other On-board programming function
Flash programming voltage can be generated internally.
Embedded RAMs
General-purpose RAM 16K bytes (shared with MTB)
Display RAM 112 bytes
DMA Controller (DMAC)
Number of channels 4 channels
Data transfer path Memory to memory, memory to peripheral, and peripheral to memory
Transfer mode Basic, ping-pong, scatter-gather
DMA trigger source UART3, SPIA, I2C, T16B, SNDA, ADC12A, and software
Clock generator (CLG)
System clock source 4 sources (IOSC/OSC1/OSC3/EXOSC)
System clock frequency (operating frequency) VD1 voltage mode = mode0: 33 MHz (max.)
VD1 voltage mode = mode1: 2.16 MHz (max.)
IOSC oscillator circuit (boot clock source) VD1 voltage mode = mode0: 32/24/16/12/8/2/1 MHz (typ.) selectable embedded oscillator
VD1 voltage mode = mode1: 2/1 MHz (typ.) selectable embedded oscillator
2 µs (max.) starting time (time from cancelation of SLEEP state to vector table read
by the CPU when the system clock = 32 MHz)
OSC1 oscillator circuit 32.768 kHz (typ.) crystal oscillator
32 kHz (typ.) embedded oscillator
Oscillation stop detection circuit included
OSC3 oscillator circuit 33 MHz (max.) crystal/ceramic oscillator
32/24/16/12/8 MHz (typ.) selectable embedded oscillator
EXOSC clock input 33 MHz (max.) square or sine wave input
Other Configurable system clock division ratio
Configurable system clock used at wake up from SLEEP state
Operating clock frequency for the CPU and all peripheral circuits is selectable.
I/O port (PPORT)
Number of general-
purpose ports
I/O ports 63 bits (max.)
Output port 1 bit
Other Pins are shared with the peripheral I/O.
Input interrupt Number of interrupt ports 56 bits (max.)
Interrupt type Rising edge interrupts and falling edge interrupts can be enabled individually.
Number of ports that support universal port
multiplexer (UPMUX)
32 bits
A peripheral circuit I/O function selected via software can be assigned to each port.
Timers
Watchdog timer (WDT2) Generates NMI or watchdog timer reset.
Programmable NMI/reset generation cycle
Real-time clock (RTCA) 128–1 Hz counter, second/minute/hour/day/day of the week/month/year counters
Theoretical regulation function for 1-second correction
Alarm and stopwatch functions
16-bit timer (T16) 8 channels
Generates the SPIA master clock and the ADC12A trigger signal.
16-bit PWM timer (T16B) 3 channels
Event counter/capture function
PWM waveform generation function
Number of PWM output or capture input ports: 4 ports/channel

1 OVERVIEW
1-2 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)
Supply voltage detector (SVD4)
Number of channels 1 channel
Detection voltage VDD or an external voltage (2 external detection ports are available.)
Detection level VDD: 32 levels (1.7 to 5.0 V)/external voltage: 32 levels (1.7 to 5.0 V)
Other Intermittent operation mode
Generates an interrupt or reset according to the detection level evaluation.
Serial interfaces
UART (UART3) 2 channels
Baud-rate generator included, IrDA1.0 supported
Open drain output, signal polarity, and baud rate division ratio are configurable.
Infrared communication carrier modulation output function
Synchronous serial interface (SPIA) 2 channels
2 to 16-bit variable data length
The 16-bit timer (T16) can be used for the baud-rate generator in master mode.
I2C (I2C) *12 channels
Baud-rate generator included
Sound generator (SNDA)
Buzzer output function 512 Hz to 16 kHz output frequencies
One-shot output function
Melody generation function Pitch: 128 Hz to 16 kHz ≈C3 to C6
Duration: 7 notes/rests (Half note/rest to thirty-second note/rest)
Tempo: 16 tempos (30 to 480)
Tie/slur may be specified.
IR remote controller (REMC3)
Number of transmitter channels 1 channel
Other EL lamp drive waveform can be generated (by the hardware) for an application example.
Output inversion function
12-bit A/D converter (ADC12A)
Conversion method Successive approximation type
Resolution 12 bits
Number of conversion channels 1 channel
Number of analog signal inputs 8 ports/channel (The temperature sensor output is connected to a port.)
Temperature sensor/reference voltage generator (TSRVR)
Temperature sensor circuit Sensor output can be measured using ADC12A.
Reference voltage generator Reference voltage for ADC12A is selectable from 2.0 V, 2.5 V, VDD, and external input.
LCD driver (LCD8D)
LCD output 52 SEG ×5–8 COM(max.), 56 SEG ×1–4 COM(max.)
LCD contrast 32 levels
LCD drive waveform 2 types (Waveform A, Waveform B) selectable
Other 1/3 or 1/2 bias power supply with voltage booster included, external voltage can be
applied.
R/F converter (RFC)
Conversion method CR oscillation type with 24-bit counters
Number of conversion channels 1 channel (Up to two sensors can be connected.)
Supported sensors DC-bias resistive sensors
Reset
#RESET pin Reset when the reset pin is set to low. Can be enabled/disabled using a register.
Power-on reset Reset at power on.
Brownout reset Reset when the power supply voltage drops.
Key entry reset Reset when the P00 to P01/P02/P03 keys
are pressed simultaneously.
Can be enabled/disabled using a register.
Watchdog timer reset Reset when the watchdog timer overflows.
Supply voltage detector reset Reset when the supply voltage detector
detects the set voltage level.
Interrupt
Non-maskable interrupt 6 systems (Reset, NMI, HardFault, SVCall, PendSV, SysTic)
Programmable interrupt External interrupt: 1 system
Internal interrupt: 26 systems
Power supply voltage
VDD operating voltage 1.8 to 5.5 V
VDD operating voltage for Flash programming 2.2 to 5.5 V
VDD operating voltage when LCD driver is used 1.8 to 5.5 V
Operating temperature
Operating temperature range -40 to 105°C
Flash programming temperature range -40 to 85°C
Current consumption (Typ. value)
SLEEP mode *20.3 µA IOSC = OFF, OSC1 = OFF, OSC3 = OFF
0.8 µA IOSC = OFF, OSC1 = 32.768 kHz (crystal oscillator), OSC3 = OFF, RTCA = ON
HALT mode *31.5 µA OSC1 = 32.768 kHz (crystal oscillator)
4.0 µA OSC1 = 32.768 kHz (crystal oscillator), LCD = ON (no panel load)

1 OVERVIEW
S1C31W65 TECHNICAL MANUAL Seiko Epson Corporation 1-3
(Rev. 1.1)
Current consumption (Typ. value)
RUN mode 195 µA/MHz VD1 voltage mode = mode0, CPU = IOSC (16 MHz)
130 µA/MHz VD1 voltage mode = mode1, CPU = IOSC (2 MHz)
Shipping form
Package *4TQFP14-100PIN (P-TQFP100-1212-0.40, 12 ×12 mm, t = 1.2 mm, 0.4 mm pitch)
*1 The input filter in I2C (SDA and SCL inputs) does not comply with the standard for removing noise spikes less than 50 ns.
*2 SLEEP mode refers to deep sleep mode in the Cortex®-M0+ processor. The RAM retains data even in SLEEP mode.
*3 HALT mode refers to sleep mode in the Cortex®-M0+ processor.
*4 Shown in parentheses is a JEITA package name.
1.2 Block Diagram
CPU core, interrpt controller, and debuger
(Cortex®-M0+) RAM
16K bytes
Display RAM
112 bytes
System clock
Interrupt signal
DMA request signal
SWCLK
SWD
MTB
16-bit peripheral bus
32-bit AHB bus
#ADTRG0
ADIN00–06
(ADIN07)
VREFA0
12-bit A/D
converter
(ADC12A)
1 Ch.
Temperature
sensor/
Reference
voltage generator
(TSRVR)
IOSC
oscillator
EXOSC
input circuit
Clock generator
(CLG)
Power generator
(PWGA)
VDD
VSS
VD1
RTC1S
SDA0–1
SCL0–1
EXSVD00–01
P00–07
P10–17
P20–27
P30–37
P40–47
P50–57
P60–67
PD0–D3
PD4
PD5–D7
FOUT
OSC1
OSC2
OSC3
OSC4
EXOSC
VPP
OSC3
oscillator
OSC1
oscillator
I/O port
(PPORT)
Watchdog timer
(WDT2)
Real-time clock
(RTCA)
I2C
(I2C)
2 Ch.
Supply voltage
detector
(SVD4)
1 Ch.
16-bit timer
(T16)
8 Ch.
TOUT00–03
TOUT10–13
TOUT20–23
CAP00–03
CAP10–13
CAP20–23
EXCL00–01
EXCL10–11
EXCL20–21
16-bit PWM timer
(T16B)
3 Ch.
SDI0–1
SDO0–1
SPICLK0–1
#SPISS0–1
Synchronous
serial interface
(SPIA)
2 Ch.
USIN0–1
USOUT0–1
UART
(UART3)
2 Ch.
Flash memory
128K bytes
DMA controller
REMO
CLPLS
IR remote
controller
(REMC3)
1 Ch.
COM0–3
COM4–7/
SEG0–3
SEG4–55
LFRO
VC1–3
CP1–2
LCD driver
(LCD8D)
R/F converter
(RFC)
1 Ch.
RFIN0
REF0
SENA0
SENB0
RFCLKO0
Power-on reset
(POR)
System reset controller
(SRC)
#RESET
Brownout reset
(BOR)
BZOUT
#BZOUT
Sound generator
(SNDA)
Figure 1.2.1 S1C31W65 Block Diagram

1 OVERVIEW
1-4 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)
1.3 Pins
1.3.1 Pin Configuration Diagram
TQFP14-100PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VSS
P60 P61 P62 P63
SEG12 SEG11 SEG10
SEG9 SEG8 SEG7 SEG6 SEG5 SEG4
PD5
P64 P65 P66 P67
COM3 COM2 COM1 COM0
PD6 PD7
VSS
P60/SEG16 P61/SEG15 P62/SEG14 P63/SEG13
SEG12 SEG11 SEG10
SEG9 SEG8 SEG7 SEG6 SEG5 SEG4
VPP/PD5
P64/COM7/SEG3 P65/COM6/SEG2 P66/COM5/SEG1 P67/COM4/SEG0
COM3 COM2 COM1 COM0
PD6/CP1
PD7/CP2
P36 P35 P34 P33 P32 P31 P30 SEG48 SEG49 SEG50 SEG51 SEG52 P27 P26 P25 P24 P23 P22 PD3 PD2 P21 P20 PD1 PD0 VDD
P36/UPMUX/EXSVD01/SEG41 P35/UPMUX/EXSVD00/SEG42
P34/LFRO/UPMUX/SEG43 P33/FOUT/UPMUX/SEG44 P32/RTC1S/UPMUX/SEG45
P31/#ADTRG0/UPMUX/SEG46
P30/EXOSC/UPMUX/SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 P27/EXCL21/UPMUX/SEG53 P26/EXCL11/UPMUX/SEG54 P25/EXCL01/UPMUX/SEG55 P24/EXCL20/UPMUX P23/CLPLS/UPMUX P22/REMO/UPMUX PD3/OSC4 PD2/OSC3 P21/#BZOUT/UPMUX P20/BZOUT/UPMUX SWD/PD1 SWCLK/PD0 VDD
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VSS
VD1
#RESET
OSC1
OSC2
PD4
P17
P16
P15
P14
P13
P12
P11
P10
P07
P06
P05
P04
P03
P02
P01
P00
VC3
VC2
VC1
VSS
VD1
#RESET
OSC1
OSC2
PD4
P17/UPMUX/VREFA0
P16/EXCL10/UPMUX/ADIN00
P15/EXCL00/UPMUX/ADIN01
P14/UPMUX/ADIN02
P13/UPMUX/ADIN03
P12/UPMUX/ADIN04
P11/UPMUX/ADIN05
P10/UPMUX/ADIN06
P07/RFIN0/UPMUX
P06/REF0/UPMUX
P05/SENA0/UPMUX
P04/SENB0/UPMUX
P03/#SPISS1/UPMUX
P02/SPICLK1/UPMUX
P01/SDO1/UPMUX
P00/SDI1/UPMUX
VC3
VC2
VC1
Pin name
P37
P40
P41
P42
P43
P44
P45
P46
P47
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
P50
P51
P52
P53
P54
P55
P56
P57
VDD
Port function
or signal
assignment
P37/RFCLKO0/UPMUX/SEG40
P40/SEG39
P41/SEG38
P42/SEG37
P43/SEG36
P44/SEG35
P45/SEG34
P46/SEG33
P47/SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
P50/SEG24
P51/SEG23
P52/SEG22
P53/SEG21
P54/SEG20
P55/SEG19
P56/SEG18
P57/SEG17
VDD
Figure 1.3.1.1 S1C31W65 Pin Configuration Diagram (TQFP14-100PIN)

1 OVERVIEW
S1C31W65 TECHNICAL MANUAL Seiko Epson Corporation 1-5
(Rev. 1.1)
1.3.2 Pin Descriptions
Symbol meanings
Assigned signal: The signal listed at the top of each pin is assigned in the initial state. The pin function must be
switched via software to assign another signal (see the “I/O Ports” chapter).
I/O: I = Input
O = Output
I/O = Input/output
P = Power supply
A = Analog signal
Hi-Z = High impedance state
Initial state: I (Pull-up) = Input with pulled up
I (Pull-down) = Input with pulled down
Hi-Z = High impedance state
O (H) = High level output
O (L) = Low level output
Tolerant fail-safe structure:
✓= Over voltage tolerant fail-safe type I/O cell included (see the “I/O Ports” chapter)
Table 1.3.2.1 Pin Description
Pin name Assigned
signal I/O Initial state
Tolerant
fail-safe
structure
Function
VDD VDD P – –Power supply (+)
VSS VSS P – – GND
VD1 VD1 A – – VD1 regulator output
VC1–3 VC1–3 P – – LCD panel driver power supply
OSC1 OSC1 A - – OSC1 oscillator circuit input
OSC2 OSC2 A - – OSC1 oscillator circuit output
#RESET #RESET I I (Pull-up) – Reset input
P00 P00 I/O Hi-Z ✓I/O port
SDI1 I Synchronous serial interface Ch.1 data input
UPMUX I/O User-selected I/O (universal port multiplexer)
P01 P01 I/O Hi-Z ✓I/O port
SDO1 O Synchronous serial interface Ch.1 data output
UPMUX I/O User-selected I/O (universal port multiplexer)
P02 P02 I/O Hi-Z ✓I/O port
SPICLK1 I/O Synchronous serial interface Ch.1 clock input/output
UPMUX I/O User-selected I/O (universal port multiplexer)
P03 P03 I/O Hi-Z ✓I/O port
#SPISS1 I Synchronous serial interface Ch.1 slave-select input
UPMUX I/O User-selected I/O (universal port multiplexer)
P04 P04 I/O Hi-Z ✓I/O port
SENB0 A R/F converter Ch.0 sensor B oscillator pin
UPMUX I/O User-selected I/O (universal port multiplexer)
P05 P05 I/O Hi-Z ✓I/O port
SENA0 A R/F converter Ch.0 sensor A oscillator pin
UPMUX I/O User-selected I/O (universal port multiplexer)
P06 P06 I/O Hi-Z ✓I/O port
REF0 A R/F converter Ch.0 reference oscillator pin
UPMUX I/O User-selected I/O (universal port multiplexer)
P07 P07 I/O Hi-Z – I/O port
RFIN0 A R/F converter Ch.0 oscillation input
UPMUX I/O User-selected I/O (universal port multiplexer)
P10 P10 I/O Hi-Z – I/O port
UPMUX I/O User-selected I/O (universal port multiplexer)
ADIN06 A 12-bit A/D converter Ch.0 analog signal input 6
P11 P11 I/O Hi-Z – I/O port
UPMUX I/O User-selected I/O (universal port multiplexer)
ADIN05 A 12-bit A/D converter Ch.0 analog signal input 5
P12 P12 I/O Hi-Z – I/O port
UPMUX I/O User-selected I/O (universal port multiplexer)
ADIN04 A 12-bit A/D converter Ch.0 analog signal input 4

1 OVERVIEW
1-6 Seiko Epson Corporation S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)
Pin name Assigned
signal I/O Initial state
Tolerant
fail-safe
structure
Function
P13 P13 I/O Hi-Z – I/O port
UPMUX I/O User-selected I/O (universal port multiplexer)
ADIN03 A 12-bit A/D converter Ch.0 analog signal input 3
P14 P14 I/O Hi-Z – I/O port
UPMUX I/O User-selected I/O (universal port multiplexer)
ADIN02 A 12-bit A/D converter Ch.0 analog signal input 2
P15 P15 I/O Hi-Z – I/O port
EXCL00 I 16-bit PWM timer Ch.0 event counter input 0
UPMUX I/O User-selected I/O (universal port multiplexer)
ADIN01 A 12-bit A/D converter Ch.0 analog signal input 1
P16 P16 I/O Hi-Z – I/O port
EXCL10 I 16-bit PWM timer Ch.1 event counter input 0
UPMUX I/O User-selected I/O (universal port multiplexer)
ADIN00 A 12-bit A/D converter Ch.0 analog signal input 0
P17 P17 I/O Hi-Z – I/O port
UPMUX I/O User-selected I/O (universal port multiplexer)
VREFA0 A 12-bit A/D converter Ch.0 reference voltage input
P20 P20 I/O Hi-Z ✓I/O port
BZOUT O Sound generator output
UPMUX I/O User-selected I/O (universal port multiplexer)
P21 P21 I/O Hi-Z ✓I/O port
#BZOUT O Sound generator inverted output
UPMUX I/O User-selected I/O (universal port multiplexer)
P22 P22 I/O Hi-Z ✓I/O port
REMO O IR remote controller transmit data output
UPMUX I/O User-selected I/O (universal port multiplexer)
P23 P23 I/O Hi-Z ✓I/O port
CLPLS O IR remote controller clear pulse output
UPMUX I/O User-selected I/O (universal port multiplexer)
P24 P24 I/O Hi-Z ✓I/O port
EXCL20 I 16-bit PWM timer Ch.2 event counter input 0
UPMUX I/O User-selected I/O (universal port multiplexer)
P25 P25 I/O Hi-Z ✓I/O port
EXCL01 I 16-bit PWM timer Ch.0 event counter input 1
UPMUX I/O User-selected I/O (universal port multiplexer)
SEG55 A LCD segment output
P26 P26 I/O Hi-Z ✓I/O port
EXCL11 I 16-bit PWM timer Ch.1 event counter input 1
UPMUX I/O User-selected I/O (universal port multiplexer)
SEG54 A LCD segment output
P27 P27 I/O Hi-Z ✓I/O port
EXCL21 I 16-bit PWM timer Ch.2 event counter input 1
UPMUX I/O User-selected I/O (universal port multiplexer)
SEG53 A LCD segment output
P30 P30 I/O Hi-Z ✓I/O port
EXOSC I Clock generator external clock input
UPMUX I/O User-selected I/O (universal port multiplexer)
SEG47 A LCD segment output
P31 P31 I/O Hi-Z ✓I/O port
#ADTRG0 I 12-bit A/D converter Ch.0 trigger input
UPMUX I/O User-selected I/O (universal port multiplexer)
SEG46 A LCD segment output
P32 P32 I/O Hi-Z ✓I/O port
RTC1S O Real-time clock 1-second cycle pulse output
UPMUX I/O User-selected I/O (universal port multiplexer)
SEG45 A LCD segment output
P33 P33 I/O Hi-Z ✓I/O port
FOUT O Clock external output
UPMUX I/O User-selected I/O (universal port multiplexer)
SEG44 A 12-bit A/D converter Ch.0 analog signal input 3