Altera CPLD User manual

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Altera CPLD learning board manual
QQ:906606596

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Contents
Development board intended use........................................................................................................3
Development board hardware description..........................................................................................3
Hardware Circuit Description.............................................................................................................4
Power..............................................................................................................................................4
Clock...............................................................................................................................................4
I/O ports ..........................................................................................................................................4
LED.................................................................................................................................................5
Push Buttons ...................................................................................................................................5
Buzzer .............................................................................................................................................6
General headers...............................................................................................................................6

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Development board intended use
The development board uses the Altera's MAX II Series EP M240 T100C5N chip design. This
chip is also compatible with EPM 570T100C5N.
The objective of this development board is the help customers reduce costs and accelerate learning
by providing quick access to programmable logic device design and development. Thus, this
development board provides a platform to help users quickly learn the hardware programmable
logic devices.
The development board provides a JTAG interface for programming the chip. Programming by
ByteBlasterII download cable is recommended is it can download to FPGA / CPLD chips by
Altera Corporation.
The development board has 65 I / O ports are cited by pin outs marked on the board. The user
can configure the pin assignments.
The development board facilitates user’s development of their own products. It also maximizes
savings for the user when studying the development costs.
Development board hardware description
MAX II U1 EP M240T100C5
8 7 segment LED displays
8 LED lights
BELL
Five separate keys
JTAG download mode
External 5V DC power supply
50MHz Active Crystals

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Hardware Circuit Description
Power
Use an external 5V DC power supply. Please note that the polarity of an external 5V DC power
supply is positive (+ve) with respect to center.
Clock
CPLD (pin) P12 is provided with the 50M Hz clock frequency of the active crystal U3.
I/O ports
I / O ports are assigned as follows:
LED1: P86
LED2: P87
LED3: P96
LED4: P89
LED5: P97
LED6: P91
LED7: P92
LED8: P95
LEDA : P85 LEDB : P84 LEDC : P83 LEDD : P82
LEDE : P81 LEDF : P78 LEDG : P77 LEDH : P76
When LED1 to LED8 is low, LEDAto LEDH(LEDDP)
is low to light LED segment

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LED
I / O ports are assigned as follows:
D30: P51
D31: P52
D32: P53
D33: P54
D34: P55
D35: P56
D36: P57
D37: P58
When the I / O port is low LED will be lit
Push Buttons
I / O ports are assigned as follows:
DEV_CLK: P44
K1: P29
K2: P28
K3: P27
K4: P26
When a key is pressed pin will be pulled LOW

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Buzzer
Drive P50 low to make noise with Buzzer.
General headers
I/O is also brought out to general headers JP1, JP2 and JP3.