Atmel ATmega8 User manual

Features
•High-performance, Low-power Atmel®AVR® 8-bit Microcontroller
•Advanced RISC Architecture
– 130 Powerful Instructions – Most Single-clock Cycle Execution
– 32 × 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16MIPS Throughput at 16MHz
– On-chip 2-cycle Multiplier
•High Endurance Non-volatile Memory segments
– 8Kbytes of In-System Self-programmable Flash program memory
– 512Bytes EEPROM
– 1Kbyte Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
•Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Three PWM Channels
– 8-channel ADC in TQFP and QFN/MLF package
Eight Channels 10-bit Accuracy
– 6-channel ADC in PDIP package
Six Channels 10-bit Accuracy
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
•Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
Standby
•I/O and Packages
– 23 Programmable I/O Lines
– 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF
•Operating Voltages
– 2.7V - 5.5V (ATmega8L)
– 4.5V - 5.5V (ATmega8)
•Speed Grades
– 0 - 8MHz (ATmega8L)
– 0 - 16MHz (ATmega8)
•Power Consumption at 4Mhz, 3V, 25C
– Active: 3.6mA
– Idle Mode: 1.0mA
– Power-down Mode: 0.5µA
8-bit Atmel with
8KBytes In-
System
Programmable
Flash
ATmega8
ATmega8L
Summary
Rev.2486AAS–AVR–02/2013

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2486AAS–AVR–02/2013
ATmega8(L)
Pin
Configurations
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
(INT1) PD3
(XCK/T0) PD4
GND
VCC
GND
VCC
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
PC1 (ADC1)
PC0 (ADC0)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK)
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
(T1) PD5
(AIN0) PD6 (AIN1) PD7
(ICP1) PB0
(OC1A) PB1
(SS/OC1B) PB2
(MOSI/OC2) PB3
(MISO) PB4
PD2 (INT0) PD1 (TXD) PD0 (RXD) PC6 (RESET) PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2)
TQFP Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
(RESET) PC6
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(XCK/T0) PD4
VCC
GND
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP1) PB0
PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
PC1 (ADC1)
PC0 (ADC0)
GND
AREF
AVCC
PB5 (SCK)
PB4 (MISO)
PB3 (MOSI/OC2)
PB2 (SS/OC1B)
PB1 (OC1A)
PDIP
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
MLF Top View
(INT1) PD3
(XCK/T0) PD4
GND
VCC
GND
VCC
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
PC1 (ADC1)
PC0 (ADC0)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK)
(T1) PD5
(AIN0) PD6 (AIN1) PD7
(ICP1) PB0
(OC1A) PB1
(SS/OC1B) PB2
(MOSI/OC2) PB3
(MISO) PB4
PD2 (INT0) PD1 (TXD) PD0 (RXD) PC6 (RESET) PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2)
NOTE:
The large center pad underneath the MLF
packages is made of metal and internally
connected to GND. It should be soldered
or glued to the PCB to ensure good
mechanical stability. If the center pad is
left unconneted, the package might
loosen from the PCB.

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2486AAS–AVR–02/2013
ATmega8(L)
Overview The Atmel®AVR®ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achieves
throughputs approaching 1MIPS per MHz, allowing the system designer to optimize power con-
sumption versus processing speed.
Block Diagram Figure 1. Block Diagram
INTERNAL
OSCILLATOR
OSCILLATOR
WATCHDOG
TIMER
MCU CTRL.
& TIMING
OSCILLATOR
TIMERS/
COUNTERS
INTERRUPT
UNIT
STACK
POINTER
EEPROM
SRAM
STATUS
REGISTER
USART
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
PROGRAMMING
LOGIC
SPI
ADC
INTERFACE
COMP.
INTERFACE
PORTC DRIVERS/BUFFERS
PORTC DIGITAL INTERFACE
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
+
-
PORTB DRIVERS/BUFFERS
PORTB DIGITAL INTERFACE
PORTD DIGITAL INTERFACE
PORTD DRIVERS/BUFFERS
XTAL1
XTAL2
CONTROL
LINES
VCC
GND
MUX &
ADC
AGND
AREF
PC0 - PC6 PB0 - PB7
PD0 - PD7
AVR CPU
TWI
RESET

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2486AAS–AVR–02/2013
ATmega8(L)
The Atmel®AVR®core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two inde-
pendent registers to be accessed in one single instruction executed in one clock cycle. The
resulting architecture is more code efficient while achieving throughputs up to ten times faster
than conventional CISC microcontrollers.
The ATmega8 provides the following features: 8 Kbytes of In-System Programmable Flash with
Read-While-Write capabilities, 512 bytes of EEPROM, 1 Kbyte of SRAM, 23 general purpose
I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare
modes, internal and external interrupts, a serial programmable USART, a byte oriented Two-
wire Serial Interface, a 6-channel ADC (eight channels in TQFP and QFN/MLF packages) with
10-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port,
and five software selectable power saving modes. The Idle mode stops the CPU while allowing
the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-
down mode saves the register contents but freezes the Oscillator, disabling all other chip func-
tions until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous timer
continues to run, allowing the user to maintain a timer base while the rest of the device is sleep-
ing. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous
timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the
crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very
fast start-up combined with low-power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
Flash Program memory can be reprogrammed In-System through an SPI serial interface, by a
conventional non-volatile memory programmer, or by an On-chip boot program running on the
AVR core. The boot program can use any interface to download the application program in the
Application Flash memory. Software in the Boot Flash Section will continue to run while the
Application Flash Section is updated, providing true Read-While-Write operation. By combining
an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATmega8 is a powerful microcontroller that provides a highly-flexible and cost-effective solution
to many embedded control applications.
The ATmega8 is supported with a full suite of program and system development tools, including
C compilers, macro assemblers, program simulators, and evaluation kits.
Disclaimer Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Minimum and Maxi-
mum values will be available after the device is characterized.

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2486AAS–AVR–02/2013
ATmega8(L)
Pin Descriptions
VCC Digital supply voltage.
GND Ground.
Port B (PB7..PB0)
XTAL1/XTAL2/TOSC1/
TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscil-
lator amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting
Oscillator amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1
input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in “Alternate Functions of Port B” on page
58 and “System Clock and Clock Options” on page 25.
Port C (PC5..PC0) Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
PC6/RESET If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical char-
acteristics of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.
The minimum pulse length is given in Table 15 on page 38. Shorter pulses are not guaranteed to
generate a Reset.
The various special features of Port C are elaborated on page 61.
Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega8 as listed on page
63.
RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page
38. Shorter pulses are not guaranteed to generate a reset.

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2486AAS–AVR–02/2013
ATmega8(L)
Ordering Information
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green
3. Tape & Reel
4. See characterization specification at 105C
Speed (MHz) Power Supply (V) Ordering Code(2) Package(1) Operation Range
8 2.7 - 5.5
ATmega8L-8AU
ATmega8L-8AUR(3)
ATmega8L-8PU
ATmega8L-8MU
ATmega8L-8MUR(3)
32A
32A
28P3
32M1-A
32M1-A Industrial
(-40C to 85C)
16 4.5 - 5.5
ATmega8-16AU
ATmega8-16AUR(3)
ATmega8-16PU
ATmega8-16MU
ATmega8-16MUR(3)
32A
32A
28P3
32M1-A
32M1-A
8 2.7 - 5.5
ATmega8L-8AN
ATmega8L-8ANR(3)
ATmega8L-8PN
ATmega8L-8MN
ATmega8L-8MUR(3)
32A
32A
28P3
32M1-A
32M1-A Industrial
(-40C to 105C)
16 4.5 - 5.5
ATmega8-16AN
ATmega8-16ANR(3)
ATmega8-16PN
ATmega8-16MN
ATmega8-16MUR(3)
32A
32A
28P3
32M1-A
32M1-A
Package Type
32A 32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
32M1-A 32-pad, 5 × 5 × 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

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2486AAS–AVR–02/2013
ATmega8(L)
Packaging Information
32A
TITLE DRAWING NO. REV.
32A, 32-lead, 7 x 7mm body size, 1.0mm body thickness,
0.8mm lead pitch, thin prole plastic quad at package (TQFP) C
32A
2010-10-20
PIN 1 IDENTIFIER
0°~7°
PIN 1
L
C
A1 A2 A
D1
D
eE1 E
B
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ABA.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 8.75 9.00 9.25
D1 6.90 7.00 7.10 Note 2
E 8.75 9.00 9.25
E1 6.90 7.00 7.10 Note 2
B 0.30 – 0.45
C 0.09 – 0.20
L 0.45 – 0.75
e 0.80 TYP
COMMON DIMENSIONS
(Unit of measure = mm)
SYMBOL MIN NOM MAX NOTE

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2486AAS–AVR–02/2013
ATmega8(L)
28P3
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
28P3, 28-lead (0.300"/7.62mm Wide) Plastic Dual
Inline Package (PDIP) B
28P3
09/28/01
PIN
1
E1
A1
B
REF
E
B1
C
L
SEATING PLANE
A
0º ~ 15º
D
e
eB
B2
(4 PLACES)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – – 4.5724
A1 0.508 – –
D 34.544 – 34.798 Note 1
E 7.620 – 8.255
E1 7.112 – 7.493 Note 1
B 0.381 – 0.533
B1 1.143 – 1.397
B2 0.762 – 1.143
L 3.175 – 3.429
C 0.203 – 0.356
eB – – 10.160
e 2.540 TYP
Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25mm (0.010").

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2486AAS–AVR–02/2013
ATmega8(L)
32M1-A
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
32M1-A, 32-pad, 5 x 5 x 1.0mm Body, Lead Pitch 0.50mm, E
32M1-A
5/25/06
3.10mm Exposed Pad, Micro Lead Frame Package (MLF)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D1
D
E1 E
e
b
A3
A2
A1
A
D2
E2
0.08 C
L
1
2
3
P
P
0
1
2
3
A 0.80 0.90 1.00
A1 – 0.02 0.05
A2 – 0.65 1.00
A3 0.20 REF
b 0.18 0.23 0.30
D
D1
D2 2.95 3.10 3.25
4.90 5.00 5.10
4.70 4.75 4.80
4.70 4.75 4.80
4.90 5.00 5.10
E
E1
E2 2.95 3.10 3.25
e 0.50 BSC
L 0.30 0.40 0.50
P – – 0.60
– – 12o
Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0
Pin 1 ID
Pin #1 Notch
(0.20 R)
K 0.20 – –
K
K

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2486AAS–AVR–02/2013
ATmega8(L)
Errata The revision letter in this section refers to the revision of the ATmega8 device.
ATmega8
Rev. D to I, M
•First Analog Comparator conversion may be delayed
•Interrupts may be lost when writing the timer registers in the asynchronous timer
•Signature may be Erased in Serial Programming Mode
•CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32KHz Oscillator is
Used to Clock the Asynchronous Timer/Counter2
•Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request
1. First Analog Comparator conversion may be delayed
If the device is powered by a slow rising VCC, the first Analog Comparator conversion will
take longer than expected on some devices.
Problem Fix / Workaround
When the device has been powered or reset, disable then enable theAnalog Comparator
before the first conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronized to the asynchronous timer
clock is written when the asynchronous Timer/Counter register(TCNTx) is 0x00.
Problem Fix / Workaround
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor
0x00 before writing to the asynchronous Timer Control Register(TCCRx), asynchronous
Timer Counter Register(TCNTx), or asynchronous Output Compare Register(OCRx).
3. Signature may be Erased in Serial Programming Mode
If the signature bytes are read before a chiperase command is completed, the signature may
be erased causing the device ID and calibration bytes to disappear. This is critical, espe-
cially, if the part is running on internal RC oscillator.
Problem Fix / Workaround:
Ensure that the chiperase command has exceeded before applying the next command.
4. CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32KHz
Oscillator is Used to Clock the Asynchronous Timer/Counter2
When the internal RC Oscillator is used as the main clock source, it is possible to run the
Timer/Counter2 asynchronously by connecting a 32KHz Oscillator between XTAL1/TOSC1
and XTAL2/TOSC2. But when the internal RC Oscillator is selected as the main clock
source, the CKOPT Fuse does not control the internal capacitors on XTAL1/TOSC1 and
XTAL2/TOSC2. As long as there are no capacitors connected to XTAL1/TOSC1 and
XTAL2/TOSC2, safe operation of the Oscillator is not guaranteed.
Problem Fix / Workaround
Use external capacitors in the range of 20pF - 36pF on XTAL1/TOSC1 and XTAL2/TOSC2.
This will be fixed in ATmega8 Rev. G where the CKOPT Fuse will control internal capacitors
also when internal RC Oscillator is selected as main clock source. For ATmega8 Rev. G,
CKOPT = 0 (programmed) will enable the internal capacitors on XTAL1 and XTAL2. Cus-
tomers who want compatibility between Rev. G and older revisions, must ensure that
CKOPT is unprogrammed (CKOPT = 1).