Altera Cyclone III FPGA User manual

101 Innovation Drive
San Jose, CA 95134
www.altera.com
Cyclone III FPGA Starter Board
Reference Manual
Document Date: October 2007

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ii Reference Manual0Altera Corporation
Cyclone III FPGA Starter Board October 2007
Part Number MNL-01016-1.1

Altera Corporation iii
October 2007 Preliminary
Contents
Chapter 1. Introduction
General Description ............................................................................................................................... 1–1
Board Component Blocks ................................................................................................................ 1–2
Block Diagram .................................................................................................................................. 1–3
Handling the Board ............................................................................................................................... 1–3
Chapter 2. Board Components & Interfaces
Board Overview ..................................................................................................................................... 2–1
Featured Device ..................................................................................................................................... 2–5
Clocking Circuitry ................................................................................................................................. 2–6
Jumpers ................................................................................................................................................... 2–7
Interfaces ................................................................................................................................................. 2–8
USB Interface ..................................................................................................................................... 2–8
HSMC Expansion Connector .......................................................................................................... 2–9
General User Interfaces ................................................................................................................. 2–10
Push Buttons .............................................................................................................................. 2–13
LEDs ............................................................................................................................................ 2–14
Memory ................................................................................................................................................. 2–16
Parallel Flash ................................................................................................................................... 2–16
DDR SDRAM .................................................................................................................................. 2–18
SSRAM ............................................................................................................................................. 2–19
Power Supply ....................................................................................................................................... 2–22
Statement of China-RoHS Compliance ............................................................................................ 2–23
Additional Information
Revision History ............................................................................................................................... Info–i
How to Contact Altera ..................................................................................................................... Info–i
Typographic Conventions .............................................................................................................. Info–ii

iv Altera Corporation
Preliminary October 2007
Contents Stratix Device Handbook, Volume 1

Altera Corporation Reference Manual 1–1
October 2007 Preliminary
1. Introduction
General
Description
This reference manual provides comprehensive information about the
Altera®Cyclone®III family of devices and the Cyclone III FPGA starter
board.
The Cyclone®III starter board provides a hardware platform that offers a
unique opportunity to customize your development environment via
expansion connectors and daughter cards as well as evaluate the feature-
rich, low-power Altera®Cyclone III device.
For more functionality, the starter board can be expanded through
daughter cards connected to the Altera High Speed Mezzanine Card
(HSMC) connector. Altera and development kit partners are creating
HSMC daughter cards that allow you to expand the functionality of the
board.
fFor the latest information about available HMSC daughter cards, go to
www.altera.com/products/devkits/kit-index.html.
The main features of the Cyclone III starter board are:
■Low-power consumption Altera Cyclone III EP3C25 chip in a
324-pin FineLine BGA (FBGA) package
■Expandable through HSMC connector
■32-Mbyte DDR SDRAM
■16-Mbyte parallel flash device for configuration and storage
■1 Mbyte high-speed SSRAM memory
■Four user push-button switches
■Four user LEDs
The main advantages of the Cyclone III starter board are:
■Facilitates a fast and successful FPGA design experience with helpful
example designs and demonstrations.
■Directly configure and communicate with the Cyclone III device via
the on-board USB-Blaster™circuitry and JTAG header
■Active Parallel flash configuration
■Low power consumption
■Cost-effective modular design

1–2 Reference Manual Altera Corporation
Cyclone III FPGA Starter Board October 2007
General Description
Board Component Blocks
■Altera Cyclone III EP3C25F324 FPGA
●25K logic elements (LEs)
●66 M9K memory blocks (0.6 Mbits)
●16 18x18 multiplier blocks
●Four PLLs
●214 I/Os
■Clock management system
●One 50 MHz clock oscillator to support a variety of protocols
●The Cyclone III device distributes the following clocks from its
on-board PLLs:
•DDR clock
•SSRAM clock
•Flash clock
■HSMC connector
●Provides 12 V and 3.3 V interface for installed daughter cards
●Provides up to 84 I/O pins for communicating with HSMC
daughter cards
■General user-interface
●Four user LEDs
●Two board-specific LEDs
●Push-buttons:
•System reset
•User reset
•Four general user push-buttons
■Memory subsystem
●Synchronous SRAM device
•1-Mbyte standard synchronous SRAM
•167-MHz
•Shares bus with parallel flash device
●Parallel flash device
•16-Mbyte device for active parallel configuration and
storage
•Shares bus with SRAM device
●DDR SDRAM device
•56-pin, 32-Mbyte DDR SDRAM
•167-MHz
•Connected to FPGA via dedicated 16-bit bus
■Built-in USB-Blaster interface
●Using the Altera EPM3128A CPLD
●For external configuration of Cyclone III device
●For system debugging using the SignalTap®and Nios®
debugging console
●Communications port for Board Diagnostic graphical user
interface (GUI)

Altera Corporation Reference Manual 1–3
October 2007 Cyclone III FPGA Starter Board
Introduction
Block Diagram
Figure 1–1 shows a functional block diagram of the Cyclone III FPGA
starter board.
Figure 1–1. Cyclone III FPGA Starter Board
Handling the
Board
When handling the board, it is important to observe the following
precaution:
cStatic Discharge Precaution—Without proper anti-static handling,
the board can be damaged. Therefore, use anti-static handling
precautions when touching the board.
84
HSMC
4
Switches
4
LEDs
4
Parallel Flash
16MB
SSRAM
1MB
4
USB
Blaster
4
DDR
32MB
42
72
Cyclone III
EP3C25F324

1–4 Reference Manual Altera Corporation
Cyclone III FPGA Starter Board October 2007
Handling the Board

Altera Corporation Reference Manual 2–1
October 2007 Preliminary
2. Board Components &
Interfaces
Board Overview This chapter provides operational and connectivity detail for the board’s
major components and interfaces and is divided into the following major
blocks:
■Featured device
■Clocking circuitry
■Jumpers
■Interfaces
●USB interface
●Altera®HSMC expansion connector
●General user interfaces
■Memory
■Power supply
■Statement of China-RoHS compliance
1Board schematics, the physical layout database, and
manufacturing files for the Cyclone®III FPGA starter board are
included in the Cyclone III FPGA Starter Kit in the following
directory:
altera\<version#>\kits\cycloneIII_3c25_start\board_design_files
fFor information on powering-up the Cyclone III FPGA starter board and
installing the demo software, refer to the Cyclone III FPGA Starter Kit
Getting Started User Guide.

2–2 Reference Manual Altera Corporation
Cyclone III FPGA Starter Board October 2007
Board Overview
Figure 2–1 shows the top view of the Cyclone III FPGA starter board.
Figure 2–1. Top View of the Cyclone III FPGA Starter Board
Cyclone III Device (U1)
User Push Button Switches
User LEDs
USB
UART (U8)
HSMC
Connector (J1)
DC Power
Input (J2)
Power Switch
(SW1)
USB
Connector
(J3)
Configuration Done LED
32-Mbyte
DDR SDRAM (U4)
Flash LED
1-Mbyte SSRAM (U5)
50-MHz
System Clock
Reconfigure
and Reset
Push Buttons
16-Mbyte
Parallel
Flash (U6)
JTAG Header (J4)
2.5 V I/O Power
Measurement (JP3)
FPGA Core Power
Measurement (JP6)

Altera Corporation Reference Manual 2–3
October 2007 Cyclone III FPGA Starter Board
Board Components & Interfaces
Figure 2–2 shows the diagonal view of the Cyclone III FPGA starter
board.
Figure 2–2. Diagonal View of the Cyclone III FPGA Starter Board

2–4 Reference Manual Altera Corporation
Cyclone III FPGA Starter Board October 2007
Board Overview
Table 2–1 describes the components and lists their corresponding board
references.
Table 2–1. Cyclone III FPGA Starter Board (Part 1 of 2)
Type Component/
Interface Board Reference Description Page
Featured Device
FPGA Cyclone III
device
U1 EP3C25F324-C8, 324-pin FineLine BGA
(FBGA) package
2–5
User Interfaces
I/O Push-button
switches
Button1–Button4, CPU
Reset, Reconfigure
Four push-button switches for user-defined,
logic inputs.
2–13
I/O LEDs LED1–LED4,
Conf_Done, Link,
Power, Flash_CEN,
Load
Four user-defined LEDs 2–14
Connections & Interfaces
I/O USB UART U8 USB interface to the Cyclone III device for
external FPGA configuration and
communication with applications running on
the FPGA.
2–8
Input HSMC
Connector
J1 Header for connecting the HSMC interface. 2–9
Configuration & Reset
Input JTAG header J4 Jumper header to select which JTAG source
the board uses, i.e., the JTAG header
configuration or the USB JTAG configuration.
2–8
Input USB
connector
J3 Type B USB Connector that allows for
connecting a Type A-B USB cable between a
PC and the board.
2–8
Display Configuration
done LED
Conf_Done LED that illuminates when FPGA is
successfully configured.
2–14
Memory
Flash 16 Mbytes of
parallel flash
memory
U6 16 Mbytes of non-volatile memory. 2–16
Display Flash LED LED that illuminates when the flash is being
accessed.
N/A
SSRAM 1 Mbyte
high-speed
SSRAM
U5 256K x 32 synchronous SRAM 2–20
DDR SDRAM 32-Mbyte
DDR SDRAM
U4 4M x16 x 4 DDR SDRAM 2–18

Altera Corporation Reference Manual 2–5
October 2007 Cyclone III FPGA Starter Board
Board Components & Interfaces
Featured
Device
The Cyclone III FPGA Starter Kit features the EP3C25F324 device (U1) in
a 324-pin FineLine BGA (FBGA) package.Table 2–2 lists Cyclone III
device features.
Clock Circuitry
Oscillator Clock Y1 50-MHz clock oscillator used for the system
clock.
2–6
Power Supply
Input DC power
jack
J2 12-V DC unregulated power source. 2–22
Input Power switch SW1 Switches the board’s power on and off. 2–22
Probe point Current sense
resistor
JP6 Measure FPGA core power using current
sense resistor.
N/A
Probe point Current sense
resistor
JP3 Measure 2.5 V I/O power (shared between
devices) using current sense resistor.
N/A
Table 2–1. Cyclone III FPGA Starter Board (Part 2 of 2)
Type Component/
Interface Board Reference Description Page
Table 2–2. Cyclone III Device Features
Architectural
Feature Results
Altera’s
third-generation of
low-cost FPGAs
●Lowest overall FPGA system cost available
●Staggered I/O ring to decrease die area
●Wide range of low-cost packages
●Support for low-cost serial and parallel flash for configuration options
Lowest power
consumption
FPGA available
●Based on the TSMC’s low-power 65nm process
●Supports hot-socketing
●Unused I/O banks can be powered down
●Extends battery life for portable or hand-held applications
●Eliminates or reduces cooling system costs
Increased system
integration
●Densities up to 119,088 logic elements
●High memory-to-logic ratio
●Highest multiplier-to-logic ratio in the industry
●Up to four dynamically reconfigurable, cascadable phase-locked-loops (PLLs), each
with up to five outputs
●Multi-value on-chip termination (OCT) support with calibration feature.

2–6 Reference Manual Altera Corporation
Cyclone III FPGA Starter Board October 2007
Clocking Circuitry
Table 2–3 lists the Cyclone III EP3C25F324 device pin count.
You can configure the Cyclone III device via the on-board USB-Blaster™or
through the JTAG interface using an external programming cable (sold
separately).
fFor additional information about Altera devices, go to
www.altera.com/products/devices.
Clocking
Circuitry
The Cyclone III FPGA starter board’s clocking circuitry is designed to be
simple and easy to use. A single 50-MHz clock input is used and all other
clocks are generated using the Cyclone III device’s phase-locked loops
(PLLs). The dedicated PLLs are used to distribute the flash, SSRAM, and
HSMC clocks.
Table 2–4 shows the clock pinout.
Table 2–3. Cyclone III Device Pin Count
Board Component Pins
SRAM/flash (shared bus) 72
SDRAM (DDR) 42
Push buttons 4
LEDs 4
USB-Blaster/configuration 4
HSMC 84
Total Pins Used 210
Total EP3C25F324 pins 214
Unused pins 4 (1)
Note to Ta ble 2 –3:
(1) In some DDR designs, you will be unable to use some of the other I/Os that share
the same VREF banks with the DDR. Therefore, if you have added DDR to your
system, you will need to remove two or three LEDs or I/Os for the HSMC
connector, which shares the same VREF bank as the DDR.
Table 2–4. Clock Pinout
Signal Name FPGA Pin Direction Type
50MHz B9 Input 2.5 V

Altera Corporation Reference Manual 2–7
October 2007 Cyclone III FPGA Starter Board
Board Components & Interfaces
Figure 2–3 shows the simplest clocking scheme with a single clock input;
however, much more complex clocking schemes can be implemented
with CycloneIIIFPGAs.
Figure 2–3. Cyclone III FPGA Starter Board’s Clocking Scheme
Jumpers Table 2–5 lists board jumpers and jumper operational descriptions.
50 MHz
Oscillator
16 MB
Parallel Flash
SSRAM
HSMC
Cyclone III
EP3C25F324
V9
32 MB DDR
Note: Reference numbers are FPGA pin numbers.
Out:
A1,
C14,
D14,
V18,
U18 In:
A9
F18,
F17
N18,
N17
U2, V2
A2
H4
Table 2–5. Board Jumpers (Part 1 of 2)
JumperBoard
Reference Jumper Operational Descriptions
JP1 and JP2 Removing both shunts adds the HSMC connector to the JTAG
chain. If the shunts are in place on both jumpers, then the HSMC
connector is removed from the JTAG chain.
JP3 Sense resistor for measuring the power consumed by the 2.5 V
supply to VCCIO,the DDR, the flash I/O, and the SSRAM.
JP4 1.25 V termination supply for DDR2. To supply an external
voltage, remove the jumper and connect the external supply to
pin 2. (Pin 2 has a rounded shape on the bottom of the board.)

2–8 Reference Manual Altera Corporation
Cyclone III FPGA Starter Board October 2007
Interfaces
Interfaces This section describes the following Cyclone III FPGA starter board’s
interface blocks:
■USB interface
■HSMC expansion connector
■General user interfaces
USB Interface
The USB-Blaster circuitry is built onto the board. You can simply plug the
USB cable (provided with the kit) into USB connector J3 on the board and
the other end to a USB port on your computer to program and
communicate with the Cyclone III device via the JTAG port.
A USB physical connection is used to enable computers to communicate
with the starter board. To simplify the USB interface, the board contains a
FTDI FT2232L USB universal asynchronous receiver/transmitter (UART)
circuit. The data from the FTDI chip is translated into a JTAG stream
using the Altera EPM3128A CPLD connected to the Cyclone III device’s
dedicated JTAG port.
The 5 V supply for the FTDI device is drawn from the USB connection.
The rest of the circuit operates on 3.3 V supply with 100 mA maximum
and 1.8 V supply with 900 mA maximum voltage.
JP5 3.3 V supply for the MAX device and HSMC. To supply an
external voltage, remove the jumper and connect the external
supply to pin 2. (Pin 2 has a rounded shape on the bottom of the
board.)
JP6 Sense resistor for measuring the power consumed by the 1.2 V
VCCINT supply to the Cyclone III device.
JP7 1.8 V power supply to flash device. To supply an external
voltage, remove the jumper and connect the external supply to
pin 2. (Pin 2 has a rounded shape on the bottom of the board.)
JP8 Adding the shunt enables configuration of the Cyclone III device
using the JTAG header and an external USB-Blaster. When the
shunt is not in place, the embedded USB-Blaster circuitry must
be used to configure the Cyclone III device. (The board ships
without the JTAG header populated.)
Table 2–5. Board Jumpers (Part 2 of 2)
JumperBoard
Reference Jumper Operational Descriptions

Altera Corporation Reference Manual 2–9
October 2007 Cyclone III FPGA Starter Board
Board Components & Interfaces
HSMC Expansion Connector
The board provides one HSMC connector. The HSMC connector is a
modified version of standard high-speed Samtec connectors. To provide
better signal integrity between host boards and daughter cards when
using high-speed transceivers, the standard high-speed Samtec connector
is modified by removing every third pin in bank -1.
1CMOS utilization of the HSMC pins is assumed and no options
for supporting other differential signaling is provided with the
board. The eight clock-data-recovery high-speed transceiver
channels are not connected.
Table 2–6 lists the ordering codes and shows the relationship between the
standard Samtec Q-series connectors and the modified parts’ ordering
codes.
The board provides both 12 V unregulated and 3.3 V regulated power
supply to the HSMC connector for any installed daughter cards.
fFor more information regarding the HSMC, refer to the High Speed
Mezzanine Card Electrical and Mechanical Specification version 1.2 or later.
Table 2–7 lists the guaranteed minimum on-board power supply levels.
The power rails are delivered via designated pins on the HSMC
connector.
Table 2–6. Altera-Specific & Standard Samtec Part Numbers
Altera-Specific Samtec
Part Number
Standard Samtec Part
Number
Daughter cards ASP-122952-01 QTH-090-01-L-D-A
Host boards ASP-122953-01 QTH-090-01-L-D-A
Table 2–7. HSMC Power Requirements
Voltage Current Rating Maximum Voltage
12 V 1.0 A 12.0 W
3.3 V 2.0 A 6.6 W

2–10 Reference Manual Altera Corporation
Cyclone III FPGA Starter Board October 2007
Interfaces
Table 2–8 lists HSMC A connector board reference and manufacturing
information.
The HSMC uses the Samtec connector’s header provided on the board.
Figure 2–4 shows the outline of the Samtec header.
Figure 2–4. Samtec Connector’s Header
Table 2–9 lists the HSMC Port A interface pins. Signal names and
directions are relative to the Cyclone III FPGA. (The HSMC is operating
as the host.)
General User Interfaces
To allow you to fully leverage the I/O capabilities of the Cyclone III
device, the following are available on the board (remaining I/Os are
connected to additional board resources):
■Push buttons: System and user reset, and user-defined push buttons
■LEDs: Board-specific and user-defined LEDs
Some of the board’s buttons and LEDs have a specific board function
while others are user-defined and are provided to control FPGA designs.
Table 2–8. HSMC A Connector Manufacturing Information
Board Reference Description Manufacturer Manufacturer
Part Number
J1 High speed
Mezzanine card
connector
Samtec ASP-12953-01
2.413
((90 POS / 30 x .7875) + .050)
.78 REF
.626 REF
.036 REF .006 REF
.245 REF
.150 REF
01
02
.285 REF
DP Bank
.571
(29 EQ Spaces @ .0197)

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October 2007 Cyclone III FPGA Starter Board
Board Components & Interfaces
Table 2–9. HSMC Pinout (Part 1 of 3)
Signal Name FPGA Pin Name Direction Type HSMC Pin
HSMC_SDA E1 Bidirectional 2.5 V 33
HSMC_SCL F3 Bidirectional 2.5 V 34
HSMC_TCK J1 35
HSMC_TMS J2 36
HSMC_TDI J6 37
HSMC_TDO J5 38
HSMC_CLKOUT0 A1 Output 2.5 V 39
HSMC_CLKIN0 A9 Input 2.5 V 40
HSMC_CLKOUT_p1 D14 Output 2.5 V 95
HSMC_CLKIN_p1 F17 Input 2.5 V 96
HSMC_CLKOUT_n1 C14 Output 2.5 V 97
HSMC_CLKIN_n1 F18 Input 2.5 V 98
HSMC_CLKOUT_p2 U18 Output 2.5 V 155
HSMC_CLKIN_p2 N17 Input 2.5 V 156
HSMC_CLKOUT_n2 V18 Output 2.5 V 157
HSMC_CLKIN_n2 N18 Input 2.5 V 158
HSMC_D0 H6 Bidirectional 2.5 V 41
HSMC_D1 D3 Bidirectional 2.5 V 42
HSMC_D2 M5 Bidirectional 2.5 V 43
HSMC_D3 L6 Bidirectional 2.5 V 44
HSMC_D4 T1 Bidirectional 2.5 V 47
HSMC_D5 M3 Bidirectional 2.5 V 48
HSMC_D6 N7 Bidirectional 2.5 V 49
HSMC_D7 T2 Bidirectional 2.5 V 50
HSMC_D8 N8 Bidirectional 2.5 V 53
HSMC_D9 H15 Bidirectional 2.5 V 54
HSMC_D10 J13 Bidirectional 2.5 V 55
HSMC_D11 H16 Bidirectional 2.5 V 56
HSMC_D12 N10 Bidirectional 2.5 V 59
HSMC_D13 N16 Bidirectional 2.5 V 60
HSMC_D14 N11 Bidirectional 2.5 V 61
HSMC_D15 N15 Bidirectional 2.5 V 62
HSMC_D16 K17 Bidirectional 2.5 V 65
HSMC_D17 R16 Bidirectional 2.5 V 66

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Cyclone III FPGA Starter Board October 2007
Interfaces
HSMC_D18 P11 Bidirectional 2.5 V 67
HSMC_D19 T16 Bidirectional 2.5 V 68
HSMC_TX_p4 B2 Bidirectional 2.5 V 71
HSMC_RX_p4 C2 Bidirectional 2.5 V 72
HSMC_TX_n4 B1 Bidirectional 2.5 V 73
HSMC_RX_n4 C1 Bidirectional 2.5 V 74
HSMC_TX_p5 G2 Bidirectional 2.5 V 77
HSMC_RX_p5 H2 Bidirectional 2.5 V 78
HSMC_TX_n5 G1 Bidirectional 2.5 V 79
HSMC_RX_n5 H1 Bidirectional 2.5 V 80
HSMC_TX_p6 K2 Bidirectional 2.5 V 83
HSMC_RX_p6 K5 Bidirectional 2.5 V 84
HSMC_TX_n6 K1 Bidirectional 2.5 V 85
HSMC_RX_n6 L5 Bidirectional 2.5 V 86
HSMC_TX_p7 L2 Bidirectional 2.5 V 89
HSMC_RX_p7 L4 Bidirectional 2.5 V 90
HSMC_TX_n7 L1 Bidirectional 2.5 V 91
HSMC_RX_n7 L3 Bidirectional 2.5 V 92
HSMC_TX_p8 M2 Bidirectional 2.5 V 101
HSMC_RX_p8 P2 Bidirectional 2.5 V 102
HSMC_TX_n8 M1 Bidirectional 2.5 V 103
HSMC_RX_n8 P1 Bidirectional 2.5 V 104
HSMC_TX_p9 R2 Bidirectional 2.5 V 107
HSMC_RX_p9 T3 Bidirectional 2.5 V 108
HSMC_TX_n9 R1 Bidirectional 2.5 V 109
HSMC_RX_n9 R3 Bidirectional 2.5 V 110
HSMC_TX_p10 E17 Bidirectional 2.5 V 113
HSMC_RX_p10 G17 Bidirectional 2.5 V 114
HSMC_TX_n10 E18 Bidirectional 2.5 V 115
HSMC_RX_n10 G18 Bidirectional 2.5 V 116
HSMC_TX_p11 H17 Bidirectional 2.5 V 119
HSMC_RX_p11 K18 Bidirectional 2.5 V 120
HSMC_TX_n11 H18 Bidirectional 2.5 V 121
HSMC_RX_n11 L18 Bidirectional 2.5 V 122
Table 2–9. HSMC Pinout (Part 2 of 3)
Signal Name FPGA Pin Name Direction Type HSMC Pin