Texas Instruments TPS65941212-Q1 User manual

User’s Guide
TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide
for Jacinto™ 7 J721E, PDN-0B
ABSTRACT
This user’s guide can be used as a guide for integrating the TPS65941212-Q1 and TPS65941111-Q1 power
management integrated circuits (PMICs) into a system powering the Automotive Jacinto™ 7 DRA829 or
TDA4VM processor.
Table of Contents
1 Introduction.............................................................................................................................................................................2
2 Device Versions...................................................................................................................................................................... 2
3 Processor Connections..........................................................................................................................................................4
3.1 Power Mapping.................................................................................................................................................................. 4
3.2 Control Mapping.................................................................................................................................................................7
4 Supporting Functional Safety Systems..............................................................................................................................10
4.1 Achieving ASIL-B System Requirements......................................................................................................................... 11
4.2 Achieving up to ASIL-D System Requirements................................................................................................................11
5 Static NVM Settings..............................................................................................................................................................13
5.1 Application-Based Configuration Settings........................................................................................................................13
5.2 Device Identification Settings........................................................................................................................................... 14
5.3 BUCK Settings................................................................................................................................................................. 14
5.4 LDO Settings....................................................................................................................................................................16
5.5 VCCA Settings................................................................................................................................................................. 17
5.6 GPIO Settings.................................................................................................................................................................. 17
5.7 Finite State Machine (FSM) Settings............................................................................................................................... 20
5.8 Interrupt Settings..............................................................................................................................................................20
5.9 POWERGOOD Settings...................................................................................................................................................23
5.10 Miscellaneous Settings.................................................................................................................................................. 24
5.11 Interface Settings............................................................................................................................................................25
5.12 Multi-Device Settings..................................................................................................................................................... 26
5.13 Watchdog Settings......................................................................................................................................................... 26
6 Pre-Configurable Finite State Machine (PFSM) Settings.................................................................................................. 26
6.1 Configured States............................................................................................................................................................ 27
6.2 PFSM Triggers................................................................................................................................................................. 28
6.3 Power Sequences............................................................................................................................................................ 29
7 Impact of NVM Changes.......................................................................................................................................................49
8 References............................................................................................................................................................................ 50
9 Revision History................................................................................................................................................................... 50
Trademarks
Jacinto™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
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1 Introduction
This user’s guide describes a power distribution network (PDN), PDN-0B, between two TPS6594-Q1 devices
and either DRA829V or TDA4VM processor with independent MCU and Main power rails. This PDN enables
board level isolation of the processor MCU and Main voltage resources as required to leverage the processor
architecture in implementing two desirable end product features:
1. MCU processor acts as independent safety monitor (MCU Safety Island) over the Main processing
resources to ensure safe system operations.
2. MCU processor maintains minimum system operations (MCU Only) to significantly reduce processor power
dissipation thereby extending battery life during stand-by use cases and reducing component temperature.
This description includes the following to clarify platform system operation:
1. PDN power resource connections
2. PDN digital control connections
3. Primary and secondary PMIC default NVM contents
4. PMIC sequencing settings to support different PDN power state transitions for an advanced processor
system
PMIC and processor data manuals describe recommended operation, electrical characteristics, external
components, package details, register maps, and overall component functionality. In the event of any
inconsistency between any user's guide, application report, or other referenced material, the data sheet
specification is the definitive source.
2 Device Versions
There are different orderable part numbers (PNs) of the TPS6594-Q1 device available with unique NVM settings
to support different end product use cases and processor types. The unique NVM settings for each PMIC
device is optimized per PDN design to support different processors, processing loads, SDRAM types, system
functional safety levels, and end product features (such as low power modes, processor voltages, and memory
subsystems). The NVM settings can be identified by both NVM_ID and NVM_REV registers. Each PMIC device
is distinguished by the part number, NVM_ID, and NVM_REV values listed in Table 2-1.
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Table 2-1. Dual TPS6594-Q1 Orderable Part Numbers for Independent MCU and Main PDN System
PDN USE CASE PDN Orderable Part Number TI_NVM_ID
(TI_NVM_REV
)
Orderable Part
Number
TI_NVM_I
D
(TI_NVM
_REV)
Error
Signal
Monitor
ing
• Up to 9 A(1) on the Primary PMIC 3-phase
CPU rail
• Up to 12 A1 on the Secondary PMIC 4-
phase CORE rail
• Up to 3.4 A(1) on the SDRAM, with support
for LPDDR4
• Supports Processor 2 GHz maximum
clock with high-speed SERDES operations
• Supports 32 Gb of LPDDR4 SDRAM with
4266MTs data rate
• Supports Functional Safety up to ASIL-D
level with MCU Safety Island
• Supports MCU-only and DDR_Retention
low power modes
• Supports I/O level of 3.3 V or 1.8 V
• Supports optional end product features:
– Compliant high-speed SD Card
memory
– Compliant USB 2.0 Interface
– On-board Efuse programming of high
security processors
0B TPS65941212RWERQ1 0x12 (0x03) TPS65941111R
WERQ1
0x11
(0x03)
Combin
ed MCU
and
SOC
0C TPS65941213RWERQ1 0x13 (0x04) TPS65941111R
WERQ1
0x11
(0x03)
Dedicat
ed MCU
and
SOC
(1) TI recommends having 15% margin between the maximum expected load current and the maximum current allowed per each PMIC
output rail.
Note
PDN-0C is recommended for all new designs and designs needing the additional functional safety
coverage provided afforded by the GPIO optimizations found in PDN-0C. This document describes
PDN-0B.
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3 Processor Connections
This section details how the dual TPS6594-Q1 power resources and GPIO signals are connected to the
processor and other peripheral components in order to support the PDN use case.
3.1 Power Mapping
Figure 3-1 shows the power mapping between the dual TPS6594-Q1 PMIC power resources and processor
voltage domains required to support independent MCU and Main power rails. In this configuration, both PMICs
use a 3.3 V input voltage. For Functional Safety applications, there is a protection FET before VCCA that
connects to the OVPGDRV pin of the primary PMIC, allowing voltage monitoring of the input supply to the
PMICs.
The VCCA voltage must be the first voltage applied to the PMIC devices. VIO_IN of the PMICs must not
be supplied before VCCA. A load switch supplies VIO_IN in this PDN. This load switch also supplies the
VDDSHVx_MCU voltage domain of the processor. This allows PMIC GPIO control signals referenced to VIO_IN
to remain active during MCU Only low power mode and to be disabled during DDR Retention (aka Suspend-to-
RAM) to reduce PMIC power.
For SD card dual-voltage I/O support (3.3 V and 1.8 V), LDO1 of the TPS659411-Q1 device can be used. A
processor GPIO control signal with a logic high default value is used to set SD VIO to 3.3 V initially. During
processor power up, the boot loader SW can set GPIO signal low to select 1.8 V level as needed for high-speed
card operation per SD specification. This allows control of the LDO1 voltage without the need for the MCU
processor to establish I2C communication with the PMICs during boot from SD card operations.
This PDN uses four discrete power components with three being required and one is optional depending
upon end product features. The two TPS22965-Q1 Load Switches connect VCCA_3V3 power rail to supply
OV protected 3.3 V to processor I/O domains. Two load switches are required in order to enable isolation
between MCU and Main processor sub-sections for MCU Safety Island or MCU Only low power operations. The
TPS62813-Q1 Buck Converter supplies LPDDR4 SDRAM component with required 1.1V supply. The unused
primary PMIC FB pin, FB_B3, has been configured per NVM settings, Table 5-3, to provide voltage monitoring
for VDD_DDR_1V1 power rail if an end product OV/UV monitoring requirements include this supply. The one
optional discrete power component is TLV73318-Q1 LDO that can be used if an end product uses a high security
processor type and desires the capability to program Efuse values on-board. If this feature is not desired, then
this LDO can be omitted and processor VPP pins treated per data manual recommendations.
Note
The PMIC voltage monitor on FB_B3 must be connected to 1.1 V. The VMON_ABIST_EN=1 for both
the primary and secondary PMICs. If 1.1 V is not connected to FB_B3 when the monitor is enabled
then the self-test fails and the BIST_FAIL_INT interrupt is set and the device goes to the safe state
and main processor voltages are disabled.
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TPS65941212-Q1
BUCK4
(4A max)
BUCK5
(2A max)
LDO1
(500mA max)
LDO2
(500mA max)
LDO3
(500mA max)
LDO4
(300mA max)
PRIMARY PMIC
Processor
MAIN PROCESSOR
VDD_CORE
VDDAR_CPU/CORE
VDDS_DDR_BIAS
VDD_PHY_1V8
VDD_CPU_AVS*
MAIN ANALOG
VDDA_1P8_PHYs
VDDA_0P8_PHYs
VDDA_0P8_PLLs/DLLs
VDDA_1P8_PLLs
VDDA_3P3_USB
MAIN DIGITAL
VDDSHV0-4
VDDSHV6
VDDS_MMC0
VDD1_DDR_1V8
MCU SAFETY ISLAND
VDD_MCU
VDDAR_MCU
VDDSHVx_MCU (1.8V)
System
VPP_x (EFUSE)
VDD_MCU_0 V85
VDA_MCU_1V8
VDDSHVx_MCU (3.3V)
VDA_DLL_0V8
TPS22965-Q1
(load switch, 4A max)
VDD_MCUIO_3V3
VDD_MCUIO_1V8
LPDDR4
VDD1
VDD2
3.3V
VDD_CPU (AVS)
VCCA
OVPGDRV
VIO_IN
BUCK1 + BUCK2
+ BUCK3
(10.5A max)
VDDSHV5
TLV73318P-Q1
(LDO, 300mA max)
TPS62813-Q1
(BUCK, 3A max)
VDD_IO_3V3
VPP_EFUSE_1V 8
VDD_DDR_1V1
VDDA_x
VDDS_DDR_IO
VDDQ
Octal SPI FLASH
Hyper FLASH
EMMC
VCCQ
VCC
TPS65941111-Q1
BUCK5
(2A max)
LDO1
(500mA max)
LDO2
(500mA max)
LDO3
(500mA max)
LDO4
(300mA max)
SECONDARY PMIC
VCCA
OVPGDRV
VIO_IN
BUCK1 + BUCK2
+ BUCK3 + BUCK4
(14A max)
VDD_CORE_0V8
TPS22965-Q1
(load switch, 4A max)
VDD_RAM_0V85
UFS
VCCQ
VCC
FB_B3 (pin 49)
LDO
PDN Features
Base PDN
MCU-only
Suspend-to-RAM
BUCK
Processor
Processor Sub-group
Processor Voltage
Domains
Power Components
System Group
System Sub-group
System Rail
VDD_SD_DV**
VDD_USB_3V 3
VDD_IO_1V8
VDA_PLL_1V8
Figure 3-1. Power Connections
• * VDD_CPU_AVS, boot voltage of 0.8 V then software sets device specific AVS; 0.68 V – 0.72 V.
• ** VDD_SD_DV, 3.3 V then software changes to 1.8 V per HS-SD.
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Table 3-1 identifies which power resources are required to support different system features. If the system
feature listed is not required, the power resource connection can be removed and the processor voltage domains
need to be grouped into alternative power rails.
Table 3-1. PDN Power Mapping and System Features
Power Mapping System Features
Device Power
Resource Power Rails Processor and Memory Domains Active SoC MCU - only Suspend- to-RAM SD Card USB Interface
TPS659412
12-Q1
BUCK123 VDD_CPU_
AVS VDD_CPU Required
FB_B3 VDDS_DDR_BIAS,
VDDS_DDR_IO, LPDDR4 Required Required
BUCK4 VDD_MCU_
0V85 VDDAR_MCU, VDD_MCU Required Required
BUCK5 VDD_PHY_
1V8 VDDA_1P8_PHYs Required
LDO1 VDD1_DDR
_1V8 Mem: VDD1 Required Optional Required
LDO2 VDD_MCUI
O_1V8
VDDSHVx_MCU (1.8 V) Required Required
Mem: VCC
LDO3 VDA_DLL_0
V8 VDDA_0P8_PLLs/DLLs Required
LDO4 VDA_MCU_
1V8 VDDA_x Required Required
TPS659411
11-Q1
BUCK1234 VDD_CORE
_0V8
VDD_CORE,
VDDA_0P8_PHYs Required
BUCK5 VDD_RAM_
0V85
VDDAR_CPU/CORE Required
LDO1 VDD_SD_D
VVDDSHV5 Required
LDO2 VDD_USB_
3V3 VDDA_3P3_USB Required
LDO3 VDD_IO_1V
8
VDDS_MMC0 Required
Mem: VCCQ
LDO4 VDA_PLL_1
V8
VDDA_1P8_PLLs Required
TPS22965-
Q1 Load Switch VDD_MCUI O_3V3 VDDSHVx_MCU (3.3 V) Required Required
TPS22965-
Q1 Load Switch VDD_IO_3V 3
VDDSHV0-4,VDDSHV6
(3.3 V) Required Required
TLV73318P-
Q1
LDO VPP_EFUS
E_1V8
VPP_x(EFUSE) Optional
TPS62813-
Q1
BUCK VDD_DDR_
1V1
VDDS_DDR_BIAS,
VDDS_DDR_IO
Required Optional Required
Mem: VDD2
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3.2 Control Mapping
Figure 3-2 shows the digital control signal mapping between processor and PMIC devices. For the two PMIC
devices to work together, the primary PMIC and secondary PMIC must establish an SPMI communication
channel. This allows the two TPS6594-Q1 to synchronize their internal Pre-Configurable State Machines (PFSM)
so that they operate as one PFSM across all power and digital resources. The GPIO_5 and GPIO_6 pins on the
TPS6594-Q1 are assigned for this functionality. In addition, the primary PMIC LDOVINT pin is connected to the
secondary PMIC ENABLE input to correctly initiate the PFSM.
Other digital connections from the TPS6594-Q1 devices to the processor provide error monitoring, processor
reset, processor wake up, and system low-power modes. Specific GPIO pins have been assigned to key signals
in order to ensure proper operation during low power modes when only a few GPIO pins remain operational.
The digital connections shown in Figure 3-2 allow system features including MCU-only MCU Safety Island and
suspend-to-RAM low power modes, functional safety up to ASIL-D, compliant dual voltage SD card operation,
and LPDDR4x integration.
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TPS65941212-Q1
ENABLE
INTn
nRSTOUT
GPIO_1 (SCL_I2C2)
TPS65941111-Q1
PRIMARY PMIC
Processor
SoC MAIN CONTROLS
MMC1_IO
DDR_RET
RESETSTATz
SAFETY MCU CONTROLS
Safety MCU GPIO
WKUP_I2C0_SCL/SDA
MCU_PORz
Board
MCU_SAFETY_ERRORn
TPS22965-Q1
Warm Reset
ON REQUEST
SCL_I2C1
SDA_I2C1
GPIO_2 (SDA_I2C2)
GPIO_3 (GPO)
GPIO_4 (LP_WKUP1)
GPIO_5 (SCLK_SPMI)
GPIO_6 (SDATA_SPMI)
GPIO_7 (nERR_MCU)
GPIO_8 (DISABLE_WDOG)
GPIO_9 (GPI)
GPIO_10 (WKUP1)
GPIO_11 (nRSTOUT_SoC)
INTn
GPIO_1 (GPI)
SECONDARY PMIC
SCL_I2C1
SDA_I2C1
GPIO_2 (GPI)
GPIO_8 (GPI)
GPIO_9 (GPO)
GPIO_5 (SCLK_SPMI)
GPIO_6 (SDATA_SPMI)
GPIO_10 (WKUP2)
LDOVINT LDOVINT
MCU_I2C0_SCL/SDA
PMIC_POWER_EN1
PORz
PMIC Voltage Domains
VRTC ±1.8V
VINT ±1.8V
VIO ±1.8V or 3.3V
PORz_OUT
Disable Watchdog
Wakeup
PDN FEATURES
Base PDN
MCU-only
Suspend-to-RAM
Reset to Board
GPIO_11 (GPO)
TPS22965-Q1
GPIO_3 (GPO)
GPIO_4 (GPO)
GPIO_7 (GPI)
ENABLE
nRSTOUT
TPS62813-Q1
TPS62813-Q1
VCCA
Domain Descriptions
Processor Group
Processor Sub-group
Processor I/O
Power
System Group
System Sub-group
System I/O
SYS_SAFETY_ERRn
HW_WKUP_I2C0
HW_WKUP_I2C0
HW_MCU_I2C0_SCL
HW_MCU_I2C0_SDA
EN_MCU3V3IO_LDSW
H_WAKE_PMIC
H_MCU_INTn
H_MCU_PORz_1V8
LEOA_SCLK
LEOA_SDATA
PMICA_SAFETY_ERRn
PMICA_GPIO8
PMICA_GPIO10
H_SOC_PORz_1V8
SEL_SDIO_3V3_1V8n
EN_DDR_BUCK
H_DDR_RET_1V1
EN_EFUSE_LDO
EN_3V3IO_LDSW
Figure 3-2. TPS6594-Q1 Digital Connections
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Note
The PMIC voltage domain of an IO can be different depending upon configuration. When configured
as an input GPIO3 and GPIO4 are in the VRTC domain. When configured as an output, GPIO3 and
GPIO4 are in the VINT domain.
Note
In addition to the I2C signals, four additional signals are open-drain outputs and require a pullup to a
specific power rail. Please refer to Table 3-2 for a list of the signals and the specific power rail.
Table 3-2. Open-drain signals and Power Rail
PDN Signal Pullup Power Rail
H_MCU_INTn VDD_MCUIO_3V3
H_MCU_PORz_1V8 VDA_MCU_1V8
H_SOC_PORz_1V8 VDA_MCU_1V8
H_DDR_RET_1V1 VDD_DDR_1V1_REG
H_WKUP_I2C0 VDD_MCUIO_3V3
H_MCU_I2C0_SCL/SDA VDD_MCUIO_3V3
Please use Table 3-3 as a guide to understand GPIO assignments required for each PDN system feature.
If the feature listed is not required, the digital connection can be removed; however, the GPIO pin is still
configured per NVM defined default function shown. After the processor has booted up, system software can
potentially reconfigure an unused GPIO to support a new function. This is possible as long as that function is
only needed after boot and default function does not cause any conflicts with normal operations (for example,
two outputs driving same net). For details on how functional safety related connections help achieve functional
safety system-level goals, see Section 4.
Table 3-3. Digital Connections by System Feature
Device
GPIO Mapping System Features
PMIC Pin NVM
Function PDN Signals Active SoC Functional Safety
MCU - only
and MCU-
Safety
Island
Suspend-
to-RAM SD Card
TPS659412
12-Q1
nPWRON/
ENABLE Enable SOC_PWR_ON Required
INT INT H_MCU_INTn Required
nRSTOUT nRSTOUT H_MCU_PORz_1V8 Required Required
SCL_I2C1 SCL_I2C1 H_WKUP_I2C0 Required
SDA_I2C1 SDA_I2C1 H_WKUP_I2C0 Required
GPIO_1 SCL_I2C2 H_MCU_I2C0_SCL Required
GPIO_2 SDA_I2C2 H_MCU_I2C0_SDA Required
GPIO_3 GPO EN_MCU3V3IO_LDSW Required
GPIO_4 LP_WKUP1 H_WAKE_PMIC Required
GPIO_5 SCLK_SPM
ILEOA_SCLK Required
GPIO_6 SDATA_SP
MI LEOA_SDATA Required
GPIO_7 nERR_MC
UPMICA_SAFETY_ERRn Required
GPIO_8 DISABLE_
WDOG PMICA_GPIO8 (2) (2)
GPIO_9 GPI PMICA_GPIO9(3)
GPIO_10 WKUP1 PMIC_POWER_EN1 Required
GPIO_11 nRSTOUT_
SOC H_SOC_PORz_1V8 Required
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Table 3-3. Digital Connections by System Feature (continued)
Device
GPIO Mapping System Features
PMIC Pin NVM
Function PDN Signals Active SoC Functional Safety
MCU - only
and MCU-
Safety
Island
Suspend-
to-RAM SD Card
TPS659411
11-Q1
nPWRON/
ENABLE ENABLE VINT_LEOA_1V8 Required
nINT nINT H_MCU_INTn
nRSTOUT nRSTOUT Unused
SCL_I2C1 SCL_I2C1 H_WKUP_I2C0 Required
SDA_I2C1 SCL_I2C1 H_WKUP_I2C0 Required
GPIO_1 GPI Unused(3)
GPIO_2 GPI SEL_SDIO_3V3_1V8n(1) Required
GPIO_3 GPO EN_DDR_BUCK
GPIO_4 GPO H_DDR_RET_1V1 Required
GPIO_5 SCLK_SPM
ILEOA_SCLK Required
GPIO_6 SDATA_SP
MI LEOA_SDATA Required
GPIO_7 GPI Unused(3)
GPIO_8 GPI Unused(3)
GPIO_9 GPO EN_EFUSE_LDO(3)
GPIO_10 WKUP2 Unused(3)
GPIO_11 GPO EN_3V3IO_LDSW Required
(1) This pin is an input with an internal pulldown enabled. A rising edge on this GPI initiates the FSM trigger and associated sequence.
The sequence configures LDO1 to bypass mode, supplying 3.3 V. A falling edge triggers an alternate sequence which configures
LDO1 to LDO mode, supplying 1.8 V. See also Table 6-1
(2) If it is desired to disable the watchdog through hardware, GPIO_8 is required and must be set high by the time nRSTOUT goes high.
After nRSTOUT is high, the watchdog state is latched and the pin can be configured for other functions through software.
(3) This GPIO is not required for power sequencing or PMIC functionality and can be configured by software for a different purpose if
desired.
4 Supporting Functional Safety Systems
By using the dual TPS6594-Q1 solution to power the DRA829V or TDA4VM processor, the system can leverage
the following PMIC functional safety features:
• Independent Power Control of MCU and Main Rails
• Independent Monitoring and Reset for MCU and Main Rails
• Input Supply Monitoring
• Output Voltage and Current Monitoring
• Question and Answer Watchdog
• Fault Reporting Interrupts
• Enable Drive Pin that provides an independent path to disable system actuators
• Error Pin Monitoring
• Internal Diagnostics including voltage monitoring, temperature monitoring, and Built-In Self-Test
Refer to the Safety Manual of the TPS6594-Q1 device for full descriptions and analysis of the PMIC functional
safety features. These functional safety features can assist in achieving up to ASIL-D rating for a system.
Additionally, these features help in achieving the functional safety assumptions utilized by the processor to
achieve up to ASIL-D rating. See the DRA829/TDA4VM Safety Manual for Jacinto™ 7 Processors for a complete
list of functional safety system assumptions.
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