Texas Instruments TPS65941212-Q1 User manual

User’s Guide
TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide
for Jacinto™ 7 J721E, PDN-0B
ABSTRACT
This user’s guide can be used as a guide for integrating the TPS65941212-Q1 and TPS65941111-Q1 power
management integrated circuits (PMICs) into a system powering the Automotive Jacinto™ 7 DRA829 or
TDA4VM processor.
Table of Contents
1 Introduction.............................................................................................................................................................................2
2 Device Versions...................................................................................................................................................................... 2
3 Processor Connections..........................................................................................................................................................4
3.1 Power Mapping.................................................................................................................................................................. 4
3.2 Control Mapping.................................................................................................................................................................7
4 Supporting Functional Safety Systems..............................................................................................................................10
4.1 Achieving ASIL-B System Requirements......................................................................................................................... 11
4.2 Achieving up to ASIL-D System Requirements................................................................................................................11
5 Static NVM Settings..............................................................................................................................................................13
5.1 Application-Based Configuration Settings........................................................................................................................13
5.2 Device Identification Settings........................................................................................................................................... 14
5.3 BUCK Settings................................................................................................................................................................. 14
5.4 LDO Settings....................................................................................................................................................................16
5.5 VCCA Settings................................................................................................................................................................. 17
5.6 GPIO Settings.................................................................................................................................................................. 17
5.7 Finite State Machine (FSM) Settings............................................................................................................................... 20
5.8 Interrupt Settings..............................................................................................................................................................20
5.9 POWERGOOD Settings...................................................................................................................................................23
5.10 Miscellaneous Settings.................................................................................................................................................. 24
5.11 Interface Settings............................................................................................................................................................25
5.12 Multi-Device Settings..................................................................................................................................................... 26
5.13 Watchdog Settings......................................................................................................................................................... 26
6 Pre-Configurable Finite State Machine (PFSM) Settings.................................................................................................. 26
6.1 Configured States............................................................................................................................................................ 27
6.2 PFSM Triggers................................................................................................................................................................. 28
6.3 Power Sequences............................................................................................................................................................ 29
7 Impact of NVM Changes.......................................................................................................................................................49
8 References............................................................................................................................................................................ 50
9 Revision History................................................................................................................................................................... 50
Trademarks
Jacinto™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
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1 Introduction
This user’s guide describes a power distribution network (PDN), PDN-0B, between two TPS6594-Q1 devices
and either DRA829V or TDA4VM processor with independent MCU and Main power rails. This PDN enables
board level isolation of the processor MCU and Main voltage resources as required to leverage the processor
architecture in implementing two desirable end product features:
1. MCU processor acts as independent safety monitor (MCU Safety Island) over the Main processing
resources to ensure safe system operations.
2. MCU processor maintains minimum system operations (MCU Only) to significantly reduce processor power
dissipation thereby extending battery life during stand-by use cases and reducing component temperature.
This description includes the following to clarify platform system operation:
1. PDN power resource connections
2. PDN digital control connections
3. Primary and secondary PMIC default NVM contents
4. PMIC sequencing settings to support different PDN power state transitions for an advanced processor
system
PMIC and processor data manuals describe recommended operation, electrical characteristics, external
components, package details, register maps, and overall component functionality. In the event of any
inconsistency between any user's guide, application report, or other referenced material, the data sheet
specification is the definitive source.
2 Device Versions
There are different orderable part numbers (PNs) of the TPS6594-Q1 device available with unique NVM settings
to support different end product use cases and processor types. The unique NVM settings for each PMIC
device is optimized per PDN design to support different processors, processing loads, SDRAM types, system
functional safety levels, and end product features (such as low power modes, processor voltages, and memory
subsystems). The NVM settings can be identified by both NVM_ID and NVM_REV registers. Each PMIC device
is distinguished by the part number, NVM_ID, and NVM_REV values listed in Table 2-1.
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Table 2-1. Dual TPS6594-Q1 Orderable Part Numbers for Independent MCU and Main PDN System
PDN USE CASE PDN Orderable Part Number TI_NVM_ID
(TI_NVM_REV
)
Orderable Part
Number
TI_NVM_I
D
(TI_NVM
_REV)
Error
Signal
Monitor
ing
• Up to 9 A(1) on the Primary PMIC 3-phase
CPU rail
• Up to 12 A1 on the Secondary PMIC 4-
phase CORE rail
• Up to 3.4 A(1) on the SDRAM, with support
for LPDDR4
• Supports Processor 2 GHz maximum
clock with high-speed SERDES operations
• Supports 32 Gb of LPDDR4 SDRAM with
4266MTs data rate
• Supports Functional Safety up to ASIL-D
level with MCU Safety Island
• Supports MCU-only and DDR_Retention
low power modes
• Supports I/O level of 3.3 V or 1.8 V
• Supports optional end product features:
– Compliant high-speed SD Card
memory
– Compliant USB 2.0 Interface
– On-board Efuse programming of high
security processors
0B TPS65941212RWERQ1 0x12 (0x03) TPS65941111R
WERQ1
0x11
(0x03)
Combin
ed MCU
and
SOC
0C TPS65941213RWERQ1 0x13 (0x04) TPS65941111R
WERQ1
0x11
(0x03)
Dedicat
ed MCU
and
SOC
(1) TI recommends having 15% margin between the maximum expected load current and the maximum current allowed per each PMIC
output rail.
Note
PDN-0C is recommended for all new designs and designs needing the additional functional safety
coverage provided afforded by the GPIO optimizations found in PDN-0C. This document describes
PDN-0B.
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3 Processor Connections
This section details how the dual TPS6594-Q1 power resources and GPIO signals are connected to the
processor and other peripheral components in order to support the PDN use case.
3.1 Power Mapping
Figure 3-1 shows the power mapping between the dual TPS6594-Q1 PMIC power resources and processor
voltage domains required to support independent MCU and Main power rails. In this configuration, both PMICs
use a 3.3 V input voltage. For Functional Safety applications, there is a protection FET before VCCA that
connects to the OVPGDRV pin of the primary PMIC, allowing voltage monitoring of the input supply to the
PMICs.
The VCCA voltage must be the first voltage applied to the PMIC devices. VIO_IN of the PMICs must not
be supplied before VCCA. A load switch supplies VIO_IN in this PDN. This load switch also supplies the
VDDSHVx_MCU voltage domain of the processor. This allows PMIC GPIO control signals referenced to VIO_IN
to remain active during MCU Only low power mode and to be disabled during DDR Retention (aka Suspend-to-
RAM) to reduce PMIC power.
For SD card dual-voltage I/O support (3.3 V and 1.8 V), LDO1 of the TPS659411-Q1 device can be used. A
processor GPIO control signal with a logic high default value is used to set SD VIO to 3.3 V initially. During
processor power up, the boot loader SW can set GPIO signal low to select 1.8 V level as needed for high-speed
card operation per SD specification. This allows control of the LDO1 voltage without the need for the MCU
processor to establish I2C communication with the PMICs during boot from SD card operations.
This PDN uses four discrete power components with three being required and one is optional depending
upon end product features. The two TPS22965-Q1 Load Switches connect VCCA_3V3 power rail to supply
OV protected 3.3 V to processor I/O domains. Two load switches are required in order to enable isolation
between MCU and Main processor sub-sections for MCU Safety Island or MCU Only low power operations. The
TPS62813-Q1 Buck Converter supplies LPDDR4 SDRAM component with required 1.1V supply. The unused
primary PMIC FB pin, FB_B3, has been configured per NVM settings, Table 5-3, to provide voltage monitoring
for VDD_DDR_1V1 power rail if an end product OV/UV monitoring requirements include this supply. The one
optional discrete power component is TLV73318-Q1 LDO that can be used if an end product uses a high security
processor type and desires the capability to program Efuse values on-board. If this feature is not desired, then
this LDO can be omitted and processor VPP pins treated per data manual recommendations.
Note
The PMIC voltage monitor on FB_B3 must be connected to 1.1 V. The VMON_ABIST_EN=1 for both
the primary and secondary PMICs. If 1.1 V is not connected to FB_B3 when the monitor is enabled
then the self-test fails and the BIST_FAIL_INT interrupt is set and the device goes to the safe state
and main processor voltages are disabled.
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TPS65941212-Q1
BUCK4
(4A max)
BUCK5
(2A max)
LDO1
(500mA max)
LDO2
(500mA max)
LDO3
(500mA max)
LDO4
(300mA max)
PRIMARY PMIC
Processor
MAIN PROCESSOR
VDD_CORE
VDDAR_CPU/CORE
VDDS_DDR_BIAS
VDD_PHY_1V8
VDD_CPU_AVS*
MAIN ANALOG
VDDA_1P8_PHYs
VDDA_0P8_PHYs
VDDA_0P8_PLLs/DLLs
VDDA_1P8_PLLs
VDDA_3P3_USB
MAIN DIGITAL
VDDSHV0-4
VDDSHV6
VDDS_MMC0
VDD1_DDR_1V8
MCU SAFETY ISLAND
VDD_MCU
VDDAR_MCU
VDDSHVx_MCU (1.8V)
System
VPP_x (EFUSE)
VDD_MCU_0 V85
VDA_MCU_1V8
VDDSHVx_MCU (3.3V)
VDA_DLL_0V8
TPS22965-Q1
(load switch, 4A max)
VDD_MCUIO_3V3
VDD_MCUIO_1V8
LPDDR4
VDD1
VDD2
3.3V
VDD_CPU (AVS)
VCCA
OVPGDRV
VIO_IN
BUCK1 + BUCK2
+ BUCK3
(10.5A max)
VDDSHV5
TLV73318P-Q1
(LDO, 300mA max)
TPS62813-Q1
(BUCK, 3A max)
VDD_IO_3V3
VPP_EFUSE_1V 8
VDD_DDR_1V1
VDDA_x
VDDS_DDR_IO
VDDQ
Octal SPI FLASH
Hyper FLASH
EMMC
VCCQ
VCC
TPS65941111-Q1
BUCK5
(2A max)
LDO1
(500mA max)
LDO2
(500mA max)
LDO3
(500mA max)
LDO4
(300mA max)
SECONDARY PMIC
VCCA
OVPGDRV
VIO_IN
BUCK1 + BUCK2
+ BUCK3 + BUCK4
(14A max)
VDD_CORE_0V8
TPS22965-Q1
(load switch, 4A max)
VDD_RAM_0V85
UFS
VCCQ
VCC
FB_B3 (pin 49)
LDO
PDN Features
Base PDN
MCU-only
Suspend-to-RAM
BUCK
Processor
Processor Sub-group
Processor Voltage
Domains
Power Components
System Group
System Sub-group
System Rail
VDD_SD_DV**
VDD_USB_3V 3
VDD_IO_1V8
VDA_PLL_1V8
Figure 3-1. Power Connections
• * VDD_CPU_AVS, boot voltage of 0.8 V then software sets device specific AVS; 0.68 V – 0.72 V.
• ** VDD_SD_DV, 3.3 V then software changes to 1.8 V per HS-SD.
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Table 3-1 identifies which power resources are required to support different system features. If the system
feature listed is not required, the power resource connection can be removed and the processor voltage domains
need to be grouped into alternative power rails.
Table 3-1. PDN Power Mapping and System Features
Power Mapping System Features
Device Power
Resource Power Rails Processor and Memory Domains Active SoC MCU - only Suspend- to-RAM SD Card USB Interface
TPS659412
12-Q1
BUCK123 VDD_CPU_
AVS VDD_CPU Required
FB_B3 VDDS_DDR_BIAS,
VDDS_DDR_IO, LPDDR4 Required Required
BUCK4 VDD_MCU_
0V85 VDDAR_MCU, VDD_MCU Required Required
BUCK5 VDD_PHY_
1V8 VDDA_1P8_PHYs Required
LDO1 VDD1_DDR
_1V8 Mem: VDD1 Required Optional Required
LDO2 VDD_MCUI
O_1V8
VDDSHVx_MCU (1.8 V) Required Required
Mem: VCC
LDO3 VDA_DLL_0
V8 VDDA_0P8_PLLs/DLLs Required
LDO4 VDA_MCU_
1V8 VDDA_x Required Required
TPS659411
11-Q1
BUCK1234 VDD_CORE
_0V8
VDD_CORE,
VDDA_0P8_PHYs Required
BUCK5 VDD_RAM_
0V85
VDDAR_CPU/CORE Required
LDO1 VDD_SD_D
VVDDSHV5 Required
LDO2 VDD_USB_
3V3 VDDA_3P3_USB Required
LDO3 VDD_IO_1V
8
VDDS_MMC0 Required
Mem: VCCQ
LDO4 VDA_PLL_1
V8
VDDA_1P8_PLLs Required
TPS22965-
Q1 Load Switch VDD_MCUI O_3V3 VDDSHVx_MCU (3.3 V) Required Required
TPS22965-
Q1 Load Switch VDD_IO_3V 3
VDDSHV0-4,VDDSHV6
(3.3 V) Required Required
TLV73318P-
Q1
LDO VPP_EFUS
E_1V8
VPP_x(EFUSE) Optional
TPS62813-
Q1
BUCK VDD_DDR_
1V1
VDDS_DDR_BIAS,
VDDS_DDR_IO
Required Optional Required
Mem: VDD2
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3.2 Control Mapping
Figure 3-2 shows the digital control signal mapping between processor and PMIC devices. For the two PMIC
devices to work together, the primary PMIC and secondary PMIC must establish an SPMI communication
channel. This allows the two TPS6594-Q1 to synchronize their internal Pre-Configurable State Machines (PFSM)
so that they operate as one PFSM across all power and digital resources. The GPIO_5 and GPIO_6 pins on the
TPS6594-Q1 are assigned for this functionality. In addition, the primary PMIC LDOVINT pin is connected to the
secondary PMIC ENABLE input to correctly initiate the PFSM.
Other digital connections from the TPS6594-Q1 devices to the processor provide error monitoring, processor
reset, processor wake up, and system low-power modes. Specific GPIO pins have been assigned to key signals
in order to ensure proper operation during low power modes when only a few GPIO pins remain operational.
The digital connections shown in Figure 3-2 allow system features including MCU-only MCU Safety Island and
suspend-to-RAM low power modes, functional safety up to ASIL-D, compliant dual voltage SD card operation,
and LPDDR4x integration.
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TPS65941212-Q1
ENABLE
INTn
nRSTOUT
GPIO_1 (SCL_I2C2)
TPS65941111-Q1
PRIMARY PMIC
Processor
SoC MAIN CONTROLS
MMC1_IO
DDR_RET
RESETSTATz
SAFETY MCU CONTROLS
Safety MCU GPIO
WKUP_I2C0_SCL/SDA
MCU_PORz
Board
MCU_SAFETY_ERRORn
TPS22965-Q1
Warm Reset
ON REQUEST
SCL_I2C1
SDA_I2C1
GPIO_2 (SDA_I2C2)
GPIO_3 (GPO)
GPIO_4 (LP_WKUP1)
GPIO_5 (SCLK_SPMI)
GPIO_6 (SDATA_SPMI)
GPIO_7 (nERR_MCU)
GPIO_8 (DISABLE_WDOG)
GPIO_9 (GPI)
GPIO_10 (WKUP1)
GPIO_11 (nRSTOUT_SoC)
INTn
GPIO_1 (GPI)
SECONDARY PMIC
SCL_I2C1
SDA_I2C1
GPIO_2 (GPI)
GPIO_8 (GPI)
GPIO_9 (GPO)
GPIO_5 (SCLK_SPMI)
GPIO_6 (SDATA_SPMI)
GPIO_10 (WKUP2)
LDOVINT LDOVINT
MCU_I2C0_SCL/SDA
PMIC_POWER_EN1
PORz
PMIC Voltage Domains
VRTC ±1.8V
VINT ±1.8V
VIO ±1.8V or 3.3V
PORz_OUT
Disable Watchdog
Wakeup
PDN FEATURES
Base PDN
MCU-only
Suspend-to-RAM
Reset to Board
GPIO_11 (GPO)
TPS22965-Q1
GPIO_3 (GPO)
GPIO_4 (GPO)
GPIO_7 (GPI)
ENABLE
nRSTOUT
TPS62813-Q1
TPS62813-Q1
VCCA
Domain Descriptions
Processor Group
Processor Sub-group
Processor I/O
Power
System Group
System Sub-group
System I/O
SYS_SAFETY_ERRn
HW_WKUP_I2C0
HW_WKUP_I2C0
HW_MCU_I2C0_SCL
HW_MCU_I2C0_SDA
EN_MCU3V3IO_LDSW
H_WAKE_PMIC
H_MCU_INTn
H_MCU_PORz_1V8
LEOA_SCLK
LEOA_SDATA
PMICA_SAFETY_ERRn
PMICA_GPIO8
PMICA_GPIO10
H_SOC_PORz_1V8
SEL_SDIO_3V3_1V8n
EN_DDR_BUCK
H_DDR_RET_1V1
EN_EFUSE_LDO
EN_3V3IO_LDSW
Figure 3-2. TPS6594-Q1 Digital Connections
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Note
The PMIC voltage domain of an IO can be different depending upon configuration. When configured
as an input GPIO3 and GPIO4 are in the VRTC domain. When configured as an output, GPIO3 and
GPIO4 are in the VINT domain.
Note
In addition to the I2C signals, four additional signals are open-drain outputs and require a pullup to a
specific power rail. Please refer to Table 3-2 for a list of the signals and the specific power rail.
Table 3-2. Open-drain signals and Power Rail
PDN Signal Pullup Power Rail
H_MCU_INTn VDD_MCUIO_3V3
H_MCU_PORz_1V8 VDA_MCU_1V8
H_SOC_PORz_1V8 VDA_MCU_1V8
H_DDR_RET_1V1 VDD_DDR_1V1_REG
H_WKUP_I2C0 VDD_MCUIO_3V3
H_MCU_I2C0_SCL/SDA VDD_MCUIO_3V3
Please use Table 3-3 as a guide to understand GPIO assignments required for each PDN system feature.
If the feature listed is not required, the digital connection can be removed; however, the GPIO pin is still
configured per NVM defined default function shown. After the processor has booted up, system software can
potentially reconfigure an unused GPIO to support a new function. This is possible as long as that function is
only needed after boot and default function does not cause any conflicts with normal operations (for example,
two outputs driving same net). For details on how functional safety related connections help achieve functional
safety system-level goals, see Section 4.
Table 3-3. Digital Connections by System Feature
Device
GPIO Mapping System Features
PMIC Pin NVM
Function PDN Signals Active SoC Functional Safety
MCU - only
and MCU-
Safety
Island
Suspend-
to-RAM SD Card
TPS659412
12-Q1
nPWRON/
ENABLE Enable SOC_PWR_ON Required
INT INT H_MCU_INTn Required
nRSTOUT nRSTOUT H_MCU_PORz_1V8 Required Required
SCL_I2C1 SCL_I2C1 H_WKUP_I2C0 Required
SDA_I2C1 SDA_I2C1 H_WKUP_I2C0 Required
GPIO_1 SCL_I2C2 H_MCU_I2C0_SCL Required
GPIO_2 SDA_I2C2 H_MCU_I2C0_SDA Required
GPIO_3 GPO EN_MCU3V3IO_LDSW Required
GPIO_4 LP_WKUP1 H_WAKE_PMIC Required
GPIO_5 SCLK_SPM
ILEOA_SCLK Required
GPIO_6 SDATA_SP
MI LEOA_SDATA Required
GPIO_7 nERR_MC
UPMICA_SAFETY_ERRn Required
GPIO_8 DISABLE_
WDOG PMICA_GPIO8 (2) (2)
GPIO_9 GPI PMICA_GPIO9(3)
GPIO_10 WKUP1 PMIC_POWER_EN1 Required
GPIO_11 nRSTOUT_
SOC H_SOC_PORz_1V8 Required
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Table 3-3. Digital Connections by System Feature (continued)
Device
GPIO Mapping System Features
PMIC Pin NVM
Function PDN Signals Active SoC Functional Safety
MCU - only
and MCU-
Safety
Island
Suspend-
to-RAM SD Card
TPS659411
11-Q1
nPWRON/
ENABLE ENABLE VINT_LEOA_1V8 Required
nINT nINT H_MCU_INTn
nRSTOUT nRSTOUT Unused
SCL_I2C1 SCL_I2C1 H_WKUP_I2C0 Required
SDA_I2C1 SCL_I2C1 H_WKUP_I2C0 Required
GPIO_1 GPI Unused(3)
GPIO_2 GPI SEL_SDIO_3V3_1V8n(1) Required
GPIO_3 GPO EN_DDR_BUCK
GPIO_4 GPO H_DDR_RET_1V1 Required
GPIO_5 SCLK_SPM
ILEOA_SCLK Required
GPIO_6 SDATA_SP
MI LEOA_SDATA Required
GPIO_7 GPI Unused(3)
GPIO_8 GPI Unused(3)
GPIO_9 GPO EN_EFUSE_LDO(3)
GPIO_10 WKUP2 Unused(3)
GPIO_11 GPO EN_3V3IO_LDSW Required
(1) This pin is an input with an internal pulldown enabled. A rising edge on this GPI initiates the FSM trigger and associated sequence.
The sequence configures LDO1 to bypass mode, supplying 3.3 V. A falling edge triggers an alternate sequence which configures
LDO1 to LDO mode, supplying 1.8 V. See also Table 6-1
(2) If it is desired to disable the watchdog through hardware, GPIO_8 is required and must be set high by the time nRSTOUT goes high.
After nRSTOUT is high, the watchdog state is latched and the pin can be configured for other functions through software.
(3) This GPIO is not required for power sequencing or PMIC functionality and can be configured by software for a different purpose if
desired.
4 Supporting Functional Safety Systems
By using the dual TPS6594-Q1 solution to power the DRA829V or TDA4VM processor, the system can leverage
the following PMIC functional safety features:
• Independent Power Control of MCU and Main Rails
• Independent Monitoring and Reset for MCU and Main Rails
• Input Supply Monitoring
• Output Voltage and Current Monitoring
• Question and Answer Watchdog
• Fault Reporting Interrupts
• Enable Drive Pin that provides an independent path to disable system actuators
• Error Pin Monitoring
• Internal Diagnostics including voltage monitoring, temperature monitoring, and Built-In Self-Test
Refer to the Safety Manual of the TPS6594-Q1 device for full descriptions and analysis of the PMIC functional
safety features. These functional safety features can assist in achieving up to ASIL-D rating for a system.
Additionally, these features help in achieving the functional safety assumptions utilized by the processor to
achieve up to ASIL-D rating. See the DRA829/TDA4VM Safety Manual for Jacinto™ 7 Processors for a complete
list of functional safety system assumptions.
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4.1 Achieving ASIL-B System Requirements
To achieve a system functional safety level of ASIL-B, the following PDN features are available:
• PMIC over voltage and under voltage monitoring on the power resource voltage outputs
• PMIC over-voltage monitoring and protection on the input to the PMIC (VCCA)
• Watchdog monitoring of safety processor
• MCU error monitoring
• MCU reset
• I2C communication
• Error indicator for driving external circuitry (optional)
The PDN has an in-line, external power FET, as shown in Figure 3-1, between the input supply and PMICs.
The voltage before and after the FET is monitored by the PMIC, and the PMIC controls the FET through the
OVPGDRV pin. The FET can quickly isolate the PMICs when an over-voltage event greater than 6 V is detected
on the input supply to protect the system from being damaged. This includes all power rails sourced from
the FET output. Any power connected upstream from the FET is not protected from over voltage events. In
Figure 3-1 the load switches that supply power to the MCU and Main I/O domains, the discrete buck supplying
the DDR, and the discrete LDO supplying EFUSE are all connected after the FET to extend the over voltage
protection to these processor domains and discrete power resources.
The PMIC internal over voltage and under voltage monitoring and their respective monitoring threshold levels
are enabled by default and can be updated through I2C after startup. PMIC power rails connected directly to
the processor are monitored by default. Rails supplied through the load switches are not monitored directly. To
monitor the load switch output voltage that supplies the MCU I/O of the processor, it is recommended to use
the POK monitor built into the VDDSHV0_MCU voltage domain of the processor. The unused feedback pin
of BUCK3 on TPS65941212-Q1, FB_B3, is assigned to monitor the VDD_DDR_1V1 voltage supplied by the
external BUCK regulator. For monitoring the load switch voltage that supplies the Main I/O, an unused feedback
pin of the TPS65941111- Q1 (FB_B3 or FB_B4) can be configured through I2C and connected to the output of
the load switch to enable monitoring.
The internal Q&A Watchdog is enabled by default on the primary TPS6594-Q1 device. Once the device is
in ACTIVE state, the trigger or Q&A watchdog settings can be configured through the secondary I2C in the
device. The primary and secondary I2C CRC is not enabled by default but must be enabled with the I2C_2
trigger described in Table 6-1. Once enabled the secondary I2C is disabled for 2ms. It is recommended to
enable I2C CRC and wait a minimum of 2ms before starting the Q&A Watchdog. The steps for configuring and
starting the watchdog can be found in the TPS6594-Q1 datasheet. Setting the DISABLE_WDOG signal high on
primary TPS6594-Q1 GPIO_8 disables the watchdog timer if this feature needs to be suspended during initial
development or is not required in the system.
GPIO_7 of the primary TPS6594-Q1 PMIC is configured as the MCU error signal monitor, and must be enabled
though the ESM_MCU_EN register bit. MCU reset is supported through the connection between the primary
PMIC nRSTOUT pin and the MCU_PORz of the processor. Lastly, there are two I2C ports between the
TPS6594-Q1 and the processor. The first is used for all non-watchdog communication, such as voltage level
control, and the second allows the watchdog monitoring to be on an independent communication channel.
There is an option to use the primary TPS6594-Q1 EN_DRV pin to indicate an error has been detected and the
system is entering SAFE state. This signal can be utilized if the system has some additional external circuitry
that needs to be driven by an error event. In this PDN, the EN_DRV is not utilized, but still available.
4.2 Achieving up to ASIL-D System Requirements
For ASIL-C or ASIL-D systems, the following features in addition to the ones described in Section 4.1 can be
used:
• PMIC current monitoring on all output power rails
• Isolation of processor MCU and Main power domains
• SoC error monitoring
• SoC reset
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The current monitoring is enabled by default for all BUCKs and LDOs for the TPS6594-Q1 devices. Additionally,
Figure 3-1 shows that the MCU domain of the processor is powered by different power resources of the
PMICs than the main power domain of the processor. SoC error signal monitoring can be utilized if GPIO_3 of
TPS65941111-Q1 is available to be reconfigured as nERR_SoC. This feature is enabled through I2C using the
ESM_SOC_EN register bit. The SoC reset functionality is supported through the connection of GPIO_11 on the
primary TPS6594-Q1, configured as nRSTOUT_SoC, to the PORz pin of the processor.
Table 4-1. System Level Safety Features
ASIL-B ASIL-D
Safety Monitoring
Processor
External SW
Wdog
External Wdog
COMM & INTn
Safety MCU
Processing ESM
Safety MCU Reset
Safety Status
Signal
System Input
Voltage Monitoring
SoC Main
Processing ESM
SoC Main Reset
SoC: MCU Island
R5 Cores
TPS65941212-Q1:
Q&A Watchdog
TPS65941212-Q1:
I2C2
TPS65941212-Q1
and
TPS65941111-Q1:
nINT
TPS65941212-Q1:
nERR_MCU
connected to
SOC:MCU_SAFE
TY_ERRz
TPS65941212-Q1:
nRSTOUT
connected to
MCU_PORz_1V8
TPS65941212-Q1:
ENDRV
TPS65941212-Q1:
VSYS_SENSE -
OV with Safety
FET OVPGDRV
TPS65941212-Q1
and
TPS65941111-Q1
with VCCA OV
& UV and SoC
(VMON1) -UV
TSP65941212-Q1:
nERR_MCU
connected to
SOC:
SOC_SAFETY_E
RRz
TPS65941212-Q1:
nRSTOUT_SOC
connected to
SOC_PORz_1V8
Table 4-2. Monitoring Safety Features
ASIL-B ASIL-D Adds
Device Power Resource PDN Power Rail Safe State Power
Group1
Supply Voltage
Monitoring
Supply Current
Monitoring
TPS65941212-Q1
(PMIC-A)
BUCK1-3 VDD_CPU_AVS SOC PMIC-A - OV & UV PMIC-A -CM
BUCK4 VDD_MCUIO_0V8 MCU PMIC-A - OV & UV PMIC-A -CM
BUCK5 VDD_PHY_1V8 SOC PMIC-A - OV & UV PMIC-A -CM
LDO1 VDD1_LPDDR4_1V8 SOC PMIC-A - OV & UV PMIC-A -CM2
LDO2 VDD_MCUIO_1V8 MCU PMIC-A - OV & UV PMIC-A -CM
LDO3 VDA_DLL_0V8 SOC PMIC-A - OV & UV PMIC-A -CM
LDO4 VDA_MCU_1V8 MCU PMIC-A - OV & UV PMIC-A -CM
TPS65941111-Q1
(PMIC-B)
BUCK1-4 VDD_CORE_0V8 SOC PMIC-B - OV & UV PMIC-B -CM
BUCK5 VDD_RAM_0V85 SOC PMIC-B - OV & UV PMIC-B -CM
LDO1 VDD_SD_DV SOC PMIC-B - OV & UV PMIC-B -CM
LDO2 VDA_USB_3V3 SOC PMIC-B - OV & UV PMIC-B -CM
LDO3 VDD_IO_1V8 SOC PMIC-B - OV & UV PMIC-B -CM
LDO4 VDA_PLL_1V8 SOC PMIC-B - OV & UV PMIC-B -CM
TPS22965W-Q1 Ld Sw A VDD_MCUIO_3V3 MCU SoC
(VDDSHV0_MCU) -
OV & UV
NA
TPS22965W-Q1 Ld Sw B VDD_IO_3V3 SOC PMIC-B (FB_B4) - OV
& UV7
NA3 4
TPS62813-Q1 Buck A VDD_LPDDR4_1V1 None PMIC-A (FB_B3) - OV
& UV5
NA2
TLV73318P-Q1 LDO-A VDD_EFUSE_1V8 None NA6NA6
1. Rail Group settings for the TPS65941212-Q1 and TPS65941111-Q1 are found in Table 5-7.
2. Power rails VDD_DDR_1V1 and VDD1_LPDDR4_1V8 are safety critical but do not required direct voltage
or current monitoring since other means are available (for example, SoC internal timeout gaskets and ECC
checkers) provide diagnostic coverage to detect faults in the DDR voltage.
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3. Power rails VDD_IO_1V8/3V3 and VDD_GPIORET_1V8/3V3 are typically not safety critical since other
means are available (for example, black-channel checkers) to provide diagnostic coverage to detect faults in
SoC signaling interfaces (for example, CAN, UART, and SPI).
4. If an SoC GPIO control signal is used in a safety critical interface, then adding voltage and current
monitoring to specific VIO power rail may be needed per customer's end product design.
5. PMIC resource, FB_B3 is used to monitor both OV and UV of VDD_DDR_1V1. This PMIC monitor is not
associated with a Power group, but can be added to a group by software.
6. Power rail VPP_EFUSE_1V8 is not safety critical since Efuse programming does not occur during safety
critical processing.
7. PMIC-B, Buck3 and 4 have unused remote sense feedback inputs that can be assigned to provide OV and
UV voltage monitoring after SoC SW boot for 2x external power rails per desired functional safety needs.
Optional OV/UV monitoring of VDD_DDR_1V1 and VDD_IO_3V3 power rails are examples.
5 Static NVM Settings
The TPS6594-Q1 devices consist of fixed registers and configurable registers that are loaded from the NVM. For
all NVM registers, the initial NVM settings that load into the registers are provided in this section. Note: these
initial NVM settings can be changed during state transitions, such as moving from STANDBY to ACTIVE mode.
The register map, including default values of fixed registers, is located in the TPS6594-Q1 datasheet.
5.1 Application-Based Configuration Settings
In the TPS6594-Q1 datasheet, there are seven application-based configurations for each BUCK to operate
within. The following list includes the different configurations available:
• 2.2 MHz Single Phase for DDR Termination
• 4.4 MHz VOUT Less than 1.9 V, Multiphase or High COUT Single Phase
• 4.4 MHz VOUT Less than 1.9 V, Low COUT, Single Phase Only
• 4.4 MHz VOUT Greater than 1.7 V, Single Phase Only
• 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase
• 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only
• 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only
The seven configurations also have optimal output inductance values that optimize the performance of each
buck under these various conditions. Table 5-1 shows the default configurations for the BUCKs. These settings
cannot be changed after device startup.
Table 5-1. Application Use Case Settings
Device BUCK Rail Default Application Use Case Recommended Inductor Value
TPS65941212-Q1
BUCK1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH
BUCK2 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH
BUCK3 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH
BUCK4 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH
BUCK5 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH
TPS65941111-Q1
BUCK1 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH
BUCK2 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH
BUCK3 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH
BUCK4 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH
BUCK5 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase 470 nH
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5.2 Device Identification Settings
These settings are used to distinguish which device is detected in a system. These settings cannot be changed
after device startup.
Table 5-2. Device Identification NVM Settings
Register Name Field Name TPS65941212-Q1 TPS65941111-Q1
Value Description Value Description
DEV_REV DEVICE_ID 0x82 0x82
NVM_CODE_1 TI_NVM_ID 0x12 0x11
NVM_CODE_2 TI_NVM_REV 0x3 0x3
PHASE_CONFIG MP_CONFIG 0x3 3+1+1 0x0 4+1
5.3 BUCK Settings
These settings detail the default voltages, configurations, and monitoring of the BUCK rails. All these settings
can be changed though I2C after startup.
Table 5-3. BUCK NVM Settings
Register Name Field Name TPS65941212-Q1 TPS65941111-Q1
Value Description Value Description
BUCK1_CTRL BUCK1_EN 0x0 Disabled; BUCK1 regulator 0x0 Disabled; BUCK1 regulator
BUCK1_FPWM 0x0 PFM and PWM operation
(AUTO mode).
0x0 PFM and PWM operation
(AUTO mode).
BUCK1_FPWM_MP 0x0 Automatic phase adding and
shedding.
0x0 Automatic phase adding and
shedding.
BUCK1_VMON_EN 0x0 Disabled; OV, UV, SC and
ILIM comparators.
0x0 Disabled; OV, UV, SC and
ILIM comparators.
BUCK1_VSEL 0x0 BUCK1_VOUT_1 0x0 BUCK1_VOUT_1
BUCK1_PLDN 0x1 Enabled; Pull-down resistor 0x1 Enabled; Pull-down resistor
BUCK1_RV_SEL 0x1 Enabled 0x1 Enabled
BUCK1_CONF BUCK1_SLEW_RATE 0x3 5.0 mV/μs 0x3 5.0 mV/μs
BUCK1_ILIM 0x5 5.5 A 0x5 5.5 A
BUCK2_CTRL BUCK2_EN 0x0 Disabled; BUCK2 regulator 0x0 Disabled; BUCK2 regulator
BUCK2_FPWM 0x0 PFM and PWM operation
(AUTO mode).
0x0 PFM and PWM operation
(AUTO mode).
BUCK2_VMON_EN 0x0 Disabled; OV, UV, SC and
ILIM comparators.
0x0 Disabled; OV, UV, SC and
ILIM comparators.
BUCK2_VSEL 0x0 BUCK2_VOUT_1 0x0 BUCK2_VOUT_1
BUCK2_PLDN 0x1 Enabled; Pull-down resistor 0x1 Enabled; Pull-down resistor
BUCK2_RV_SEL 0x1 Enabled 0x1 Enabled
BUCK2_CONF BUCK2_SLEW_RATE 0x3 5.0 mV/μs 0x3 5.0 mV/μs
BUCK2_ILIM 0x5 5.5 A 0x5 5.5 A
BUCK3_CTRL BUCK3_EN 0x0 Disabled; BUCK3 regulator 0x0 Disabled; BUCK3 regulator
BUCK3_FPWM 0x0 PFM and PWM operation
(AUTO mode).
0x0 PFM and PWM operation
(AUTO mode).
BUCK3_FPWM_MP 0x0 Automatic phase adding and
shedding.
0x0 Automatic phase adding and
shedding.
BUCK3_VMON_EN 0x0 Disabled; OV, UV, SC and
ILIM comparators.
0x0 Disabled; OV, UV, SC and
ILIM comparators.
BUCK3_VSEL 0x0 BUCK3_VOUT_1 0x0 BUCK3_VOUT_1
BUCK3_PLDN 0x1 Enabled; Pull-down resistor 0x1 Enabled; Pull-down resistor
BUCK3_RV_SEL 0x0 Disabled 0x0 Disabled
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Table 5-3. BUCK NVM Settings (continued)
Register Name Field Name TPS65941212-Q1 TPS65941111-Q1
Value Description Value Description
BUCK3_CONF BUCK3_SLEW_RATE 0x7 0.31 mV/μs 0x2 10 mV/μs
BUCK3_ILIM 0x5 5.5 A 0x4 4.5 A
BUCK4_CTRL BUCK4_EN 0x0 Disabled; BUCK4 regulator 0x0 Disabled; BUCK4 regulator
BUCK4_FPWM 0x0 PFM and PWM operation
(AUTO mode).
0x0 PFM and PWM operation
(AUTO mode).
BUCK4_VMON_EN 0x0 Disabled; OV, UV, SC and
ILIM comparators.
0x0 Disabled; OV, UV, SC and
ILIM comparators.
BUCK4_VSEL 0x0 BUCK4_VOUT_1 0x0 BUCK4_VOUT_1
BUCK4_PLDN 0x1 Enabled; Pull-down resistor 0x1 Enabled; Pull-down resistor
BUCK4_RV_SEL 0x1 Enabled 0x0 Disabled
BUCK4_CONF BUCK4_SLEW_RATE 0x3 5.0 mV/μs 0x2 10 mV/μs
BUCK4_ILIM 0x5 5.5 A 0x4 4.5 A
BUCK5_CTRL BUCK5_EN 0x0 Disabled; BUCK5 regulator 0x0 Disabled; BUCK5 regulator
BUCK5_FPWM 0x0 PFM and PWM operation
(AUTO mode).
0x0 PFM and PWM operation
(AUTO mode).
BUCK5_VMON_EN 0x0 Disabled; OV, UV, SC and
ILIM comparators.
0x0 Disabled; OV, UV, SC and
ILIM comparators.
BUCK5_VSEL 0x0 BUCK5_VOUT_1 0x0 BUCK5_VOUT_1
BUCK5_PLDN 0x1 Enable Pull-down resistor 0x1 Enable Pull-down resistor
BUCK5_RV_SEL 0x1 Enabled 0x1 Enabled
BUCK5_CONF BUCK5_SLEW_RATE 0x3 5.0 mV/μs 0x3 5.0 mV/μs
BUCK5_ILIM 0x3 3.5 A 0x3 3.5 A
BUCK1_VOUT_1 BUCK1_VSET1 0x37 0.800 V 0x37 0.800 V
BUCK1_VOUT_2 BUCK1_VSET2 0x37 0.800 V 0x0 0.3 V
BUCK2_VOUT_1 BUCK2_VSET1 0x37 0.800 V 0x37 0.800 V
BUCK2_VOUT_2 BUCK2_VSET2 0x37 0.800 V 0x0 0.3 V
BUCK3_VOUT_1 BUCK3_VSET1 0x73 1.10 V 0x0 0.3 V
BUCK3_VOUT_2 BUCK3_VSET2 0x73 1.10 V 0x0 0.3 V
BUCK4_VOUT_1 BUCK4_VSET1 0x41 0.850 V 0x0 0.3 V
BUCK4_VOUT_2 BUCK4_VSET2 0x41 0.850 V 0x0 0.3 V
BUCK5_VOUT_1 BUCK5_VSET1 0xb2 1.80 V 0x41 0.850 V
BUCK5_VOUT_2 BUCK5_VSET2 0x0 0.3 V 0x0 0.3 V
BUCK1_PG_WINDOW BUCK1_OV_THR 0x3 +5% / +50 mV 0x3 +5% / +50 mV
BUCK1_UV_THR 0x3 -5% / -50 mV 0x3 -5% / -50 mV
BUCK2_PG_WINDOW BUCK2_OV_THR 0x3 +5% / +50 mV 0x3 +5% / +50 mV
BUCK2_UV_THR 0x3 -5% / -50 mV 0x3 -5% / -50 mV
BUCK3_PG_WINDOW BUCK3_OV_THR 0x3 +5% / +50 mV 0x0 +3% / +30mV
BUCK3_UV_THR 0x3 -5% / -50 mV 0x0 -3% / -30mV
BUCK4_PG_WINDOW BUCK4_OV_THR 0x3 +5% / +50 mV 0x0 +3% / +30mV
BUCK4_UV_THR 0x3 -5% / -50 mV 0x0 -3% / -30mV
BUCK5_PG_WINDOW BUCK5_OV_THR 0x3 +5% / +50 mV 0x3 +5% / +50 mV
BUCK5_UV_THR 0x3 -5% / -50 mV 0x3 -5% / -50 mV
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5.4 LDO Settings
These settings detail the default voltages, configurations, and monitoring of the LDO rails. All these settings can
be changed though I2C after startup. Note: only TPS65941212-Q1 device contains LDO outputs.
Table 5-4. LDO NVM Settings
Register Name Field Name TPS65941212-Q1 TPS65941111-Q1
Value Description Value Description
LDO1_CTRL LDO1_EN 0x0 Disabled; LDO1 regulator. 0x0 Disabled; LDO1 regulator.
LDO1_SLOW_
RAMP
0x0 25mV/us max ramp up slew
rate for LDO output from
0.3V to 90% of LDOn_VSET
0x0 25mV/us max ramp up slew
rate for LDO output from
0.3V to 90% of LDOn_VSET
LDO1_PLDN 0x1 125 Ohm 0x1 125 Ohm
LDO1_VMON_
EN
0x0 Disable OV and UV
comparators.
0x0 Disable OV and UV
comparators.
LDO1_RV_SEL 0x1 Enabled 0x1 Enabled
LDO2_CTRL LDO2_EN 0x0 Disabled; LDO2 regulator. 0x0 Disabled; LDO2 regulator.
LDO2_SLOW_
RAMP
0x0 25mV/us max ramp up slew
rate for LDO output from
0.3V to 90% of LDOn_VSET
0x0 25mV/us max ramp up slew
rate for LDO output from
0.3V to 90% of LDOn_VSET
LDO2_PLDN 0x1 125 Ohm 0x1 125 Ohm
LDO2_VMON_
EN
0x0 Disabled; OV and UV
comparators.
0x0 Disabled; OV and UV
comparators.
LDO2_RV_SEL 0x1 Enabled 0x1 Enabled
LDO3_CTRL LDO3_EN 0x0 Disabled; LDO3 regulator. 0x0 Disabled; LDO3 regulator.
LDO3_SLOW_
RAMP
0x0 25mV/us max ramp up slew
rate for LDO output from
0.3V to 90% of LDOn_VSET
0x0 25mV/us max ramp up slew
rate for LDO output from
0.3V to 90% of LDOn_VSET
LDO3_PLDN 0x1 125 Ohm 0x1 125 Ohm
LDO3_VMON_
EN
0x0 Disabled; OV and UV
comparators.
0x0 Disabled; OV and UV
comparators.
LDO3_RV_SEL 0x1 Enabled 0x1 Enabled
LDO4_CTRL LDO4_EN 0x0 Disabled; LDO4 regulator. 0x0 Disabled; LDO4 regulator.
LDO4_SLOW_
RAMP
0x0 25mV/us max ramp up slew
rate for LDO output from
0.3V to 90% of LDOn_VSET
0x0 25mV/us max ramp up slew
rate for LDO output from
0.3V to 90% of LDOn_VSET
LDO4_PLDN 0x1 125 Ohm 0x1 125 Ohm
LDO4_VMON_
EN
0x0 Disabled; OV and UV
comparators.
0x0 Disabled; OV and UV
comparators.
LDO4_RV_SEL 0x1 Enabled 0x1 Enabled
LDO1_VOUT LDO1_VSET 0x1c 1.80 V 0x3a 3.30 V
LDO1_BYPAS
S
0x0 Linear regulator mode. 0x1 Bypass mode.
LDO2_VOUT LDO2_VSET 0x1c 1.80 V 0x3a 3.30 V
LDO2_BYPAS
S
0x0 Linear regulator mode. 0x1 Bypass mode.
LDO3_VOUT LDO3_VSET 0x8 0.80 V 0x1c 1.80 V
LDO3_BYPAS
S
0x0 Linear regulator mode. 0x0 Linear regulator mode.
LDO4_VOUT LDO4_VSET 0x38 1.800 V 0x38 1.800 V
LDO1_PG_WI
NDOW
LDO1_OV_TH
R
0x3 +5% / +50 mV 0x3 +5% / +50 mV
LDO1_UV_TH
R
0x3 -5% / -50 mV 0x3 -5% / -50 mV
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Table 5-4. LDO NVM Settings (continued)
Register Name Field Name TPS65941212-Q1 TPS65941111-Q1
Value Description Value Description
LDO2_PG_WI
NDOW
LDO2_OV_TH
R
0x3 +5% / +50 mV 0x3 +5% / +50 mV
LDO2_UV_TH
R
0x3 -5% / -50 mV 0x3 -5% / -50 mV
LDO3_PG_WI
NDOW
LDO3_OV_TH
R
0x3 +5% / +50 mV 0x3 +5% / +50 mV
LDO3_UV_TH
R
0x3 -5% / -50 mV 0x3 -5% / -50 mV
LDO4_PG_WI
NDOW
LDO4_OV_TH
R
0x3 +5% / +50 mV 0x3 +5% / +50 mV
LDO4_UV_TH
R
0x3 -5% / -50 mV 0x3 -5% / -50 mV
5.5 VCCA Settings
These settings detail the default monitoring enabled on VCCA. All these settings can be changed though I2C
after startup.
Table 5-5. VCCA NVM Settings
Register Name Field Name TPS65941212-Q1 TPS65941111-Q1
Value Description Value Description
VCCA_VMON_CTRL VMON_DEGLITCH_SE
L
0x1 20 us 0x1 20 us
VCCA_VMON_EN 0x1 Enabled; OV and UV
comparators.
0x1 Enabled; OV and UV
comparators.
VCCA_PG_WINDOW VCCA_OV_THR 0x7 +10% 0x7 +10%
VCCA_UV_THR 0x7 -10% 0x7 -10%
VCCA_PG_SET 0x0 3.3 V 0x0 3.3 V
GENERAL_REG_1 FAST_VCCA_OVP 0x0 slow, 4us deglitch filter
enabled
0x0 slow, 4us deglitch filter
enabled
GENERAL_REG_3 LPM_EN_DISABLES_V
CCA_VMON
0x1 VCCA_VMON enabled if
VCCA_VMON_EN=1 and
LPM_EN=0
0x1 VCCA_VMON enabled if
VCCA_VMON_EN=1 and
LPM_EN=0
5.6 GPIO Settings
These settings detail the default configurations of the GPIO rails. All these settings can be changed though I2C
after startup. Note that the contents of the GPIOx_SEL field determine which other fields in the GPIOx_CONF
and GPIO_OUT_x registers are applicable. To understand which NVM fields apply to each GPIOx_SEL option,
see the Digital Signal Descriptions section in TPS6594-Q1 data sheet.
Table 5-6. GPIO NVM Settings
Register Name Field Name TPS65941212-Q1 TPS65941111-Q1
Value Description Value Description
GPIO1_CONF GPIO1_OD 0x0 Push-pull output 0x0 Push-pull output
GPIO1_DIR 0x0 Input 0x0 Input
GPIO1_SEL 0x1 SCL_I2C2/CS_SPI 0x0 GPIO1
GPIO1_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
GPIO1_PU_PD_EN 0x0 Disabled; Pull-up/pull-down
resistor.
0x0 Disabled; Pull-up/pull-down
resistor.
GPIO1_DEGLITCH_EN 0x0 No deglitch, only
synchronization.
0x0 No deglitch, only
synchronization.
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Table 5-6. GPIO NVM Settings (continued)
Register Name Field Name TPS65941212-Q1 TPS65941111-Q1
Value Description Value Description
GPIO2_CONF GPIO2_OD 0x0 Push-pull output 0x0 Push-pull output
GPIO2_DIR 0x0 Input 0x0 Input
GPIO2_SEL 0x2 SDA_I2C2/SDO_SPI 0x0 GPIO2
GPIO2_PU_SEL 0x0 Pull-down resistor selected 0x1 Pull-up resistor selected
GPIO2_PU_PD_EN 0x0 Disabled; Pull-up/pull-down
resistor.
0x1 Enabled; Pull-up/pull-down
resistor.
GPIO2_DEGLITCH_EN 0x0 No deglitch, only
synchronization.
0x1 8 us deglitch time.
GPIO3_CONF GPIO3_OD 0x0 Push-pull output 0x0 Push-pull output
GPIO3_DIR 0x1 Output 0x1 Output
GPIO3_SEL 0x0 GPIO3 0x0 GPIO3
GPIO3_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
GPIO3_PU_PD_EN 0x0 Disabled; Pull-up/pull-down
resistor.
0x0 Disabled; Pull-up/pull-down
resistor.
GPIO3_DEGLITCH_EN 0x0 No deglitch, only
synchronization.
0x0 No deglitch, only
synchronization.
GPIO4_CONF GPIO4_OD 0x0 Push-pull output 0x1 Open-drain output
GPIO4_DIR 0x0 Input 0x1 Output
GPIO4_SEL 0x6 LP_WKUP1 0x0 GPIO4
GPIO4_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
GPIO4_PU_PD_EN 0x1 Enabled; Pull-up/pull-down
resistor.
0x0 Disabled; Pull-up/pull-down
resistor.
GPIO4_DEGLITCH_EN 0x0 No deglitch, only
synchronization.
0x0 No deglitch, only
synchronization.
GPIO5_CONF GPIO5_OD 0x0 Push-pull output 0x0 Push-pull output
GPIO5_DIR 0x1 Output 0x0 Input
GPIO5_SEL 0x1 SCLK_SPMI 0x1 SCLK_SPMI
GPIO5_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
GPIO5_PU_PD_EN 0x1 Enabled; Pull-up/pull-down
resistor.
0x0 Disabled; Pull-up/pull-down
resistor.
GPIO5_DEGLITCH_EN 0x0 No deglitch, only
synchronization.
0x0 No deglitch, only
synchronization.
GPIO6_CONF GPIO6_OD 0x0 Push-pull output 0x0 Push-pull output
GPIO6_DIR 0x0 Input 0x0 Input
GPIO6_SEL 0x1 SDATA_SPMI 0x1 SDATA_SPMI
GPIO6_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
GPIO6_PU_PD_EN 0x1 Enabled; Pull-up/pull-down
resistor.
0x0 Disabled; Pull-up/pull-down
resistor.
GPIO6_DEGLITCH_EN 0x0 No deglitch, only
synchronization.
0x0 No deglitch, only
synchronization.
GPIO7_CONF GPIO7_OD 0x0 Push-pull output 0x0 Push-pull output
GPIO7_DIR 0x0 Input 0x0 Input
GPIO7_SEL 0x1 NERR_MCU 0x0 GPIO7
GPIO7_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
GPIO7_PU_PD_EN 0x1 Enabled; Pull-up/pull-down
resistor.
0x0 Disabled; Pull-up/pull-down
resistor.
GPIO7_DEGLITCH_EN 0x1 8 us deglitch time. 0x1 8 us deglitch time.
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Table 5-6. GPIO NVM Settings (continued)
Register Name Field Name TPS65941212-Q1 TPS65941111-Q1
Value Description Value Description
GPIO8_CONF GPIO8_OD 0x0 Push-pull output 0x0 Push-pull output
GPIO8_DIR 0x0 Input 0x0 Input
GPIO8_SEL 0x3 DISABLE_WDOG 0x0 GPIO8
GPIO8_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
GPIO8_PU_PD_EN 0x1 Enabled; Pull-up/pull-down
resistor.
0x0 Disabled; Pull-up/pull-down
resistor.
GPIO8_DEGLITCH_EN 0x1 8 us deglitch time. 0x0 No deglitch, only
synchronization.
GPIO9_CONF GPIO9_OD 0x0 Push-pull output 0x0 Push-pull output
GPIO9_DIR 0x0 Input 0x1 Output
GPIO9_SEL 0x0 GPIO9 0x0 GPIO9
GPIO9_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
GPIO9_PU_PD_EN 0x0 Disabled; Pull-up/pull-down
resistor.
0x0 Disabled; Pull-up/pull-down
resistor.
GPIO9_DEGLITCH_EN 0x0 No deglitch, only
synchronization.
0x0 No deglitch, only
synchronization.
GPIO10_CONF GPIO10_OD 0x0 Push-pull output 0x0 Push-pull output
GPIO10_DIR 0x0 Input 0x0 Input
GPIO10_SEL 0x6 WKUP1 0x7 WKUP2
GPIO10_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
GPIO10_PU_PD_EN 0x1 Enabled; Pull-up/pull-down
resistor.
0x1 Enabled; Pull-up/pull-down
resistor.
GPIO10_DEGLITCH_E
N
0x1 8 us deglitch time. 0x1 8 us deglitch time.
GPIO11_CONF GPIO11_OD 0x1 Open-drain output 0x0 Push-pull output
GPIO11_DIR 0x1 Output 0x1 Output
GPIO11_SEL 0x2 NRSTOUT_SOC 0x0 GPIO11
GPIO11_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
GPIO11_PU_PD_EN 0x0 Disabled; Pull-up/pull-down
resistor.
0x0 Disabled; Pull-up/pull-down
resistor.
GPIO11_DEGLITCH_E
N
0x0 No deglitch, only
synchronization.
0x0 No deglitch, only
synchronization.
NPWRON_CONF NPWRON_SEL 0x0 ENABLE 0x0 ENABLE
ENABLE_PU_SEL 0x0 Pull-down resistor selected 0x0 Pull-down resistor selected
ENABLE_PU_PD_EN 0x1 Enabled; Pull-up/pull-down
resistor.
0x1 Enabled; Pull-up/pull-down
resistor.
ENABLE_DEGLITCH_E
N
0x1 8 us deglitch time when
ENABLE, 50 ms deglitch time
when NPWRON.
0x1 8 us deglitch time when
ENABLE, 50 ms deglitch time
when NPWRON.
ENABLE_POL 0x0 Active high 0x0 Active high
NRSTOUT_OD 0x1 Open-drain output 0x1 Open-drain output
GPIO_OUT_1 GPIO1_OUT 0x0 Low 0x0 Low
GPIO2_OUT 0x0 Low 0x0 Low
GPIO3_OUT 0x0 Low 0x0 Low
GPIO4_OUT 0x0 Low 0x0 Low
GPIO5_OUT 0x0 Low 0x0 Low
GPIO6_OUT 0x0 Low 0x0 Low
GPIO7_OUT 0x0 Low 0x0 Low
GPIO8_OUT 0x0 Low 0x0 Low
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TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7
J721E, PDN-0B
19
Copyright © 2022 Texas Instruments Incorporated

Table 5-6. GPIO NVM Settings (continued)
Register Name Field Name TPS65941212-Q1 TPS65941111-Q1
Value Description Value Description
GPIO_OUT_2 GPIO9_OUT 0x0 Low 0x0 Low
GPIO10_OUT 0x0 Low 0x0 Low
GPIO11_OUT 0x0 Low 0x0 Low
5.7 Finite State Machine (FSM) Settings
These settings describe how the PMIC output rails are assigned to various system-level states. Also, the default
trigger for each system-level state is described. All these settings can be changed though I2C after startup.
Table 5-7. FSM NVM Settings
Register Name Field Name TPS65941212-Q1 TPS65941111-Q1
Value Description Value Description
RAIL_SEL_1 BUCK1_GRP_SEL 0x2 SOC rail group 0x2 SOC rail group
BUCK2_GRP_SEL 0x2 SOC rail group 0x2 SOC rail group
BUCK3_GRP_SEL 0x0 No group assigned 0x0 No group assigned
BUCK4_GRP_SEL 0x1 MCU rail group 0x0 No group assigned
RAIL_SEL_2 BUCK5_GRP_SEL 0x2 SOC rail group 0x2 SOC rail group
LDO1_GRP_SEL 0x1 MCU rail group 0x0 No group assigned
LDO2_GRP_SEL 0x1 MCU rail group 0x2 SOC rail group
LDO3_GRP_SEL 0x2 SOC rail group 0x2 SOC rail group
RAIL_SEL_3 LDO4_GRP_SEL 0x1 MCU rail group 0x2 SOC rail group
VCCA_GRP_SEL 0x1 MCU rail group 0x1 MCU rail group
FSM_TRIG_SEL_1 MCU_RAIL_TRIG 0x2 MCU power error 0x2 MCU power error
SOC_RAIL_TRIG 0x3 SOC power error 0x3 SOC power error
OTHER_RAIL_TRIG 0x1 Orderly shutdown 0x1 Orderly shutdown
SEVERE_ERR_TRIG 0x0 Immediate shutdown 0x0 Immediate shutdown
FSM_TRIG_SEL_2 MODERATE_ERR_TRI
G
0x1 Orderly shutdown 0x1 Orderly shutdown
5.8 Interrupt Settings
These settings detail the default configurations for what is monitored by nINT pin. All these settings can be
changed though I2C after startup.
Table 5-8. Interrupt NVM Settings
Register Name Field Name TPS65941212-Q1 TPS65941111-Q1
Value Description Value Description
FSM_TRIG_MASK_1 GPIO1_FSM_MASK 0x1 Masked 0x1 Masked
GPIO1_FSM_MASK_P
OL
0x0 Low; Masking sets signal
value to '0'
0x0 Low; Masking sets signal
value to '0'
GPIO2_FSM_MASK 0x1 Masked 0x0 Not masked
GPIO2_FSM_MASK_P
OL
0x0 Low; Masking sets signal
value to '0'
0x0 Low; Masking sets signal
value to '0'
GPIO3_FSM_MASK 0x1 Masked 0x1 Masked
GPIO3_FSM_MASK_P
OL
0x0 Low; Masking sets signal
value to '0'
0x0 Low; Masking sets signal
value to '0'
GPIO4_FSM_MASK 0x1 Masked 0x1 Masked
GPIO4_FSM_MASK_P
OL
0x0 Low; Masking sets signal
value to '0'
0x0 Low; Masking sets signal
value to '0'
Static NVM Settings www.ti.com
20 TPS65941212-Q1 and TPS65941111-Q1 PMIC User Guide for Jacinto™ 7
J721E, PDN-0B
SLVUC32B – JUNE 2021 – REVISED FEBRUARY 2022
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Copyright © 2022 Texas Instruments Incorporated