AMD RX881 Product guide

AMD RX881 Databook
Technical Reference Manual
Rev 1.40
P/N: 46136_rx881_ds_pub_1.40
© 2011 Advanced Micro Devices Inc

Trademarks
AMD, the AMD Arrow, ATI, the ATI logo, AMD Athlon, AMD OverDrive, AMD PowerNow!, Avivo, Cool’n’Quiet, Radeon, and combinations thereof are trademarks
of Advanced Micro Devices, Inc.
HyperTransport is a trademark of the HyperTransport Technology Consortium.
Microsoft, Windows, Windows Vista, and Windows 7 are registered trademarks of Microsoft Corporation.
PCI Express and PCIe are registered trademarks of PCI-SIG.
WinBench is a registered trademark of Ziff Davis, Inc.
Linux is a registered trademark of Linus Torvalds in the U.S. and other countries.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Disclaimer
The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with
respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time
without notice. No license, whether express, implied, arising by estoppel, or otherwise, to any intellectual property rights are granted by this publication. Except as set
forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products
including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
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property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice.
© 2011 Advanced Micro Devices, Inc. All rights reserved.

© 2011 Advanced Micro Devices, Inc. AMD RX881 Databook 1.40
Proprietary Table of Contents-1
Table of Contents
Chapter 1: Overview
1.1 Introducing the RX881........................................................................................................................................................1-1
1.2 RX881 Features...................................................................................................................................................................1-1
1.2.1 CPU HyperTransport™ Interface.........................................................................................................................1-1
1.2.2 PCI Express® Interface........................................................................................................................................1-1
1.2.3 A-Link Express II Interface..................................................................................................................................1-2
1.2.4 System Clocks ......................................................................................................................................................1-2
1.2.5 Power Management Features ...............................................................................................................................1-2
1.2.6 PC Design Guide Compliance..............................................................................................................................1-2
1.2.7 Test Capability Features.......................................................................................................................................1-2
1.2.8 Packaging .............................................................................................................................................................1-3
1.3 Software Features................................................................................................................................................................1-3
1.4 Branding Diagram...............................................................................................................................................................1-3
1.5 Conventions and Notations.................................................................................................................................................1-4
1.5.1 Pin Names.............................................................................................................................................................1-4
1.5.2 Pin Types..............................................................................................................................................................1-4
1.5.3 Numeric Representation.......................................................................................................................................1-4
1.5.4 Register Field........................................................................................................................................................1-4
1.5.5 Hyperlinks ............................................................................................................................................................1-4
1.5.6 Acronyms and Abbreviations...............................................................................................................................1-4
Chapter 2: Functional Descriptions
2.1 Host Interface......................................................................................................................................................................2-1
2.2 Clock Generation ................................................................................................................................................................2-3
Chapter 3: Pin Descriptions and Strap Options
3.1 RX881 Pin Assignment Top View......................................................................................................................................3-2
3.2 Interface Block Diagram.....................................................................................................................................................3-4
3.3 CPU HyperTransport™ Interface .......................................................................................................................................3-5
3.4 PCI Express® Interfaces.....................................................................................................................................................3-5
3.4.1 1 x 16 Lane Interface for External Graphics........................................................................................................3-5
3.4.2 A-Link Express II Interface for Southbridge........................................................................................................3-5
3.4.3 6 x 1 Lane Interface for General Purpose External Devices...............................................................................3-6
3.4.4 Miscellaneous PCI Express® Signals ..................................................................................................................3-6
3.5 Clock Interface....................................................................................................................................................................3-6
3.6 Power Management Pins....................................................................................................................................................3-7
3.7 Miscellaneous Pins..............................................................................................................................................................3-7
3.8 Power Pins...........................................................................................................................................................................3-8
3.9 Ground Pins.........................................................................................................................................................................3-9
3.10 Strapping Options .............................................................................................................................................................3-9
Chapter 4: Timing Specifications
4.1 HyperTransport™ Bus Timing ...........................................................................................................................................4-1
4.2 HyperTransport™ Reference Clock Timing Parameters....................................................................................................4-1
4.3 PCI Express® Differential Clock AC Specifications .........................................................................................................4-2
4.4 Power Rail Power-up Sequence..........................................................................................................................................4-2

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Table of Contents
Chapter 5: Electrical Characteristics and Physical Data
5.1 Electrical Characteristics.................................................................................................................................................... 5-1
5.1.1 Maximum and Minimum Ratings........................................................................................................................ 5-1
5.1.2 DC Characteristics............................................................................................................................................... 5-1
5.2 RX881 Thermal Characteristics......................................................................................................................................... 5-3
5.2.1 RX881 Thermal Limits........................................................................................................................................ 5-3
5.2.2 Thermal Diode Characteristics............................................................................................................................ 5-4
5.3 Package Information .......................................................................................................................................................... 5-5
5.3.1 Physical Dimensions............................................................................................................................................ 5-5
5.3.2 Pressure Specification.......................................................................................................................................... 5-6
5.3.3 Board Solder Reflow Process Recommendations ............................................................................................... 5-7
Chapter 6: Power Management and ACPI
6.1 ACPI Power Management Implementation ....................................................................................................................... 6-1
Chapter 7: Testability
7.1 Test Capability Features..................................................................................................................................................... 7-1
7.2 Test Interface...................................................................................................................................................................... 7-1
7.3 XOR Test............................................................................................................................................................................ 7-1
7.3.1 Description of a Generic XOR Tree.................................................................................................................... 7-1
7.3.2 Description of the RX881 XOR Tree.................................................................................................................. 7-2
7.3.3 XOR Tree Activation........................................................................................................................................... 7-2
7.3.4 XOR Tree for the RX881 .................................................................................................................................... 7-2
7.4 VOH/VOL Test.................................................................................................................................................................. 7-4
7.4.1 Description of a Generic VOH/VOL Tree........................................................................................................... 7-4
7.4.2 VOH/VOL Tree Activation................................................................................................................................. 7-5
7.4.3 VOH/VOL Pin List.............................................................................................................................................. 7-6
Appendix A: Pin Listings
A.1 RX881 Pin List Sorted by Ball Reference......................................................................................................................... 1-2
A.2 RX881 Pin List Sorted by Pin Name................................................................................................................................. 1-7
Appendix B: Revision History

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List of Figures
Figure 1-1: RX881 ASIC A11 Production Branding ..................................................................................................................... 1-3
Figure 2-1: RX881 Internal Block Diagram .................................................................................................................................. 2-1
Figure 2-2: Host Interface Block Diagram ..................................................................................................................................... 2-2
Figure 2-3: RX881 Host Bus Interface Signals .............................................................................................................................. 2-3
Figure 3-1: RX881 Pin Assignment Top View (Left) .................................................................................................................... 3-2
Figure 3-2: RX881 Pin Assignment Top View (Right) ................................................................................................................. 3-3
Figure 3-3: RX881 Interface Block Diagram ................................................................................................................................. 3-4
Figure 4-1: RX881 Power Rail Power-up Sequence ...................................................................................................................... 4-2
Figure 5-1: RX881 528-Pin FCBGA Package Outline .................................................................................................................. 5-5
Figure 5-2: RX881 Ball Arrangement (Bottom View) .................................................................................................................. 5-6
Figure 5-3: Recommended Stencil Opening Sizes for Solder Paste Pads on PCB ........................................................................ 5-7
Figure 5-4: RoHS/Lead-Free Solder (SAC305/405 Tin-Silver-Copper) Reflow Profile .............................................................. 5-8
Figure 6-1: Linked List for Capabilities ......................................................................................................................................... 6-1
Figure 7-1: Example of a Generic XOR Tree ................................................................................................................................7-2
Figure 7-2: Sample of a Generic VOH/VOL Tree ......................................................................................................................... 7-5

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List of Tables
Table 1-1: Possible Configurations for the PCIe® General Purpose Links ....................................................................................1-2
Table 1-2: Pin Type Codes ..............................................................................................................................................................1-4
Table 1-3: Acronyms and Abbreviations ........................................................................................................................................1-5
Table 3-1: CPU HyperTransport™ Interface ..................................................................................................................................3-5
Table 3-2: 1 x 16 Lane PCI Express® Interface for External Graphics ..........................................................................................3-5
Table 3-3: 1 x 4 Lane A-Link Express II Interface for Southbridge ...............................................................................................3-5
Table 3-4: 6 x 1 Lane PCI Express® Interface for General Purpose External Devices ..................................................................3-6
Table 3-5: PCI Express® Interface for Miscellaneous PCI Express® Signals ...............................................................................3-6
Table 3-6: Clock Interface ...............................................................................................................................................................3-6
Table 3-7: Power Management Pins ...............................................................................................................................................3-7
Table 3-8: Miscellaneous Pins ........................................................................................................................................................3-7
Table 3-9: Power Pins .....................................................................................................................................................................3-8
Table 3-10: Ground Pins .................................................................................................................................................................3-9
Table 3-11: Strap Definitions for the RX881 ................................................................................................................................3-10
Table 4-1: Timing Requirements for HyperTransport™ Reference Clock (100MHz) Output by the Clock Generator ................4-1
Table 4-2: PCI Express® Differential Clock (GFX_REFCLK, GPPSB_REFCLK, 100MHz) AC Characteristics ......................4-2
Table 4-3: RX881 Power Rail Power-up Sequence ........................................................................................................................4-2
Table 5-1: Maximum and Minimum Ratings ..................................................................................................................................5-1
Table 5-2: DC Characteristics for 3.3V TTL Signals .....................................................................................................................5-1
Table 5-3: DC Characteristics for POWERGOOD .........................................................................................................................5-2
Table 5-4: DC Characteristics for HyperTransport™ and PCI-E Differential Clock (HT_REFCLK, GFX_REFCLK,
GPPSB_REFCLK, 100MHz) ..........................................................................................................................................................5-2
Table 5-5: RX881 Thermal Limits ..................................................................................................................................................5-3
Table 5-6: RX881 528-Pin FCBGA Package Physical Dimensions ...............................................................................................5-5
Table 5-7: Recommended Board Solder Reflow Profile - RoHS/Lead-Free Solder ......................................................................5-8
Table 6-1: ACPI States Supported by the RX881 ...........................................................................................................................6-1
Table 6-2: ACPI Signal Definitions ................................................................................................................................................6-1
Table 7-1: Pins on the Test Interface .............................................................................................................................................7-1
Table 7-2: Example of an XOR Tree ..............................................................................................................................................7-2
Table 7-3: RX881 XOR Tree ..........................................................................................................................................................7-3
Table 7-4: Truth Table for the VOH/VOL Tree Outputs ................................................................................................................7-5
Table 7-5: RX881 VOH/VOL Tree ................................................................................................................................................7-7

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Chapter 1
Overview
1.1 Introducing the RX881
The RX881 is the latest system logic from AMD that supports AMD S1g3-socket CPUs, such as the Caspian-series
processors.
The RX881 is pin-compatible with AMD’s other mainstream 700 and 800-series products including the RS880, RS880M,
RS780, RS780D, RS780M, RX780, RD780, and RX781, allowing a single design to target multiple market segments.
Robust and Flexible Core Logic Features
The RX881 supports a high speed HyperTransport™ interface to the AMD processor, running at a data rate of up to 4.4
GT/s and supporting both HT 1.0 and HT 3.0 protocols. The RX881 is ideally suited for 64-bit operating systems, and
supports platform configurations with greater than 4GB of system memory. The rich PCI Express®(PCIe®) expansion
capabilities of RX881 include support for PCI Express graphics and up to six other PCI Express peripherals, all
supporting the PCI Express 2.0 standard with data rates of up to 5.0GT/s. These capabilities are complemented by the
advanced I/O features of AMD’s SB700 and SB800-series Southbridges.
Low Power Consumption and Industry Leading Power Management
The RX881 is manufactured using the power efficient nm technology, and it supports a whole range of industry
standards and power management features. It provides comprehensive support for the ACPI specification and AMD
power management features such as AMD PowerNow!™.
1.2 RX881 Features
1.2.1 CPU HyperTransport™Interface
•Supports 16-bit up/down HyperTransport (HT) 3.0 interface up to 4.4 GT/s.
•Supports 200, 400, 600, 800, and 1000 MHz HT1 frequencies.
•Supports 1.6, 1.8, 2.0, and 2.2 GHz HT3 frequencies.
•Supports AMD’s S1g3-socket CPUs, including the Caspian-series processors.
•Supports LDTSTOP interface and CPU link stutter mode.
1.2.2 PCI Express®Interface
•Supports PCIe Gen2 (version 2.0).
•Optimized peer-to-peer and general purpose link performance.
•Highly flexible PCI Express implementation to suit a variety of platform needs.
•Supports a x16 graphics interface.
•Supports programmable lane reversal for the graphics link to ease motherboard layout when the end device does not
support lane reversal.
•Supports six general purpose lanes, for up to six devices on specific ports. Possible configurations are listed in
Table 1-1.

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RX881 Features
•Supports x1, x2, x4, x8, x12 and x16 polarity inversion.
1.2.3 A-Link Express II Interface
•One x4 A-Link Express II interface for connection to an AMD Southbridge. The A-Link Express II is a proprietary
interface developed by AMD basing on the PCI Express technology, with additional Northbridge-Southbridge
messaging functionalities.
•Supports programmable lane reversal to ease motherboard layout.
1.2.4 System Clocks
•Support for an external clock chip to generate PCIe and A-Link Express II clocks. Alternatively, internal generation
for these clocks, with clock input from an SB800-series Southbridge, can be used (subject to characterization with
actual RX881 and SB800-series devices).
1.2.5 Power Management Features
•Single chip solution in 55nm, 1.1V CMOS technology.
•Full ACPI 2.0 and IAPC (Instantly Available PC) power management support.
•The Chip Power Management Support logic supports four device power states defined for the OnNow Architecture—
On, Standby, Suspend, and Off. Each power state can be achieved by software control bits.
•Hardware controlled intelligent clock gating enables clocks only to active functional blocks, and is completely
transparent to software.
•Support for Cool'n'Quiet™ via FID/VID change.
•Support for AMD PowerNow!™.
•Clocks to every major functional block are controlled by a unique dynamic clock switching technique that is
completely transparent to the software. By turning off the clock to the block that is idle or not used at that point, the
power consumption can be significantly reduced during normal operation.
•Supports dynamic lane reduction for the PCIe graphics interface when coupled with an AMD-based graphics device,
adjusting lane width according to required bandwidth.
1.2.6 PC Design Guide Compliance
The RX881 complies with all relevant Windows Logo Program (WLP) requirements from Microsoft for WHQL
certification.
1.2.7 Test Capability Features
The RX881 has a variety of test modes and capabilities that provide a very high fault coverage and low DPM (Defect Per
Million) ratio:
•Full scan implementation on the digital core logic through ATPG (Automatic Test Pattern Generation Vectors).
•Dedicated test logic for the on-chip custom memory macros to provide complete coverage on these modules.
Table 1-1 Possible Configurations for the PCIe®General Purpose Links
Config. B Config. C Config. C2 Config. E Config. K Config. L
GPP1 x4 x4 x2 x2 x2 x1
GPP2-----x1
GPP3 - - x2 x1 x2 x1
GPP4---x1-x1
GPP5 x2 x1 x2 x1 x1 x1
GPP6 - x1 - x1 x1 x1

Software Features
© 2011 Advanced Micro Devices, Inc. 46136 AMD RX881 Databook 1.40
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•A JTAG test mode to allow board level testing of neighboring devices.
•An EXOR tree test mode on all the digital I/O's to allow for proper soldering verification at the board level.
•A VOH/VOL test mode on all digital I/O’s to allow for proper verification of output high and output low values at the
board level.
•Access to the analog modules to allow full evaluation and characterization.
•IDDQ mode support to allow chip evaluation through current leakage measurements.
These test modes can be accessed through the settings on the instruction register of the JTAG circuitry.
1.2.8 Packaging
•Single chip solution in 55nm, 1.1V low power CMOS technology.
•528-FCBGA package, 21mmx21mm.
1.3 Software Features
•Supports Microsoft Windows XP, Windows Vista, and Windows 7.
•Supports corporate manageability requirements such as DMI.
•ACPI support.
•Full Write Combining support for maximum performance of the CPU.
•Comprehensive OS and API support.
•Hot-key support (Windows ACPI 2.0 or AMD Event Handler Utility where appropriate).
•Extensive power management support.
•Supports AMD OverDrive™ utility.
***Warning*** AMD and ATI processors are intendedto be operated only within their associated specifications and factory settings. Operating the AMD or ATI processor outside of specification or in
excess of factory settings, including but not limited to overclocking, may damage the processor and/or lead to other problems, including but not limited to, damage to the system components (including the
motherboard and components thereon (e.g. memory)), system instabilities (e.g. data loss and corrupted images), shortened processor, system component and/or system life and in extreme cases, total
system failure. AMD does not provide support or service for issues or damages related to use of an AMD or ATI processor outside of processor specifications or in excess of factory settings.
1.4 Branding Diagram
Note: The branding can be in laser, ink, or mixed laser-and-ink marking.
Figure 1-1 RX881 ASIC A11 Production Branding
RADEON IGP
YYWW
MADE IN ZZZZ
WXXXXX.XX
215-0752007
•
* YY - Assembly Start Year
WW - Assembly Start Week
Part Number
Date Code*
AMD Product Type
AMD Logo
Wafer Lot Number
Country of Origin
Note: Branding can be in laser, ink, or
mixed laser-and-ink marking.
Pin A1 Position

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Conventions and Notations
1.5 Conventions and Notations
The following conventions are used throughout this manual.
1.5.1 Pin Names
Pins are identified by their pin names or ball references. Multiplexed pins sometimes assume alternate “functional names”
when they perform their alternate functions, and these “functional names” are given in Chapter 3, “Pin Descriptions and
Strap Options.”
All active-low signals are identified by the suffix ‘#’ in their names (e.g., MEM_RAS#).
1.5.2 Pin Types
The pins are assigned different codes according to their operational characteristics. These codes are listed in Table 1-2.
1.5.3 Numeric Representation
Hexadecimal numbers are appended with “h” (Intel assembly-style notation) whenever there is a risk of ambiguity. Other
numbers are in decimal.
Pins of identical functions but different running integers (e.g., “GFX_TX7P, GFX_TX6P,... GFX_TX0P”) are referred to
collectively by specifying their integers in square brackets and with colons (i.e., “GFX_TX[7:0]P”). A similar short-hand
notation is used to indicate bit occupation in a register. For example, NB_COMMAND[15:10] refers to the bit positions
10 through 15 of the NB_COMMAND register.
1.5.4 Register Field
A field of a register is referred to by the format of [Register Name].[Register.Field]. For example,
“NB_MC_CNTL.DISABLE_BYPASS” is the “DISABLE_BYPASS” field of the register “NB_MC_CNTL.”
1.5.5 Hyperlinks
Phrases or sentences in blue italic font are hyperlinks to other parts of the manual. Users of the PDF version of this manual
can click on the links to go directly to the referenced sections, tables, or figures.
1.5.6 Acronyms and Abbreviations
The following is a list of the acronyms and abbreviations used in this manual.
Table 1-2 Pin Type Codes
Code Pin Type
I Digital Input
O Digital Output
OD Open Drain
I/O Bi-Directional Digital Input or Output
I/OD Digital Input or Open Drain
M Multifunctional
Pwr Power
Gnd Ground
A-O Analog Output
A-I Analog Input
A-I/O Analog Bi-Directional Input/Output
A-Pwr Analog Power
A-Gnd Analog Ground
Other Pin types not included in any of the categories above

Conventions and Notations
© 2011 Advanced Micro Devices, Inc. 46136 AMD RX881 Databook 1.40
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Table 1-3 Acronyms and Abbreviations
Acronym Full Expression
ACPI Advanced Configuration and Power Interface
A-Link-E A-Link Express interface between the IGP and the Southbridge.
BGA Ball Grid Array
BIOS Basic Input Output System. Initialization code stored in a ROM or Flash RAM used to start up a
system or expansion card.
BIST Built In Self Test.
CSP Chip Scale Package
DBI Dynamic Bus Inversion
DFP Digital Flat Panel. Monitor connection standard from VESA.
DPM Defects per Million
EPROM Erasable Programmable Read Only Memory
FIFO First In, First Out
GND Ground
GPIO General Purpose Input/Output
IDDQ Direct Drain Quiescent Current
JTAG Joint Test Access Group. An IEEE standard.
MB Mega Byte
PCI Peripheral Component Interface
PCIe PCI Express
PLL Phase Locked Loop
POST Power On Self Test
PD Pull-down Resistor
PU Pull-up Resistor
SDRAM Synchronous Dynamic RAM
VRM Voltage Regulation Module

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Chapter 2
Functional Descriptions
This chapter describes the functional operation of the major interfaces of the RX881 system logic. Figure 2-1, “RX881
Internal Block Diagram,” illustrates the RX881 internal blocks and interfaces.
Figure 2-1 RX881 Internal Block Diagram
2.1 Host Interface
The RX881 is optimized to interface with AMD processors through the HyperTransportTM interface. This section presents
an overview of the HyperTransportinterface. For a detailed description of the interface, please refer to the
HyperTransport I/O Link Specification from the HyperTransport Consortium. Figure 2-2, “Host Interface Block
Diagram,” illustrates the basic blocks of the host bus interface of the RX881.
CPU
Interface
Register Interface
Root
IO Controller
AMD CPU
Graphics
Controller Complex
A-Link-E II PCIe® Interface GPP Interface
PCIe®
Expansion
Slots or
On-board
Devices
Gfx Interface
(6 x 1 Lanes)
(1 x 4 Lanes) (1 x 16 Lanes)
Southbridge
HyperTransport™
Unit

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Host Interface
Figure 2-2 Host Interface Block Diagram
The HyperTransport (HT) Interface, formerly known as the LDT (Lightning Data Transport) interface, is a high speed,
packet-based link implemented on two unidirectional buses. It is a point-to-point interface where data can flow both
upstream and downstream at the same time. The commands, addresses, and data travel in packets on the HyperTransport
link. Lengths of packets are in multiples of four bytes. The HT link consists of three parts: the physical layer (PHY), the
data link layer, and the protocol/transaction layer. The PHY is the physical interface between the RX881 and the CPU.
The data link layer includes the initialization and configuration sequences, periodic redundancy checks,
connect/disconnect sequences, and information packet flow controls. The protocol layer is responsible for maintaining
strict ordering rules defined by the HT protocol.
The RX881 HyperTransport bus interface consists of eighteen unidirectional differential data/control pairs and two
differential clock pairs in each of the upstream and downstream direction. On power up, the HT link is 8-bit wide and runs
at a default speed of 400MT/s. After negotiation, carried out by the HW and SW together, the link width can be brought
up to 16-bit and the interface can run up to 4.4GT/s. The interface is illustrated in Figure 2-3, “RX881 Host Bus Interface
Signals.” The signal name and direction for each signal is shown with respect to the processor. Note that the signal names
may be different from those used in the pin listing of the RX881. Detailed descriptions of the signals are given in section
3.3, “CPU HyperTransport™ Interface‚’ on page 3-5.
HT Interface to CPU (PHY)
Configuration
Registers
Root Complex
LTA LRA
SCH
Data Link Layer
Protocol/Transaction Layer

Clock Generation
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Figure 2-3 RX881 Host Bus Interface Signals
2.2 Clock Generation
The RX881 provides support for an external clock chip to generate PCIe and A-Link Express II clocks.
HT_RXCADN
2
2
RX881
CPU
HT_RXCADP
HT_RXCTLN
HT_RXCTLP
HT_RXCLKN
HT_RXCLKP
16
16
HT_TXCADN
2
2
HT_TXCADP
HT_TXCTLN
HT_TXCTLP
HT_TXCLKN
HT_TXCLKP
16
16
2
2
2
2
HT_TXCALP
HT_RXCALN
HT_RXCALP
HT_TXCALN

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Clock Generation
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Chapter 3
Pin Descriptions and Strap Options
This chapter gives the pin descriptions and the strap options for the RX881. To jump to a topic of interest, use the
following list of hyperlinked cross references:
“RX881 Pin Assignment Top View” on page 3-2
“Interface Block Diagram” on page 3-4
“CPU HyperTransport™ Interface” on page 3-5
“PCI Express® Interfaces” on page 3-5:
“1 x 16 Lane Interface for External Graphics” on page 3-5
“A-Link Express II Interface for Southbridge” on page 3-5
“6 x 1 Lane Interface for General Purpose External Devices” on page 3-6
“Miscellaneous PCI Express® Signals” on page 3-6
“Clock Interface” on page 3-6
“Power Management Pins” on page 3-7
“Miscellaneous Pins” on page 3-7
“Power Pins” on page 3-8
“Ground Pins” on page 3-9
“Strapping Options” on page 3-9

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RX881 Pin Assignment Top View
3.1 RX881 Pin Assignment Top View
The figures below only represent the relative ball positions. For the actual physical layout of the balls, please refer to
Figure 5-2, “RX881 Ball Arrangement (Bottom View),” on page 5- 6.
Figure 3-1 RX881 Pin Assignment Top View (Left)
12345678910111213
AVSSAPCIE GFX_RX1P GFX_TX1P GFX_TX0P VDDPCIE NC NC NC POWERGOOD DAC_HSYNC PLLVDD VDDLTP18
BVSSAPCIE GFX_TX2N GFX_RX1N GFX_TX1N GFX_TX0N VDDPCIE NC NC NC STRP_DATA DAC_VSYNC PLLVSS VSSLTP18
CGFX_RX2N GFX_RX2P GFX_TX2P GFX_RX0N VDDPCIE NC LDTSTOP# ALLOW_LDTSTO
P
DGFX_TX3P GFX_TX3N VSSAPCIE GFX_RX0P VSSAPCIE VDDPCIE VDDA18PCIEP
LL SYSRESET# NC NC VSS SUS_STAT# TESTMODE
EGFX_TX4N GFX_TX4P VSSAPCIE GFX_RX3P VDDPCIE VDDA18PCIEP
LL NC GPIO3 REFCLK_P AVDD
FGFX_TX6P GFX_TX6N GFX_TX5N GFX_TX5P GFX_RX3N VDDPCIE GPIO2 NC VDD18 REFCLK_N AVDD
GVSSAPCIE VSSAPCIE VSSAPCIE GFX_RX4P GFX_RX4N VDDPCIE VSS VDD18 RESERVED GPIO4
HGFX_TX8P GFX_TX8N GFX_TX7N GFX_TX7P GFX_RX5P GFX_RX5N VSSAPCIE VDDPCIE VDDA18PCIE VDD33 VDD33
JGFX_TX9N GFX_TX9P VSSAPCIE GFX_RX6N GFX_RX6P GFX_RX7P GFX_RX7N VDDPCIE VDDA18PCIE VDDC VSS
KGFX_TX11P GFX_TX11N GFX_TX10N GFX_TX10P VDDPCIE VDDA18PCIE VSS VDDC
LVSSAPCIE VSSAPCIE VSSAPCIE GFX_RX8P GFX_RX8N VSSAPCIE GFX_RX9N VDDPCIE VDDA18PCIE VDDC VSS
MGFX_TX13P GFX_TX13N GFX_TX12N GFX_TX12P GFX_RX11N VSSAPCIE GFX_RX10N GFX_RX9P VDDPCIE VDDA18PCIE VSS VDDC VDDC
NGFX_TX14N GFX_TX14P VSSAPCIE VDDC VSS
PGFX_TX15P GFX_TX15N GFX_RX14N GFX_RX14P GFX_RX11P VSSAPCIE GFX_RX10P GFX_RX12N VDDPCIE VDDA18PCIE VDDC VSS VDDC
RVSSAPCIE VSSAPCIE VSSAPCIE GFX_RX13N GFX_RX13P VSSAPCIE GFX_RX12P VDDPCIE VDDA18PCIE VSS VDDC
TGFX_REFCLK
NGFX_REFCLK PGFX_RX15N GFX_RX15P VDDPCIE VDDA18PCIE VDDC VSS
UGPP_REFCLK
PGPP_REFCLK NVSSAPCIE GPP_RX4P GPP_RX4N GPP_RX5N GPP_RX5P VDDPCIE VDDA18PCIE VSS VDDC
VGPP_TX5P GPP_TX5N GPPSB_REFC
LKN GPPSB_REFC LKP GPP_RX3P VSSAPCIE VSSAPCIE VSSAPCIE VDDPCIE NC VSS
WVSSAPCIE VSSAPCIE VSSAPCIE SB_RX3P GPP_RX3N VSSAPCIE VSSAPCIE VDDA18PCIE VSS NC
YGPP_TX3P GPP_TX3N GPP_TX4N GPP_TX4P SB_RX3N VSSAPCIE SB_RX1N SB_RX0N VDDA18PCIE VDD_MEM NC
AA GPP_TX2N GPP_TX2P VSSAPCIE SB_RX2P SB_RX2N SB_RX1P SB_RX0P VDDA18PCIE VDD_MEM NC
AB VSSAPCIE VSSAPCIE GPP_TX1N GPP_TX1P VSSAPCIE SB_TX2P VSSAPCIE PCE_CALRN VDDA18PCIE VDD_MEM VSS NC NC
AC GPP_TX0P GPP_TX0N VSSAPCIE VSSAPCIE SB_TX2N PCE_CALRP VDD_MEM VSS
AD GPP_RX2P GPP_RX2N GPP_RX1N GPP_RX0N SB_TX3P SB_TX1N SB_TX0P THERMALDIO
DE_N VDDA18PCIE VDD_MEM VDD18_MEM NC NC
AE VSSAPCIE GPP_RX1P GPP_RX0P VSSAPCIE SB_TX3N SB_TX1P SB_TX0N THERMALDIO
DE_P VDDA18PCIE VDD_MEM VDD18_MEM NC NC
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CPU Interface
A-Link Express II Interface
Clock Interface
External graphics Interface
General Purpose External Device Interface
Power Management Interface
Powers
Grounds
Others