AMD K5 Product manual

AMD-K5 Processor
Technical Reference Manual
TM

© 1996 Advanced Micro Devices, Inc. All rights reserved.
Advanced Micro Devices reserves the right to make changes in its products
without notice in order to improve design or performance characteristics.
This publication neither states nor implies any representations or warranties
of any kind, including but not limited to any implied warranty of merchant-
ability or fitness for a particular purpose.
AMD makes no representations or warranties with respect to the accuracy or
completeness of the contents of this publication or the information contained
herein, and reserves the right to make changes at any time, without notice.
AMD disclaims responsibility for any consequences resulting from the use of
the information included herein.
Trademarks:
AMD, the AMD logo and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Am386 and Am486 are registered trademarks, and AMD-K5 and K86 are trademarks of Advanced Micro Devices, Inc.
Microsoft and Windows are registered trademarks and Windows NT is a trademark of Microsoft.
Other product names used in this publication are for identification purposes only and may be trademarks of their
respective companies.

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Contents
1 Overview 1-1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
2 Internal Architecture 2-1
2.1 Prefetch and Predecode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2 Execution Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.1 Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.2.2 Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.3 Execute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Integer/Shift Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Floating-Point Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Load/Store Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Branch Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.2.4 Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.2.5 Retire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.3 Cache Organization and Management . . . . . . . . . . . . . . . . . . . 2-13
2.3.1 Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.2 Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.3.3 Cache Tags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.3.4 Cache-Line Fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.3.5 Cache Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.6 Snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Inquire Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Internal Snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.3.7 Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Line-Fill Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Prefetch Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
Store Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
Replacement and Invalidation Writeback Buffer . . . . . . . . 2-25
Snoop Writeback Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.4 Memory Management Unit (MMU) . . . . . . . . . . . . . . . . . . . . . 2-26
2.4.1 Storage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.4.2 Read/Write Reordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.4.3 Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.4.4 Paging and the TLBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28

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3 Software Environment and Extensions 3-1
3.1 Control Register 4 (CR4) Extensions . . . . . . . . . . . . . . . . . . . . . 3-2
3.1.1 Machine-Check Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.1.2 4-Mbyte Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.1.3 Global Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.1.4 Virtual-8086 Mode Extensions (VME) . . . . . . . . . . . . . . . . . 3-12
Interrupt Redirection in Virtual-8086 Mode
Without VME Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Hardware Interrupts and the VIF and VIP Extensions . . . . 3-13
Software Interrupts and the Interrupt Redirection
Bitmap (IRB) Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.1.5 Protected Virtual Interrupt (PVI) Extensions . . . . . . . . . . . 3-24
3.2 Model-Specific Registers (MSRs) . . . . . . . . . . . . . . . . . . . . . . . 3-25
3.2.1 Machine-Check Address Register (MCAR) . . . . . . . . . . . . . 3-25
3.2.2 Machine-Check Type Register (MCTR) . . . . . . . . . . . . . . . . 3-26
3.2.3 Time Stamp Counter (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3.2.4 Array Access Register (AAR) . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3.2.5 Hardware Configuration Register (HWCR) . . . . . . . . . . . . . 3-28
3.3 New Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
3.3.1 CPUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
3.3.2 CMPXCHG8B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
3.3.3 MOV to and from CR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
3.3.4 RDTSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
3.3.5 RDMSR and WRMSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
3.3.6 RSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
3.3.7 Illegal Instruction (Reserved Opcode) . . . . . . . . . . . . . . . . . 3-36
4 Performance 4-1
4.1 Code Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.1 General Superscalar Techniques . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.2 Techniques Specific to the AMD-K5 Processor . . . . . . . . . . . 4-3
4.2 Dispatch and Execution Timing . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.2.1 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.2.2 Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.2.3 Integer Dot Product Example . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4.2.4 Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19

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5 Bus Interface 5-1
5.1 Signal Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.1 Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.1.2 Conditions for Driving and Sampling Signals . . . . . . . . . . . . 5-7
5.1.3 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.1.4 Bus Signal Compatibility with Pentium Processor . . . . . . . 5-17
5.2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
5.2.1 A20M (Address Bit 20 Mask) . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.2.2 A31–A3 (Address Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
5.2.3 ADS (Address Strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
5.2.4 ADSC (Address Strobe Copy) . . . . . . . . . . . . . . . . . . . . . . . . 5-27
5.2.5 AHOLD (Address Hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
5.2.6 AP (Address Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
5.2.7 APCHK (Address Parity Check) . . . . . . . . . . . . . . . . . . . . . . 5-32
5.2.8 BE7–BE0 (Byte Enables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
5.2.9 BF (Bus Frequency)—(BF1–BF0 for Model 1) . . . . . . . . . . . 5-36
5.2.10 BOFF (Backoff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
5.2.11 BRDY (Burst Ready) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41
5.2.12 BRDYC (Burst Ready) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44
5.2.13 BREQ (Bus Request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
5.2.14 BUSCHK (Bus Check) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46
5.2.15 CACHE (Cacheable Access) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49
5.2.16 CLK (Bus Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52
5.2.17 D/C (Data or Code) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53
5.2.18 D63–D0 (Data Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55
5.2.19 DP7–DP0 (Data Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57
5.2.20 EADS (External Address Strobe) . . . . . . . . . . . . . . . . . . . . . 5-58
5.2.21 EWBE (External Write Buffer Empty) . . . . . . . . . . . . . . . . . 5-62
5.2.22 FERR (Floating-Point Error) . . . . . . . . . . . . . . . . . . . . . . . . . 5-64
5.2.23 FLUSH (Cache Flush) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65
5.2.24 FRCMC (Functional-Redundancy Check Master/Checker) 5-68
5.2.25 HIT (Inquire-Cycle Hit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70
5.2.26 HITM (Inquire Cycle Hit To Modified Line) . . . . . . . . . . . . 5-72
5.2.27 HLDA (Bus-Hold Acknowledge) . . . . . . . . . . . . . . . . . . . . . . 5-74
5.2.28 HOLD (Bus-Hold Request) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-76
5.2.29 IERR (Internal Error) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78
5.2.30 IGNNE (Ignore Numeric Error) . . . . . . . . . . . . . . . . . . . . . . . 5-79
5.2.31 INIT (Initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-81
5.2.32 INTR (Maskable Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-84
5.2.33 INV (Invalidate Cache Line) . . . . . . . . . . . . . . . . . . . . . . . . . 5-88
5.2.34 KEN (External Cache Enable) . . . . . . . . . . . . . . . . . . . . . . . . 5-89
5.2.35 LOCK (Bus Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91
5.2.36 M/IO (Memory or I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-95
5.2.37 NA (Next Address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-96
5.2.38 NMI (Non-Maskable Interrupt) . . . . . . . . . . . . . . . . . . . . . . . 5-97
5.2.39 PCD (Page Cache Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-99

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5.2.40 PCHK (Parity Status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-101
5.2.41 PEN (Parity Enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-102
5.2.42 PRDY (Probe Ready) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-103
5.2.43 PWT (Page Writethrough) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-105
5.2.44 R/S (Run or Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-107
5.2.45 RESET (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-109
5.2.46 SCYC (Split Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-114
5.2.47 SMI (System Management Interrupt) . . . . . . . . . . . . . . . . . 5-116
5.2.48 SMIACT (System Management Interrupt Active) . . . . . . . 5-121
5.2.49 STPCLK (Stop Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-122
5.2.50 TCK (Test Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-127
5.2.51 TDI (Test Data Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-128
5.2.52 TDO (Test Data Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-129
5.2.53 TMS (Test Mode Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-130
5.2.54 TRST (Test Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-131
5.2.55 W/R (Write or Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-132
5.2.56 WB/WT (Writeback or Writethrough) . . . . . . . . . . . . . . . . . 5-133
5.3 Bus Cycle Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-136
5.3.1 Cycle Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-136
5.3.2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-137
5.3.3 Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-137
5.3.4 Bus Speed and Typical DRAM Timing . . . . . . . . . . . . . . . . 5-139
5.3.5 Bus-Cycle Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-139
5.4 Bus Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-140
5.4.1 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-140
5.4.2 Single-Transfer Reads and Writes . . . . . . . . . . . . . . . . . . . . 5-141
Single-Transfer Memory Read and Write . . . . . . . . . . . . . . 5-141
Single-Transfer Memory Write Delayed by EWBE Signal 5-144
I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-146
Single-Transfer Misaligned Memory and I/O Transfers . . 5-147
5.4.3 Burst Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-149
Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-149
Burst Writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-153
5.4.4 Bus Arbitration and Inquire Cycles . . . . . . . . . . . . . . . . . . . 5-156
AHOLD-Initiated Inquire Miss . . . . . . . . . . . . . . . . . . . . . . 5-157
AHOLD-Initiated Inquire Hit to Shared or
Exclusive Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-159
AHOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . 5-160
Bus Backoff (BOFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-162
BOFF-Initiated Inquire Hit to Modified Line . . . . . . . . . . . 5-164
HOLD-Initiated Inquire Hit to Shared or Exclusive Line . 5-166
HOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . 5-168

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5.4.5 Locked Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-169
Basic Locked Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-169
TLB Miss (4-Kbyte Page) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-171
Locked Operation with BOFF Intervention . . . . . . . . . . . . 5-173
Interrupt Acknowledge Operation . . . . . . . . . . . . . . . . . . . 5-175
5.4.6 Special Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-180
Basic Special Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-181
Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-182
FLUSH-Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . 5-183
Cache-Invalidation Cycle (INVD Instruction) . . . . . . . . . . 5-184
Cache-Writeback and Invalidation Cycle
(WBINVD Instruction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-185
Branch-Trace Message Cycles . . . . . . . . . . . . . . . . . . . . . . . 5-187
5.4.7 Mode Transitions, Reset, and Testing . . . . . . . . . . . . . . . . . 5-189
Transition from Normal Execution to SMM . . . . . . . . . . . . 5-189
Stop-Grant and Stop-Clock States . . . . . . . . . . . . . . . . . . . . 5-192
INIT-Initiated Transition from Protected
Mode to Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-195
6 System Design 6-1
6.1 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.1.2 Memory-Decoder Aliasing of Boot ROM Space . . . . . . . . . . . 6-4
6.1.3 Cacheable and Noncacheable Address Spaces . . . . . . . . . . . 6-4
6.1.4 SMM Memory Space and Cacheability . . . . . . . . . . . . . . . . . . 6-5
6.2 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.2.1 L2 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.2.2 Cacheability and Cache-State Control . . . . . . . . . . . . . . . . . . 6-9
6.2.3 Writethrough vs. Writeback Coherency States . . . . . . . . . . 6-10
6.2.4 Inquire Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6.2.5 Bus Arbitration for Inquire Cycles . . . . . . . . . . . . . . . . . . . . 6-14
BOFF Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
AHOLD Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
HOLD Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6.2.6 Write-Once Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
6.2.7 Cache Invalidations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.2.8 A20M Masking of Cache Accesses . . . . . . . . . . . . . . . . . . . . . 6-22
6.3 System Management Mode (SMM) . . . . . . . . . . . . . . . . . . . . . 6-23
6.3.1 Operating Mode and Default Register Values . . . . . . . . . . . 6-24
6.3.2 SMM State-Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
6.3.3 SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28
6.3.4 SMM Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28
6.3.5 Halt Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
6.3.6 I/O Trap Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
6.3.7 I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31

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6.3.8 Exceptions and Interrupts in SMM . . . . . . . . . . . . . . . . . . . . 6-32
6.3.9 SMM Compatibility with Pentium Processor . . . . . . . . . . . . 6-33
6.4 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
6.4.1 State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34
6.4.2 Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34
6.4.3 Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37
6.4.4 Stop Grant Inquire State . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37
6.4.5 Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38
6.4.6 Clock Control Compatibility with Pentium Processor . . . . 6-38
6.5 Power and Ground Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38
6.6 Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40
6.7 Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41
6.8 Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42
6.9 Design Support and Peripheral Products . . . . . . . . . . . . . . . . 6-43
7 Test and Debug 7-1
7.1 Hardware Configuration Register (HWCR) . . . . . . . . . . . . . . . 7-3
7.2 Built-In Self Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.2.1 Normal BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.2.2 Test Access Port (TAP) BIST . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.3 Output-Float Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.4 Cache and TLB Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.4.1 Array Access Register (AAR) . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.4.2 Array Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.4.3 Array Test Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.5 Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
7.5.1 Standard Debug Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
7.5.2 I/O Breakpoint Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
7.5.3 Debug Compatibility with Pentium Processor . . . . . . . . . . . 7-17
7.6 Branch Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
7.7 Functional-Redundancy Checking . . . . . . . . . . . . . . . . . . . . . . 7-18
7.8 Boundary-Scan Test Access Port (TAP) . . . . . . . . . . . . . . . . . . 7-19
7.8.1 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . 7-21
7.8.2 Public Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
7.9 Hardware Debug Tool (HDT) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23

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Appendix A Compatibility With the Pentium and 486 Processors A-1
A.1 Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A.1.1 Signal Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A.2 Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
A.2.1 Updates to Descriptor Accessed and TSS Busy Bits . . . . . . . A-5
A.2.2 Locked and Unlocked CMPXCHG8B Operation . . . . . . . . . . A-5
A.2.3 Bus Cycle Order of Misaligned Memory and I/O Cycles . . . . A-6
A.2.4 Halt Cycle after FLUSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6
A.2.5 Selectable Drive Strengths on Output Driver . . . . . . . . . . . . A-6
Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7
A.3 Bus Mastering Operations (including Snooping) . . . . . . . . . . A-8
A.3.1 AHOLD Snoop to Linefill Buffer Prior to or Coincident
with the Establishment of the Cacheability of the Line . . . . A-8
Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8
A.3.2 BOFF Asserted before Snoop to Linefill Buffer and
after the Cacheability of the Line is Established . . . . . . . . . . A-8
Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9
A.3.3 Snoop Before Write Hit to ICACHE Appears on Bus . . . . . . A-9
A.3.4 Invalidations during a FLUSH/WBINVD . . . . . . . . . . . . . . . . A-9
A.3.5 Cache Line Ownership . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10
A.3.6 Write Hit to a Shared Line in the DCACHE . . . . . . . . . . . . . A-10
A.4 Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11
A.4.1 Speculative TLB Refills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11
A.4.2 Page Fault Encountered by a Load/Store
Type of Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11
A.5 Power Saving Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12
A.5.1 STPCLK in Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12
A.5.2 STPCLK Pulse does not Guarantee That
One Instruction Executes . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12
A.5.3 Simultaneous I/O SMI Trap and Debug Breakpoint Trap . . A-12
A.5.4 SMM Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13
A.5.5 NMI Recognition during SMM . . . . . . . . . . . . . . . . . . . . . . . . A-13
Comment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13
A.6 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-14
A.6.1 Limit Faults on an Invalid Instruction . . . . . . . . . . . . . . . . . A-14
A.6.2 Task Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-14
A.7 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-15
A.7.1 Proprietary Branch Trace Messages . . . . . . . . . . . . . . . . . . . A-15
A.7.2 Multiple Debug Breakpoint Matches . . . . . . . . . . . . . . . . . . A-15
A.7.3 Simultaneous Debug Trap and Debug Fault . . . . . . . . . . . . A-15

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18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
List of Figures
Figure 2-1. Internal Architecture, with Pipeline Stage . . . . . . . . . . . 2-2
Figure 2-2. Pipeline Stage Functions . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Figure 3-1. Control Register 4 (CR4) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Figure 3-2. 4-Kbyte Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Figure 3-3. 4-Mbyte Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Figure 3-4. Page-Directory Entry (PDE). . . . . . . . . . . . . . . . . . . . . . . . 3-7
Figure 3-5. Page-Table Entry (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Figure 3-6. EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Figure 3-7. Task State Segment (TSS) . . . . . . . . . . . . . . . . . . . . . . . . 3-22
Figure 3-8. Machine-Check Address Register (MCAR) . . . . . . . . . . 3-25
Figure 3-9. Machine-Check Type Register (MCTR) . . . . . . . . . . . . . 3-26
Figure 5-1. Signal Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Figure 5-2. Single-Transfer Memory Read and Write. . . . . . . . . . . 5-143
Figure 5-3. Single-Transfer Memory Write Delayed
by EWBE Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-145
Figure 5-4. I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-146
Figure 5-5. Single-Transfer Misaligned Memory and
I/O Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-148
Figure 5-6. Burst Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-151
Figure 5-7. Burst Read (NA Sampled) . . . . . . . . . . . . . . . . . . . . . . . 5-152
Figure 5-8. Burst Writeback Due To Cache-Line Replacement. . . 5-155
Figure 5-9. AHOLD-Initiated Inquire Miss . . . . . . . . . . . . . . . . . . . 5-158
Figure 5-10. AHOLD-Initiated Inquire Hit to Shared
or Exclusive Line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-159
Figure 5-11. AHOLD-Initiated Inquire Hit to Modified Line. . . . . . 5-161
Figure 5-12. Basic BOFF Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 5-163
Figure 5-13. BOFF-Initiated Inquire Hit to Modified Line. . . . . . . . 5-165
Figure 5-14. HOLD-Initiated Inquire Hit to Shared
or Exclusive Line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-167
Figure 5-15. HOLD-Initiated Inquire Hit to Modified Line . . . . . . . 5-168
Figure 5-16. Basic Locked Operation . . . . . . . . . . . . . . . . . . . . . . . . . 5-170
Figure 5-17. TLB Miss (4-Kbyte Page) . . . . . . . . . . . . . . . . . . . . . . . . 5-172
Figure 5-18. Locked Operation with BOFF Intervention . . . . . . . . . 5-174
Figure 5-19A. Interrupt Acknowledge Operation Part 1. . . . . . . . . . . 5-177
Figure 5-19B. Interrupt Acknowledge Operation Part 2. . . . . . . . . . . 5-178
Figure 5-19C. Interrupt Acknowledge Operation Part 3. . . . . . . . . . . 5-179
Figure 5-20. Basic Special Bus Cycle (Halt Cycle) . . . . . . . . . . . . . . 5-181
Figure 5-21. Shutdown Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-182
Figure 5-22. FLUSH-Acknowledge Cycle. . . . . . . . . . . . . . . . . . . . . . 5-183
Figure 5-23. Cache-Invalidation Cycle (INVD Instruction) . . . . . . . 5-184
Figure 5-24A. Cache-Writeback and Invalidation Cycle
(WBINVD Instruction) Part 1 . . . . . . . . . . . . . . . . . . . . 5-185

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Figure 5-24B. Cache-Writeback and Invalidation Cycle
(WBINVD Instruction) Part 2 . . . . . . . . . . . . . . . . . . . . 5-186
Figure 5-25. Branch-Trace Message Cycle . . . . . . . . . . . . . . . . . . . . . 5-188
Figure 5-26A. Transition from Normal Execution to SMM Part 1 . . . 5-190
Figure 5-26B. Transition from Normal Execution to SMM Part 2 . . . 5-191
Figure 5-27A. Stop-Grant and Stop-Clock Modes Part 1 . . . . . . . . . . . 5-193
Figure 5-27B. Stop-Grant and Stop-Clock Modes Part 2 . . . . . . . . . . . 5-194
Figure 5-28. INIT-Initiated Transition from Protected
Mode to Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-196
Figure 6-1. Typical Desktop-System BIOS Memory Map . . . . . . . . . . 6-3
Figure 6-2. Default SMM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Figure 6-3. BOFF Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Figure 6-4. AHOLD and BOFF Example . . . . . . . . . . . . . . . . . . . . . . 6-18
Figure 6-5. Write-Once Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Figure 6-6. Clock Control State Transitions. . . . . . . . . . . . . . . . . . . . 6-36
Figure 6-7. Vcc and CLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40
Figure 7-1. Hardware Configuration Register (HWCR) . . . . . . . . . . . 7-3
Figure 7-2. Array Access Register (AAR) . . . . . . . . . . . . . . . . . . . . . . 7-8
Figure 7-3. Test Formats: Data-Cache Tags . . . . . . . . . . . . . . . . . . . . 7-10
Figure 7-4. Test Formats: Data-Cache Data . . . . . . . . . . . . . . . . . . . . 7-11
Figure 7-5. Test Formats: Instruction-Cache Tags. . . . . . . . . . . . . . . 7-12
Figure 7-6. Test Formats: Instruction-Cache Instructions . . . . . . . . 7-13
Figure 7-7. Test Formats: 4-Kbyte TLB. . . . . . . . . . . . . . . . . . . . . . . . 7-14
Figure 7-8. Test Formats: 4-Mbyte TLB . . . . . . . . . . . . . . . . . . . . . . . 7-15

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List of Tables
Table 2-1. ALU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Table 2-2. Cache States for Read and Write Accesses . . . . . . . . . . . . 2-19
Table 2-3. Cache States for Snoops, Invalidation,
and Replacements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Table 2-4. Snoop Action. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Table 3-1. Control Register 4 (CR4) Fields . . . . . . . . . . . . . . . . . . . . . . 3-3
Table 3-2. Page-Directory Entry (PDE) Fields . . . . . . . . . . . . . . . . . . . 3-8
Table 3-3. Page-Table Entry (PTE) Fields. . . . . . . . . . . . . . . . . . . . . . 3-11
Table 3-4. Virtual-Interrupt Additions to EFLAGS Register . . . . . . 3-15
Table 3-5A. Instructions that Modify the IF or VIF
Flags—Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Table 3-5B. Instructions that Modify the IF or VIF
Flags—Protected Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
Table 3-5C. Instructions that Modify the IF or VIF
Flags—Virtual-8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
Table 3-5D. Instructions that Modify the IF or
VIF Flags—Virtual-8086 Mode Interrupt
Extensions (VME) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Table 3-5E. Instructions that Modify the IF or
VIF Flags—Protected Mode Virtual
Interrupt Extensions (PVI) . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Table 3-6. Interrupt Behavior and Interrupt-Table Access . . . . . . . . 3-23
Table 3-7. Machine-Check Type Register (MCTR) Fields . . . . . . . . . 3-27
Table 3-8. CPU Clock Frequencies, Bus Frequencies,
and P-Rating Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
Table 4-1. Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Table 4-2. Integer Dot Product Internal Operations Timing . . . . . . . 4-18
Table 4-3. Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Table 5-1. Summary of Signal Characteristics . . . . . . . . . . . . . . . . . . . 5-4
Table 5-2. Conditions for Driving and Sampling Signals . . . . . . . . . . . 5-8
Table 5-3. Summary of Interrupts and Exceptions. . . . . . . . . . . . . . . 5-16
Table 5-4. Address-Generation Sequence During Bursts. . . . . . . . . . 5-21
Table 5-5. Relation Of BE7–BE0 To Other Signals . . . . . . . . . . . . . . . 5-34
Table 5-6. Encodings For Special Bus Cycles . . . . . . . . . . . . . . . . . . . 5-35
Table 5-7. Processor-to-Bus Clock Ratios. . . . . . . . . . . . . . . . . . . . . . . 5-36
Table 5-8. Outputs Floated When BOFF is Asserted . . . . . . . . . . . . . 5-38
Table 5-9. MESI-State Transitions for Reads . . . . . . . . . . . . . . . . . . . 5-51
Table 5-10. Relation Between D63–D0, BE7–BE0, and DP7–DP0 . . . . 5-56
Table 5-11. MESI-State Transitions for Inquire Cycles . . . . . . . . . . . . 5-71
Table 5-12. Outputs Floated When HLDA is Asserted. . . . . . . . . . . . . 5-74
Table 5-13. Interrupt Acknowledge Operation Definition. . . . . . . . . . 5-85
Table 5-14. PWT, Writeback/Writethrough, and MESI . . . . . . . . . . . 5-105
Table 5-15. Register State After RESET or INIT . . . . . . . . . . . . . . . . 5-110

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Table 5-16. Outputs at RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-112
Table 5-17. MESI-State Transitions for Reads . . . . . . . . . . . . . . . . . . 5-134
Table 5-18. MESI-State Transitions for Writes . . . . . . . . . . . . . . . . . . 5-135
Table 5-19. Bus Cycle Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-136
Table 5-20. Bus-Cycle Order During Misaligned Transfers . . . . . . . . 5-147
Table 5-21. Address-Generation Sequence During Bursts. . . . . . . . . 5-150
Table 5-22. Interrupt Acknowledge Operation Definition. . . . . . . . . 5-175
Table 5-23. Encodings For Special Bus Cycles . . . . . . . . . . . . . . . . . . 5-180
Table 5-24. Branch-Trace Message Special Bus Cycle Fields . . . . . . 5-187
Table 6-1. Initial State of Registers in SMM . . . . . . . . . . . . . . . . . . . . 6-25
Table 6-2. SMM State-Save Area Map . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
Table 7-1. Hardware Configuration Register (HWCR) Fields. . . . . . . 7-4
Table 7-2. BIST Error Bit Definition in EAX Register . . . . . . . . . . . . . 7-6
Table 7-3. Array IDs in Array Pointers . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
Table 7-4. Branch-Trace Message Special Bus Cycle Fields . . . . . . . 7-18
Table 7-5. Test Access Port (TAP) ID Code. . . . . . . . . . . . . . . . . . . . . 7-21
Table 7-6. Public TAP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22

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Preface
This manual describes the technical features of the AMD-K5™ processor, and its dif-
ferences from the Pentium processor, at a level of detail suitable for a hardware
designer or system-software developer to implement system boards, core system
logic, and system software. Specifically, the manual describes the following aspects
of the processor
■Internal architecture
■Software differences from the 486 and Pentium processors
■Performance parameters
■Bus signals functions
■Bus cycle timing
■Design issues for system-board designs
■Test and debugging features
A full description of the x86 programming environment is beyond the scope of this
manual. Instead, the software sections describe differences from the 486 processor’s
programming environment. A list of commercial books that describe the x86 pro-
gramming environment and other subjects of potential interest appears at the end of
this preface.
In addition to descriptions of the AMD-K5 processor’s unique internal architecture,
the manual incorporates details about the behavior of bus signals and bus cycles that
are standard to the x86 processors but that are not fully documented in other x86
manuals.
Notation
The following notation is used in this manual:
b—Binary
d—Decimal
h—Hexadecimal
Set—Written with a value of 1
Clear—Written with a value of 0
GP (0)—General-protection exception (13 decimal) with an error value of 0

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EFLAGS.IF—The IF bit in the EFLAGS register
CS:EIP—A logical address, expressed as a segment selector (CS) and offset (EIP)
000F_FFF0h—A physical-memory address using hexadecimal notation
Terminology
The following definitions apply throughout this document:
■Pin and Signal—A pin is a piece of metal on the processor’s package. A signal is
the information about logical states that a pin carries. Pins have pin numbers; sig-
nals have signal names. On processors that multiplex signals, pins can carry more
than one signal; the AMD-K5 processor, however, does not multiplex signals in
this manner.
■Assert and Negate—A signal that is driven or sampled active is asserted. A signal
that is inactive is negated. In general, asserted means sampled asserted either by
the processor or target logic. Signals that are active in a Low-voltage state, such as
BRDY, are shown with an overbar. Signals that are active in a High-voltage state,
such as INTR, are shown without an overbar. Dual-state signals, such as R/S and
WB/WT, have two states of assertion and, therefore, the term asserted has no
meaning; such dual-state signals are driven High or Low.
■Drive and Sample—A single-state signal is driven when it is asserted or negated by
a logic device; it is sampled when its driven state is detected by another device.
■Cycle and Clock—This term commonly refers to at least four different things:
•Bus-clock period: The cycle time of the CLK signal.
•Processor-clock period: The cycle time of the processor’s internal clock, which
has a frequency relative to CLK that is determined by the state of the BF sig-
nal(s) during RESET. Whenever this cycle is meant, such as in the Chapter 4
description of pipeline timing and the instruction latency, the full name, pro-
cessor-clock cycle, is used.
•Bus cycle: A signal protocol on the processor’s bus, such as a single-transfer
read cycle or a special bus cycle.
•Sequence of bus cycles: One or more contiguous bus cycles. For example, the two
bus cycles that constitute an interrupt acknowledgment are called a bus opera-
tion, so that the constituent bus cycles can be distinguished from the entire op-
eration.

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■Writeback—This term refers to two related concepts:
•Bus Cycle—A 32-byte burst write cycle to a memory block that has been cached
in the modified state. Writebacks can be caused by inquire cycles, internal
snoops, writeback and invalidate operations (such as FLUSH or the WBINVD
instruction), cache-line replacements, or locked operations on cached loca-
tions. It is sometimes called a copyback.
•Cache-Line State—A cache line in the modified or exclusive MESI state (modi-
fied, exclusive, shared, invalid).
■Writethrough—This term refers to two related concepts:
•Bus Cycle—A 1-to-8-byte, single-transfer write cycle caused by write misses or
write hits to lines in the shared or exclusive MESI state.
•Cache-Line State—A cache line in the shared MESI state.
■Flush—This term commonly refers to at least four things and is usually avoided in
favor of the following specific terms:
•Pipeline Invalidation: A pipeline-flush operation invalidates instructions in the
pipeline that have not been retired (and, depending on the type of pipeline in-
validation, entries in the reorder buffer, entries in the TLB, and/or branch-pre-
diction bits) without writing their state to any storage resource.
•Cache Invalidation: The INVD instruction invalidates the contents of the in-
struction and data caches, without writing modified data back to memory.
•Cache Writeback and Invalidation: The WBINVD instruction writes modified
lines in the data cache back to memory while invalidating each line in the in-
struction and data caches.
•FLUSH Operation: The FLUSH input signal executes the same microcode rou-
tine as the WBINVD instruction to write modified lines in the data cache back
to memory while invalidating each line in the instruction and data caches.
■Flush Acknowledge Cycle—This term commonly refers to different types of special
bus cycles driven by the processor, and is therefore avoided in favor of the follow-
ing specific terms:
•FLUSH Acknowledge: A special bus cycle driven after the FLUSH operation
completes.
•INVD Acknowledge: A special bus cycle driven after the INVD cache invalida-
tion completes.
•WBINVD Acknowledge: A sequence of two special bus cycles driven after the
WBINVD cache writeback and invalidation completes.
■Snoop—This term commonly refers to at least three different actions and is there-
fore avoided in favor of the following specific terms:
•Inquire Cycles: These are bus cycles driven by system logic. They cause the pro-
cessor to compare the inquire-cycle address with the processor’s physical

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cache tags. The AMD-K5 and Pentium processors both support inquire cycles.
•Internal Snooping: These snoops are initiated by the processor (rather than sys-
tem logic) during certain types of cache accesses. Both the AMD-K5 and Pen-
tium microprocessors support this type of internal snooping for the purpose of
detecting self-modifying code. See page 2-22 for details.
•Bus Watch: Some caching devices watch their address and data bus continu-
ously while they are held off the bus. They compare every address driven by
another bus master with their internal cache tags, and they may also be able to
update their cached lines during writebacks to memory by another bus master.
Neither the AMD-K5 nor Pentium microprocessors support bus watching.
■Cold and Warm Reset—The terms cold or hard reset and warm or soft reset are
commonly used to mean three related but different things, and the terms are
therefore avoided. A cold or hard reset typically refers to the assertion of RESET
at power-up, but warm or soft reset can refer either to the assertion of RESET
after power-up or to the assertion of INIT.
■System Logic—Any logic outside the processor, including a core-logic chipset,
another bus master, or separate controllers for L2 cache, memory, interrupts,
DMA, communications, video, bus bridging, bus arbitration, or any other system
function.
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AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
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