AMD ATHLON K Instructions for use

AMD Athlon™ Processor Model 4
Revision Guide
Publication # 23614 Rev: K
Issue Date: October 2003
Preliminary Information

Preliminary Information
Trademarks
AMD, the AMD Arrow logo, AMD Athlon, AMD Duron, and combinations thereof, AMD-751, and AMD-756 are
trademarks of Advanced Micro Devices, Inc.
Other product names used in this publication are for identification purposes only and may be trademarks of
their respective companies.
© 2001–2003 Advanced Micro Devices, Inc.
All rights reserved.
The contents of this document are provided in connection with Advanced
Micro Devices, Inc. (“AMD”) products. AMD makes no representations or
warranties with respect to the accuracy or completeness of the contents of
this publication and reserves the right to make changes to specifications and
product descriptions at any time without notice. No license, whether express,
implied, arising by estoppel or otherwise, to any intellectual property rights
is granted by this publication. Except as set forth in AMD’s Standard Terms
and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims
any express or implied warranty, relating to its products including, but not
limited to, the implied warranty of merchantability, fitness for a particular
purpose, or infringement of any intellectual property right.
The AMD products described herein may contain design defects or errors
(“Product Errata”) that cause AMD products to deviate from published
specifications. Currently characterized Product Errata may be available upon
request.
AMD’s products are not designed, intended, authorized or warranted for use
as components in systems intended for surgical implant into the body, or in
other applications intended to support or sustain life, or in any other
application in which the failure of AMD’s product could create a situation
where personal injury, death, or severe property or environmental damage
may occur. AMD reserves the right to discontinue or make changes to its
products at any time without notice.

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23614K —October 2003 AMD Athlon™ Processor Model 4 Revision Guide
Preliminary Information
Revision History
Date Rev Description
October 2003 K Revised erratum #24.
June 2003 J Added erratum #24.
December 2002 I Added errata #21–23.
July 2002 H Added erratum #20.
March 2002 G Added erratum #17.
April 2001 F Removed OPN information. Added errata items 13, 14, 15, 16. Added information on silicon
revision A9.

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AMD Athlon™ Processor Model 4 Revision Guide 23614K —October 2003
Preliminary Information
AMD Athlon™ Processor Model 4
Revision Guide
The purpose of the AMD Athlon™ Processor Model 4 Revision Guide is to communicate updated product
information on the AMD Athlon™ processor model 4 to designers of computer systems and software
developers. This guide consists of three sections:
■Product Errata: This section, which starts on page 5, provides a detailed description of product
errata, including potential effects on system operation and suggested workarounds. An erratum is
defined as a deviation from the product’s specification. A product errata may cause the behavior of
the AMD Athlon™ Processor Model 4 to deviate from published specifications.
■Revision Determination: This section, which starts on page 20, shows the AMD Athlon processor
model 4 identification numbers returned by the CPUID instruction for each revision of the
processor.
■Technical and Documentation Support: This section, which starts on page 21, provides a listing of
available technical support resources. It also lists corrections, modifications, and clarifications to
listed documents. Please refer to the data sheets listed in this section for product marking
information.
Revision Guide Policy
Occasionally AMD identifies deviations from or changes to the specification of the AMD Athlon
processor model 4. These changes are documented in the AMD Athlon™ Processor Model 4 Revision
Guide as errata. Descriptions are written to assist system and software designers in using the AMD
Athlon processor model 4 and corrections to AMD’s documentation on the AMD Athlon processor
model 4 are included. This release documents currently characterized product errata, but is not
intended to identify all errata in the processor.

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23614K —October 2003 AMD Athlon™ Processor Model 4 Revision Guide
Preliminary Information
1 Product Errata
This section documents AMD Athlon processor model 4 product errata. The errata are divided into
categories to assist referencing particular errata. A unique tracking number for each erratum has been
assigned within this document for user convenience in tracking the errata within specific revision
levels. Table 1 cross-references the revisions of the processor to each erratum. An “X” indicates that
the erratum applies to the stepping. The absence of an “X” indicates that the erratum does not apply
to the stepping. Shading within the table indicates an addition or modification from the previous
release of this document.
Note: There can be missing errata numbers. Errata that have been resolved from early revisions of the
processor have been deleted, and errata that have been reconsidered may have been deleted or
renumbered.
Table 1. Cross-Reference of Product Revision to Errata
Errata Numbers and Description Revision Numbers
A4 A5 A6 A7 A9
5MCABusUnitControlRegisterMSR408HReturnsIncorrectInformation XXXXX
10 Resistance Value of the ZN and ZP Pins X X
11 PLL Overshoot on Wake-Up from Disconnect Causes Auto-Compensation
Circuit to Fail XXXXX
13InstructionExecutionDeadlock XXXX
14 Processors with Half-Frequency Multipliers May Hang Upon Wake-up from
Disconnect XXXXX
15 Processor Does Not Support Reliable Microcode Patch Mechanism X
16 INVLPG Instruction Does Not Flush Entire Four-Megabyte Page Properly with
Certain Linear Addresses XXXXX
17 Code Modifications that Coincide with Level 2 Instruction TLB Translations
May Escape Detection Resulting in Stale Code Execution XXXXX
20 A Speculative SMC Store Followed by an Actual SMC Store May Cause One-
Time Stale Execution XXXXX
21 Real Mode RDPMC with Illegal ECX May Cause Unpredictable Operation XXXXX
22UsingTaskGatesWithBreakpointsEnabledMayCauseUnexpectedFaultsXXXXX
23SingleStepAcrossI/OSMISkipsOneDebugTrap XXXXX
24 Software Prefetches May Report A Page Fault XXXXX

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AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003
Preliminary Information
5 MCA Bus Unit Control Register MSR 408H Returns Incorrect Information
Products Affected. A4, A5, A6, A7, A9
Normal Specified Operation. System reads to MSR 408h, MCA Bus Unit Control Register MC2_CTL, should
return correct information—the lower 32 bits in EAX and all zeros for the upper 32 bits in EDX.
Non-conformance. A read to the Machine Check Architecture (MCA) Bus Unit Control MSR 408h
(MC2_CTL) returns incorrect information in EDX. It returns the information stored in the upper 32
bits of the BU Status MSR 409h (MC2_STATUS) instead.
Potential Effect on System. If the system reads this MCA control register, the upper 32 bits, which are
reported in EDX, can contain unexpected data.
Suggested Workaround. This register is only implemented as a 32-bit register. Ignore the upper 32 bits
which are reported in EDX.
Resolution Status. No fix planned.

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23614K —October 2003 AMD Athlon™ Processor Model 4 Revision Guide
Preliminary Information
10 Resistance Value of the ZN and ZP Pins
Products Affected. A4, A5
Normal Specified Operation. The ZN and ZP pins are specified such that the AMD system bus output
drivers autocompensate to whatever resistance value is applied between ZN and VDD and ZP and
VSS.
Non-conformance. The AMD system bus driver impedance is approximately 20 ohms higher than the
applied resistor value.
Potential Effect on System. The AMD Athlon system bus signal quality for signals driven to the
Northbridge may be adversely affected.
Suggested Workaround. All motherboards should have ZN/ZP resistors set to approximately 20 ohms less
than the characteristic board impedance.
Resolution Status. Fix planned for a future revision.
Note: When future revisions of the processor are used with motherboards implementing the workaround,
the expected output impedance of the driver will continue to yield good signal quality. (For example,
with a motherboard setting of 40 ohms for ZN and ZP, an old part that drives with a 60-ohm driver
works properly. A revised part with a true 40-ohm driver also works properly.)

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AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003
Preliminary Information
11 PLL Overshoot on Wake-Up from Disconnect Causes Auto-Compensation Circuit to Fail
Products Affected. A4, A5, A6, A7, A9
Normal Specified Operation. The AMD Athlon processor model 4 PLL should return to the normal
operating frequency when reconnecting to the system bus after a disconnect where the PLL was
reduced to a lower operating frequency.
Non-conformance. The AMD Athlon processor model 4 PLL can exceed the normal operating frequency
when reconnecting to the system bus after a disconnect, causing a failure to maintain sufficient system
bus I/O drive strength levels in the driver compensation circuit. The compensation circuit attempts to
correct the drive strength, but if there is not sufficient time to perform this function, the system bus
cannot operate properly.
Potential Effect on System. The system hangs.
Suggested Workaround. The event can be avoided through BIOS manipulation of the reconnect timing
using the CLK_CTRL MSR. (See AMD Athlon™ and AMD Duron™ Processor CLK_CTRL MSR Settings,
order# 24478, for exact values.)
The time for the PLL to overshoot can be greatly shortened to reduce it to a very small time period that
does not enable the failure, and the time between the rampup and the reconnect to the system bus can
be increased such that a failure in the compensation circuit has enough time to recover before
reconnecting to the bus.
Resolution Status. Fix planned for a future revision.

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23614K —October 2003 AMD Athlon™ Processor Model 4 Revision Guide
Preliminary Information
13 Instruction Execution Deadlock
Products Affected. A4, A5, A6, A7
Normal Specified Operation. Legitimate instruction sequences should execute as specified.
Non-conformance. Under rare and unlikely conditions, the load-store unit, instruction scheduler and
effective address generation unit interact in such a way that deadlock a occurs, preventing further
instruction execution.
Potential Effect on System. The system hangs. No instructions complete and the processor will not respond
to interrupts.
Suggested Workaround. None.
Resolution Status. Fix planned for a future revision.

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AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003
Preliminary Information
14 Processors with Half-Frequency Multipliers May Hang Upon Wake-up from Disconnect
Products Affected. A4, A5, A6, A7, A9
Normal Specified Operation. The processor should reconnect to the system bus upon wake-up after a
disconnect while in the C2 and C3 ACPI low-power states.
Non-conformance. The processor uses a special circuit to wake up from a low-power state and reconnect
to the system bus when the nominal operating frequency is generated with a half-frequency multiplier.
This circuit is rarely observed to glitch when coming out of the C2 and C3 low-power states.
Potential Effect on System. The system will hang.
Suggested Workaround. Do not use the C2 or C3 ACPI states on processors that run at a nominal operating
frequency generated with a half-frequency multiplier. This can be accomplished by having the BIOS
not declare C2 or C3 support to the operating system in the Fixed ACPI Description Table (FADT).
Resolution Status. Fix planned for a future revision.