AMD Am186 CC User manual

Am186™CC/CH/CU Microcontrollers
User’s Manual
Order #21914B

© 1998 Advanced Micro Devices, Inc. All rights reserved.
Advanced Micro Devices, Inc. ("AMD") reserves the right to make changes in its products
without notice in order to improve design or performance characteristics.
The information in this publication is believed to be accurate at the time of publication, but AMD makes no representations or warranties with
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FusionE86 is a service mark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am186™CC/CH/CU Microcontrollers User’s Manual iii
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iv Am186™CC/CH/CU Microcontrollers User’s Manual

Am186™CC/CH/CU Microcontrollers User’s Manual v
TABLE OF CONTENTS
PREFACE INTRODUCTION XIX
Comm86 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
Purpose of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
Intended Audience. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
Overview of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
AMD Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxii
Documentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxii
Microcontroller-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii
CHAPTER 1 ARCHITECTURAL OVERVIEW 1-1
1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
1.2 Am186CC Communications Controller . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
1.2.1 Am186CH HDLC Microcontroller . . . . . . . . . . . . . . . . . . . . . . . .1-2
1.2.2 Am186CU USB Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . .1-3
1.2.3 Feature Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4
1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4
1.4 Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.4.1 Am186 Embedded CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.4.2 Serial Communications Support . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.4.2.1 Universal Serial Bus. . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.4.2.2 HDLC Channels and TSAs . . . . . . . . . . . . . . . . . . . .1-7
1.4.2.3 General Circuit Interface . . . . . . . . . . . . . . . . . . . . . .1-8
1.4.2.4 SmartDMA Channels . . . . . . . . . . . . . . . . . . . . . . . . .1-8
1.4.2.5 Asynchronous Serial Ports. . . . . . . . . . . . . . . . . . . . .1-9
1.4.2.6 Synchronous Serial Port . . . . . . . . . . . . . . . . . . . . . .1-9
1.4.3 System Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9
1.4.3.1 Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . . . . . .1-9
1.4.3.2 General-Purpose DMA Channels . . . . . . . . . . . . . .1-10
1.4.3.3 Programmable I/O Signals. . . . . . . . . . . . . . . . . . . .1-10
1.4.3.4 Programmable Timers . . . . . . . . . . . . . . . . . . . . . . .1-10
1.4.3.5 Hardware Watchdog Timer . . . . . . . . . . . . . . . . . . . 1-11
1.4.4 Memory and Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.4.4.1 System Interfaces and Clock Control. . . . . . . . . . . . 1-11
1.4.4.2 Dynamic Random Access Memory Support . . . . . . 1-11
1.4.4.3 Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-12
1.4.5 In-Circuit Emulator Support. . . . . . . . . . . . . . . . . . . . . . . . . . . .1-12
1.5 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-13
CHAPTER 2 CONFIGURATION BASICS 2-1
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
2.2 Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
2.2.1 Processor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
2.2.2 Processor Status Flags Register . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.2.3 Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
2.3 Memory Organization and Address Generation. . . . . . . . . . . . . . . . . . . .2-5
2.4 I/O Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
2.5 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
2.6 Segments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7

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vi Am186™CC/CH/CU Microcontrollers User’s Manual
2.7 Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
2.8 Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
2.8.1 Register and Immediate Operands . . . . . . . . . . . . . . . . . . . . . .2-9
2.8.2 Memory Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
CHAPTER 3 SYSTEM OVERVIEW 3-1
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
3.2 System Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
3.3 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4
3.4 Initialization and Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5
3.5 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
3.6 Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-28
3.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-28
3.6.2 Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-29
3.6.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-30
3.6.3.1 Address and Data Buses . . . . . . . . . . . . . . . . . . . . .3-30
3.6.3.2 Programmable Bus Sizing . . . . . . . . . . . . . . . . . . . .3-30
3.6.3.3 Byte Write Enables. . . . . . . . . . . . . . . . . . . . . . . . . .3-31
3.6.3.4 Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-31
3.6.3.5 Bus Mastering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-31
3.6.3.6 DRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . .3-32
3.7 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-32
3.7.1 Clock Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-32
3.7.2 PLL Bypass Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-34
3.8 Hardware-Related Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-34
3.9 Comparison To Other Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-34
3.10 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-34
CHAPTER 4 EMULATOR SUPPORT 4-1
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.2 System Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.2.1 Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.2.2 Emulator Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.3 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4.3.1 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4.3.2 Emulator-Related Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4.3.2.1 A19–A0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4.3.2.2 AD15–AD0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4.3.2.3 {ADEN} / BHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4.3.2.4 ALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.3.2.5 ARDY and SRDY. . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.3.2.6 BHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.3.2.7 BSIZE8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.3.2.8 [CAS1–CAS0] and [RAS1–RAS0] . . . . . . . . . . . . . .4-3
4.3.2.9 CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.3.2.10 LCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.3.2.11 MCS3–MCS0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
4.3.2.12 {ONCE} . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
4.3.2.13 QS1–QS0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
4.3.2.14 [RAS1–RAS0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
4.3.2.15 RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
4.3.2.16 RES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
4.3.2.17 RESOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
4.3.2.18 S2–S0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
4.3.2.19 S6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
4.3.2.20 SRDY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
4.3.2.21 UCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
4.3.2.22 {UCSX8} and WLB. . . . . . . . . . . . . . . . . . . . . . . . . . .4-5

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Am186™CC/CH/CU Microcontrollers User’s Manual vii
4.3.2.23 WHB and WR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
4.3.2.24 WLB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
4.3.2.25 WR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
4.3.3 Hardware-Related Considerations . . . . . . . . . . . . . . . . . . . . . . .4-5
4.3.4 Comparison to Other Devices . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
4.4 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
CHAPTER 5 CHIP SELECTS 5-1
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
5.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
5.3 System Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
5.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3
5.5 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4
5.5.1 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4
5.5.2 Selecting Memory and I/O Space . . . . . . . . . . . . . . . . . . . . . . .5-5
5.5.2.1 UCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5
5.5.2.2 LCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5
5.5.2.3 MCS3–MCS0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5
5.5.2.4 PCS7–PCS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6
5.5.3 Selecting DRAM Using the Chip Selects . . . . . . . . . . . . . . . . . .5-7
5.5.4 Overlapping Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8
5.5.5 Configuring Address and Data Buses . . . . . . . . . . . . . . . . . . . .5-9
5.5.5.1 UCS and LCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-9
5.5.5.2 Non-UCS and Non-LCS. . . . . . . . . . . . . . . . . . . . . . .5-9
5.5.5.3 PCS I/O Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-9
5.5.6 Programming Ready Signals and Wait States . . . . . . . . . . . . .5-10
5.5.7 Chip Select Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-10
5.5.8 Hardware-Related Considerations . . . . . . . . . . . . . . . . . . . . . .5-10
5.5.9 Software-Related Considerations . . . . . . . . . . . . . . . . . . . . . .5-10
5.5.10 Comparison to Other Devices. . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
CHAPTER 6 DRAM CONTROLLER 6-1
6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
6.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2
6.3 System Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2
6.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
6.5 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
6.5.1 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
6.5.2 DRAM Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
6.5.3 DRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4
6.5.4 Option to Overlap DRAM with PCS . . . . . . . . . . . . . . . . . . . . . .6-5
6.5.5 DRAM Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-5
6.5.5.1 DRAM Refresh Cycle. . . . . . . . . . . . . . . . . . . . . . . . .6-5
6.5.5.2 DRAM Refresh Intervals . . . . . . . . . . . . . . . . . . . . . .6-6
6.5.6 Hardware-Related Considerations . . . . . . . . . . . . . . . . . . . . . . .6-6
6.5.7 Software-Related Considerations . . . . . . . . . . . . . . . . . . . . . . .6-6
6.5.8 Comparison to Other Devices. . . . . . . . . . . . . . . . . . . . . . . . . . .6-7
6.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7
CHAPTER 7 INTERRUPTS 7-1
7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1
7.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-2
7.3 System Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3
7.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4

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7.5 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-6
7.5.1 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-6
7.5.1.1 Types of Interrupt Channels. . . . . . . . . . . . . . . . . . . .7-6
7.5.1.2 Using Maskable Interrupts . . . . . . . . . . . . . . . . . . . . .7-7
7.5.1.3 Using Nonmaskable Interrupts. . . . . . . . . . . . . . . . . .7-8
7.5.2 Definitions of Interrupt Terms . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8
7.5.3 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
7.5.3.1 Requesting the Interrupt . . . . . . . . . . . . . . . . . . . . . .7-9
7.5.3.2 Servicing the Interrupt . . . . . . . . . . . . . . . . . . . . . . .7-10
7.5.3.3 Acknowledging the Interrupt . . . . . . . . . . . . . . . . . .7-10
7.5.3.4 End-of-Interrupt (EOI) . . . . . . . . . . . . . . . . . . . . . . .7-10
7.5.3.5 Returning from the Interrupt. . . . . . . . . . . . . . . . . . .7-10
7.5.4 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7.5.4.1 Nonmaskable Interrupt and Software
Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7.5.4.2 Maskable Hardware Interrupt Priority. . . . . . . . . . . . 7-11
7.5.5 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-13
7.5.5.1 Maskable Interrupt Cycle . . . . . . . . . . . . . . . . . . . . .7-13
7.5.5.2 Interrupts In Polled Mode. . . . . . . . . . . . . . . . . . . . .7-14
7.5.5.3 Considerations for NMI, Software Interrupts,
and Traps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-14
7.5.5.4 Maskable Interrupt Overview . . . . . . . . . . . . . . . . . .7-14
7.5.5.5 Maskable Interrupt Block Diagram. . . . . . . . . . . . . .7-15
7.5.5.6 PIOs as Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .7-18
7.5.5.7 Registers Used . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18
7.5.6 Nonmaskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18
7.5.6.1 Software Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . .7-19
7.5.6.2 Divide Error Exception (Interrupt Type 00h). . . . . . .7-19
7.5.6.3 Trace Interrupt (Interrupt Type 01h). . . . . . . . . . . . .7-19
7.5.6.4 Nonmaskable Interrupt (Interrupt Type 02h) . . . . . .7-19
7.5.6.5 Breakpoint Interrupt (Interrupt Type 03h). . . . . . . . .7-19
7.5.6.6 INT0 Detected Overflow Exception
(Interrupt Type 04h) . . . . . . . . . . . . . . . . . . . . . . . . .7-19
7.5.6.7 Array Bounds Exception (Interrupt Type 05h) . . . . .7-20
7.5.6.8 Unused Opcode Exception (Interrupt Type 06h) . . .7-20
7.5.6.9 ESC Opcode Exception (Interrupt Type 07h). . . . . .7-20
7.5.7 Software-Related Considerations . . . . . . . . . . . . . . . . . . . . . .7-20
7.5.8 Comparison to Other Devices . . . . . . . . . . . . . . . . . . . . . . . . .7-20
7.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-20
CHAPTER 8 DMA CONTROLLER 8-1
8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1
8.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3
8.3 System Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4
8.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4
8.5 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-7
8.5.1 When to Use DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-9
8.5.2 DMA Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-9
8.5.3 DMA Request Synchronization . . . . . . . . . . . . . . . . . . . . . . . .8-10
8.5.4 DMA Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-10
8.5.5 DMA and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-10
8.5.6 General-Purpose DMA Channels . . . . . . . . . . . . . . . . . . . . . . 8-11
8.5.6.1 General-Purpose DMA Usage . . . . . . . . . . . . . . . . .8-12
8.5.6.2 General-Purpose DMA Cycle. . . . . . . . . . . . . . . . . .8-12
8.5.6.3 General-Purpose DMA Transfer Suspension. . . . . .8-13
8.5.6.4 General-Purpose DMA Source and Destination
Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-13

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8.5.6.5 General-Purpose DMA Terminal Count . . . . . . . . . .8-14
8.5.6.6 General-Purpose DMA Channel Operations . . . . . .8-14
8.5.7 SmartDMA Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-26
8.5.7.1 SmartDMA Channels Introduction . . . . . . . . . . . . . .8-26
8.5.7.2 SmartDMA Channel Request Source and
Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-27
8.5.7.3 SmartDMA Channel Memory Overview. . . . . . . . . .8-28
8.5.7.4 SmartDMA Channel Usage . . . . . . . . . . . . . . . . . . .8-31
8.5.7.5 SmartDMA Channel Cycle. . . . . . . . . . . . . . . . . . . .8-35
8.5.7.6 SmartDMA Channel Descriptor Format . . . . . . . . . .8-38
8.5.7.7 SmartDMA Channel Descriptor Polling . . . . . . . . . .8-41
8.5.7.8 SmartDMA Channel Interrupts. . . . . . . . . . . . . . . . .8-42
8.5.7.9 SmartDMA Channel Use Without CPU Intervention 8-42
8.5.8 DMA and USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-43
8.5.9 Software-Related Considerations . . . . . . . . . . . . . . . . . . . . . .8-43
8.5.10 Comparison to Other Devices . . . . . . . . . . . . . . . . . . . . . . . . .8-43
8.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-44
CHAPTER 9 PROGRAMMABLE I/O SIGNALS 9-1
9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1
9.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1
9.3 System Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-2
9.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5
9.5 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5
9.5.1 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5
9.5.2 Defining the PIO Signal as Input or Output . . . . . . . . . . . . . . . .9-5
9.5.3 Driving Data on the PIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6
9.5.4 Using PIOs as Open-Drain Outputs . . . . . . . . . . . . . . . . . . . . . .9-6
9.5.5 Setting and Clearing Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6
9.5.6 Hardware-Related Considerations . . . . . . . . . . . . . . . . . . . . . . .9-7
9.5.7 Software-Related Considerations . . . . . . . . . . . . . . . . . . . . . . .9-7
9.5.8 Comparison to Other Devices . . . . . . . . . . . . . . . . . . . . . . . . . .9-7
9.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7
CHAPTER 10 PROGRAMMABLE TIMERS 10-1
10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
10.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
10.3 System Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2
10.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2
10.5 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3
10.5.1 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3
10.5.2 Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3
10.5.3 Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3
10.5.4 Requesting Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5
10.5.5 Software Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-6
10.5.6 Generating Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-6
10.5.7 Pulse Width Demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-6
10.5.7.1 Handling Short Signal Durations . . . . . . . . . . . . . . .10-7
10.5.7.2 Handling Long Signal Durations . . . . . . . . . . . . . . .10-7
10.5.8 Software-Related Considerations. . . . . . . . . . . . . . . . . . . . . . .10-8
10.5.9 Comparison to Other Devices . . . . . . . . . . . . . . . . . . . . . . . . .10-8
10.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-8
CHAPTER 11 WATCHDOG TIMER 11-1
11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.3 System Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

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11.5 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.5.1 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.5.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.5.3 Hardware-Related Considerations . . . . . . . . . . . . . . . . . . . . . . 11-4
11.5.4 Software-Related Considerations . . . . . . . . . . . . . . . . . . . . . . 11-5
11.5.5 Comparison to Other Devices . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
CHAPTER 12 SERIAL COMMUNICATIONS OVERVIEW 12-1
12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1
12.2 System Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-2
12.2.1 Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-2
12.2.2 Sample Applications for the Am186CC Communications
Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-3
12.3 Serial Communications Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .12-6
12.3.1 Asynchronous and Synchronous Communications . . . . . . . . .12-6
12.3.2 Hardware Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-6
12.3.3 FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-7
12.3.4 Polled, Interrupt, and DMA Modes . . . . . . . . . . . . . . . . . . . . . .12-7
12.3.5 Simplex, Half-Duplex, and Full-Duplex Systems . . . . . . . . . . .12-8
CHAPTER 13 ASYNCHRONOUS SERIAL PORTS (UARTS) 13-1
13.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1
13.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-2
13.3 System Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3
13.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3
13.5 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-4
13.5.1 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-4
13.5.1.1 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-5
13.5.1.2 Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-6
13.5.1.3 Autobaud Mode (High-Speed UART Only) . . . . . . .13-7
13.5.2 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-8
13.5.2.1 Data Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-8
13.5.2.2 Address Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-9
13.5.2.3 Receive Status and Data . . . . . . . . . . . . . . . . . . . .13-10
13.5.2.4 Extended Reads and Writes . . . . . . . . . . . . . . . . .13-10
13.5.3 FIFOs (High-Speed UART Only) . . . . . . . . . . . . . . . . . . . . . . 13-11
13.5.3.1 Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.5.3.2 Receive FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-12
13.5.3.3 Using the FIFOs in Polled, Interrupt, or
DMA Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-12
13.5.4 CTS/RTR Hardware Flow Control . . . . . . . . . . . . . . . . . . . . .13-13
13.5.5 Clock Sources and Baud Rate . . . . . . . . . . . . . . . . . . . . . . . .13-14
13.5.5.1 Programming the Baud Rate . . . . . . . . . . . . . . . . .13-15
13.5.5.2 Receiver Bit Sampling . . . . . . . . . . . . . . . . . . . . . .13-16
13.5.5.3 Detecting the Baud Rate Automatically
(High-Speed UART Only). . . . . . . . . . . . . . . . . . . .13-16
13.5.6 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-19
13.5.7 Break Detection and Generation. . . . . . . . . . . . . . . . . . . . . . .13-20
13.5.8 Receive Special-Character Matching
(High-Speed UART Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-21
13.5.9 Interface to General-Purpose DMA Channels . . . . . . . . . . . .13-21
13.5.10 Hardware-Related Considerations . . . . . . . . . . . . . . . . . . . . .13-22
13.5.11 Software-Related Considerations . . . . . . . . . . . . . . . . . . . . .13-22
13.5.12 Comparison to Other Devices. . . . . . . . . . . . . . . . . . . . . . . . .13-23
13.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-23

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CHAPTER 14 SYNCHRONOUS SERIAL PORT (SSI) 14-1
14.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1
14.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1
14.3 System Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-2
14.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-3
14.5 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-4
14.5.1 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-4
14.5.2 Master/Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .14-4
14.5.3 Signal Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-4
14.5.3.1 SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-4
14.5.3.2 SDATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-5
14.5.3.3 SDEN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-5
14.5.3.4 SSI Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . .14-6
14.5.4 Software-Related Considerations . . . . . . . . . . . . . . . . . . . . . .14-8
14.5.5 Comparison to Other Devices . . . . . . . . . . . . . . . . . . . . . . . . .14-8
14.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-9
CHAPTER 15 HIGH-LEVEL DATA LINK CONTROL (HDLC) 15-1
15.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1
15.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-2
15.3 System Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-4
15.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-5
15.5 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-7
15.5.1 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-7
15.5.2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-8
15.5.2.1 SmartDMA Interface . . . . . . . . . . . . . . . . . . . . . . . .15-8
15.5.2.2 Programmed I/O Interface . . . . . . . . . . . . . . . . . . . .15-8
15.5.3 General HDLC Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-9
15.5.4 HDLC Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-10
15.5.5 HDLC Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-14
15.5.6 HDLC and SmartDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-18
15.5.6.1 HDLC Transmitter . . . . . . . . . . . . . . . . . . . . . . . . .15-18
15.5.6.2 HDLC Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . .15-19
15.5.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-20
15.5.7.1 Transmit Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .15-20
15.5.7.2 Receive Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .15-20
15.5.8 Hardware-Related Considerations . . . . . . . . . . . . . . . . . . . . .15-20
15.5.9 Software-Related Considerations . . . . . . . . . . . . . . . . . . . . .15-21
15.5.10 Comparison to Other Devices . . . . . . . . . . . . . . . . . . . . . . . .15-21
15.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-21
CHAPTER 16 HDLC EXTERNAL SERIAL INTERFACE CONFIGURATION (TSAS) 16-1
16.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1
16.2 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-3
16.3 System Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-5
16.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-7
16.5 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-7
16.5.1 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-7
16.5.2 Programmable Time Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-8
16.5.3 Muxing Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-8
16.5.4 External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
16.5.4.1 Raw DCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
16.5.4.2 PCM Highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
16.5.4.3 GCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-14
16.5.5 Software-Related Considerations . . . . . . . . . . . . . . . . . . . . .16-14
16.5.6 Comparison to Other Devices . . . . . . . . . . . . . . . . . . . . . . . .16-14
16.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-14

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CHAPTER 17 GENERAL CIRCUIT INTERFACE (GCI) 17-1
17.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1
17.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1
17.3 System Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-3
17.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-5
17.5 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-5
17.5.1 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-5
17.5.1.1 Transmitting Data. . . . . . . . . . . . . . . . . . . . . . . . . . .17-6
17.5.1.2 Receiving Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-7
17.5.2 GCI Structure: Channels and Frames . . . . . . . . . . . . . . . . . . .17-8
17.5.3 GCI Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-8
17.5.4 GCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-9
17.5.4.1 GCI Bus Deactivation/Activation . . . . . . . . . . . . . . .17-9
17.5.4.2 GCI Bus Reversal . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17.5.5 GCI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-13
17.5.5.1 Four-Pin Interface . . . . . . . . . . . . . . . . . . . . . . . . .17-13
17.5.5.2 GCI-to-PCM Converted Pin Interface . . . . . . . . . .17-14
17.5.6 Operating Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-14
17.5.7 GCI Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-14
17.5.7.1 GCI HDLC Channel Steering. . . . . . . . . . . . . . . . .17-14
17.5.7.2 Monitor Channel Operation . . . . . . . . . . . . . . . . . .17-14
17.5.7.3 Monitor Channel Collision Detection . . . . . . . . . . .17-14
17.5.7.4 C/I Channel Operation . . . . . . . . . . . . . . . . . . . . . .17-15
17.5.7.5 TIC Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . .17-16
17.5.7.6 IC Channel Operation . . . . . . . . . . . . . . . . . . . . . .17-19
17.5.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-19
17.5.9 Software-Related Considerations . . . . . . . . . . . . . . . . . . . . .17-20
17.5.10 Comparison to Other Devices . . . . . . . . . . . . . . . . . . . . . . . .17-20
17.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-20
CHAPTER 18 UNIVERSAL SERIAL BUS (USB) 18-1
18.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-1
18.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-2
18.3 System Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-2
18.3.1 Signal Trade-Offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-2
18.3.1.1 USB Transceiver Interface. . . . . . . . . . . . . . . . . . . .18-3
18.3.1.2 Programmable Connect and Disconnect . . . . . . . . .18-3
18.3.1.3 USB Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . .18-5
18.3.1.4 Isochronous Synchronization Signals . . . . . . . . . . .18-6
18.3.2 DMA Trade-Offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-6
18.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-7
18.5 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-10
18.5.1 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-10
18.5.1.1 General USB Peripheral Controller
Programming Issues . . . . . . . . . . . . . . . . . . . . . . .18-10
18.5.1.2 Programming the Control Endpoint . . . . . . . . . . . . 18-11
18.5.1.3 Programming the Interrupt Endpoint . . . . . . . . . . . 18-11
18.5.1.4 Programming Data Endpoints . . . . . . . . . . . . . . . .18-12
18.5.2 Data Transmission and Data Types . . . . . . . . . . . . . . . . . . . .18-16
18.5.2.1 USB Suspend, Resume, and Remote Wakeup . . .18-16
18.5.2.2 USB Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-17
18.5.2.3 USB Protocol Handling, IN Direction . . . . . . . . . . .18-17
18.5.2.4 USB Protocol Handling, OUT Direction . . . . . . . . .18-17
18.5.3 Handling USB Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-18
18.5.4 Polled I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-18
18.5.5 Interrupt-Driven I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-19

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18.5.6 Using USB with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-19
18.5.6.1 DMA Availability. . . . . . . . . . . . . . . . . . . . . . . . . . .18-19
18.5.6.2 DMA/FIFO Interaction . . . . . . . . . . . . . . . . . . . . . .18-20
18.5.6.3 Setting Up DMA for USB . . . . . . . . . . . . . . . . . . . .18-21
18.5.6.4 Short Packets. . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-21
18.5.6.5 Error Recovery on Bulk and Interrupt Endpoints . .18-22
18.5.6.6 Error Recovery on Isochronous Endpoints . . . . . .18-23
18.5.7 Isochronous Transfer Synchronization . . . . . . . . . . . . . . . . .18-23
18.5.8 Isochronous Transfer Features . . . . . . . . . . . . . . . . . . . . . . .18-24
18.5.9 Command Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-26
18.5.9.1 Commands Handled by Device Software . . . . . . .18-26
18.5.9.2 Commands Handled by the USB Peripheral
Controller Hardware. . . . . . . . . . . . . . . . . . . . . . . .18-27
18.5.10 Command Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-28
18.5.10.1 Data Transfer Using the Control Endpoint . . . . . . .18-29
18.5.10.2 Control Endpoint Interrupts . . . . . . . . . . . . . . . . . .18-29
18.5.11 Interrupt Endpoint Programming . . . . . . . . . . . . . . . . . . . . . .18-29
18.5.11.1 USB Command Processing and the
Interrupt Endpoint . . . . . . . . . . . . . . . . . . . . . . . . .18-30
18.5.11.2 Data Transfer with the Interrupt Endpoint . . . . . . .18-30
18.5.11.3 Interrupt Endpoint Interrupts . . . . . . . . . . . . . . . . .18-30
18.5.12 Endpoint Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-30
18.5.12.1 Control Endpoint Definition . . . . . . . . . . . . . . . . . .18-30
18.5.12.2 Interrupt Endpoint Definition . . . . . . . . . . . . . . . . .18-31
18.5.12.3 Data Endpoint Definition . . . . . . . . . . . . . . . . . . . .18-32
18.5.13 Software-Related Considerations . . . . . . . . . . . . . . . . . . . . .18-33
18.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-33
APPENDIX A REGISTER SUMMARY A-1
GLOSSARY GLOSSARY-1
INDEX INDEX-1

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xiv Am186™CC/CH/CU Microcontrollers User’s Manual
LIST OF FIGURES
Figure 1-1 Am186CC Communications Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . .1-5
Figure 1-2 Am186CH HDLC Microcontroller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
Figure 1-3 Am186CU USB Microcontroller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
Figure 1-4 ISDN Terminal Adapter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-14
Figure 1-5 ISDN-to-Ethernet Low-End Router. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-14
Figure 1-6 32-Channel Linecard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-15
Figure 2-1 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
Figure 2-2 Processor Status Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
Figure 2-3 Physical Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
Figure 2-4 Memory and I/O Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
Figure 2-5 Supported Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
Figure 3-1 Typical Microcontroller Memory System With DRAM. . . . . . . . . . . . . . . . . . . . . . .3-29
Figure 3-2 Typical Microcontroller Memory System With SRAM . . . . . . . . . . . . . . . . . . . . . .3-29
Figure 3-3 Am186CC/CH/CU Microcontroller Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-33
Figure 5-1 Chip Selects and DRAM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
Figure 5-2 Chip Selectable Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6
Figure 5-3 Chip Selectable I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7
Figure 6-1 Chip Selects and DRAM Block Diagram (Same as Figure 5-1) . . . . . . . . . . . . . . . .6-2
Figure 7-1 Interrupts Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3
Figure 7-2 Interrupt Vector Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
Figure 7-3 Partial Block Diagram of Interrupt Controller Scheme . . . . . . . . . . . . . . . . . . . . . .7-15
Figure 8-1 DMA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3
Figure 8-2 Source Versus Destination Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-10
Figure 8-3 DMA Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-16
Figure 8-4 Source-Synchronized General-Purpose DMA Transfers . . . . . . . . . . . . . . . . . . . .8-18
Figure 8-5 Destination-Synchronized General-Purpose DMA Transfers . . . . . . . . . . . . . . . . .8-19
Figure 8-6 SmartDMA Channel Descriptor Ring Example. . . . . . . . . . . . . . . . . . . . . . . . . . . .8-29
Figure 8-7 SmartDMA Channel Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-30
Figure 8-8 SmartDMA Transmit Channel Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-37
Figure 8-9 SmartDMA Receive Channel Flow Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-38
Figure 9-1 PIO Operation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-2
Figure 10-1 Programmable Timers Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
Figure 10-2 Pulse Width Demodulation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-6
Figure 11-1 Watchdog Timer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Figure 11-2 Access to the WDTCON Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Figure 12-1 HDLC Control Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-4
Figure 12-2 POTS Linecard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-4
Figure 12-3 ISDN Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5
Figure 12-4 ISDN Application with GCI-to-PCM Highway Conversion . . . . . . . . . . . . . . . . . . .12-5
Figure 12-5 CTS/RTR Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-7
Figure 13-1 UARTs Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-2
Figure 13-2 UARTs Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-8
Figure 13-3 UARTs Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-8
Figure 13-4 RTR_U Signal Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-14
Figure 13-5 RTR_HU Signal Behavior with Receive FIFOs. . . . . . . . . . . . . . . . . . . . . . . . . . .13-14
Figure 13-6 UARTs Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-15
Figure 13-7 Worst Case % Error Per Bit vs. Baud Divisor Without Autobaud Enhancement .13-17
Figure 13-8 Detectable Baud Ranges for Various Frequencies. . . . . . . . . . . . . . . . . . . . . . . .13-17
Figure 13-9 Autobaud Enhancement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-18
Figure 13-10 Break Character Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-20
Figure 14-1 SSI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-2
Figure 14-2 Synchronous Serial Interface System Application Example. . . . . . . . . . . . . . . . . .14-3
Figure 14-3 SSI Multiple Transmit with SDEN as External Device Enable . . . . . . . . . . . . . . . .14-7
Figure 14-4 SSI Multiple Transmit with PIO as External Device Enable . . . . . . . . . . . . . . . . . .14-7
Figure 14-5 SSI Single-Transmit, Multiple-Receive with SDEN as External Device Enable . . .14-8
Figure 15-1 HDLC Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1

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Figure 15-2 HDLC, TSA, and GCI Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-3
Figure 15-3 HDLC Transmitter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-10
Figure 15-4 CTS Controlled Start of Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-14
Figure 15-5 CTS Controlled End of Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-14
Figure 15-6 CTS Inactive at End of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-14
Figure 15-7 HDLC Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-15
Figure 15-8 RTR Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-18
Figure 16-1 Block Diagram For TSA Multiplexing (Am186CC Communications Controller) . . .16-3
Figure 16-2 Block Diagram For TSA Multiplexing (Am186CH HDLC Microcontroller). . . . . . . .16-3
Figure 16-3 HDLC, TSA, and GCI Block Diagram (Same as Figure 15-2) . . . . . . . . . . . . . . . .16-4
Figure 16-4 ISDN PCM System Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-5
Figure 16-5 ISDN Basic-Rate GCI Application (Am186CC Communications Controller) . . . .16-10
Figure 16-6 Programmable Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-13
Figure 16-7 Converted GCI Clock and Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-13
Figure 17-1 HDLC, TSA, and GCI Block Diagram (Same as Figure 15-2) . . . . . . . . . . . . . . . .17-2
Figure 17-2 ISDN TA GCI-to-PCM Conversion System Application Example. . . . . . . . . . . . . .17-3
Figure 17-3 GCI Terminal Mode Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-8
Figure 17-4 Bus Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-10
Figure 17-5 Downstream Versus Upstream. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-12
Figure 17-6 GCI With Bus Reversal Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-12
Figure 17-7 GCI With Bus Reversal Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-13
Figure 17-8 TIC Bus Downstream Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-16
Figure 17-9 TIC Bus Upstream Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-16
Figure 18-1 USB Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-2
Figure 18-2 USB With Internal Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-4
Figure 18-3 USB With External Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-5

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xvi Am186™CC/CH/CU Microcontrollers User’s Manual
LIST OF TABLES
Table 0-1 Documentation Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxii
Table 1-1 Feature Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4
Table 2-1 Internal Processor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
Table 2-2 Configuration Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
Table 2-3 Peripheral Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
Table 2-4 Segment Register Selection Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
Table 2-5 Memory Addressing Mode Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
Table 3-1 Multiplexed Signal Trade-Offs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
Table 3-2 Multiplexed Signal Trade-Offs Ordered by PIO . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
Table 3-3 System Configuration Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4
Table 3-4 CPU and Internal Peripheral States Immediately Following Power-On Reset . . . . .3-6
Table 3-5 Reset Configuration Pins (Pinstraps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
Table 3-6 Signal Descriptions Table Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
Table 3-7 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10
Table 3-8 Programming Am186CC/CH/CU Microcontrollers Bus Width . . . . . . . . . . . . . . . .3-31
Table 5-1 Chip Selects Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3
Table 5-2 Chip Select Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3
Table 5-3 Signal Function When UCS or LCS is Configured for DRAM. . . . . . . . . . . . . . . . . .5-7
Table 6-1 DRAM Multiplexed Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2
Table 6-2 DRAM Controller Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
Table 6-3 DRAM Supported by the Am186CC/CH/CU Microcontrollers . . . . . . . . . . . . . . . . .6-4
Table 6-4 Address Multiplexing Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4
Table 6-5 Refresh Interval Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-6
Table 7-1 Interrupt Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4
Table 7-2 Interrupt Controller Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5
Table 7-3 Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-12
Table 7-4 Interrupt Channel Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-16
Table 7-5 Interrupt Channel Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-17
Table 8-1 DMA Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4
Table 8-2 DMA Controller Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4
Table 8-3 Am186CC Communications Controller DMA Channel Use . . . . . . . . . . . . . . . . . . .8-8
Table 8-4 Am186CH HDLC Microcontroller DMA Channel Use. . . . . . . . . . . . . . . . . . . . . . . .8-8
Table 8-5 Am186CU USB Microcontroller DMA Channel Use . . . . . . . . . . . . . . . . . . . . . . . . .8-9
Table 8-6 General-Purpose DMA Data Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
Table 8-7 General-Purpose DMA Request Source and Synchronization . . . . . . . . . . . . . . .8-17
Table 8-8 Maximum DMA Transfer Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-19
Table 8-9 Example Register Settings for UARTs and Circular Buffers . . . . . . . . . . . . . . . . . .8-22
Table 8-10 Am186CC SmartDMA Channel Request Source and Synchronization . . . . . . . . .8-27
Table 8-11 Am186CH SmartDMA Channel Request Source and Synchronization . . . . . . . . .8-28
Table 8-12 Am186CU SmartDMA Channel Request Source and Synchronization . . . . . . . . .8-28
Table 8-13 SmartDMA Transmit Channel Descriptor Format. . . . . . . . . . . . . . . . . . . . . . . . . .8-39
Table 8-14 SmartDMA Receive Channel Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . .8-40
Table 9-1 PIO Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3
Table 9-2 PIO Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5
Table 9-3 PIO Mode and PIO Direction Register Bit Settings. . . . . . . . . . . . . . . . . . . . . . . . . .9-6
Table 9-4 PIO Set and PIO Clear Registers’ Effect on PIO Data Register. . . . . . . . . . . . . . . .9-6
Table 10-1 Programmable Timer Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2
Table 10-2 Programmable Timers Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2
Table 10-3 Timer 0 and Timer 1 Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-4
Table 11-1 Watchdog Timer Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Table 11-2 Watchdog Timer Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Table 12-1 Multiplexed Signal Trade-Offs for Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . .12-2
Table 13-1 UARTs Multiplexed Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3
Table 13-2 UARTs Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-4
Table 13-3 Baud Rate Table for UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-15
Table 13-4 Examples of Autobaud Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-18

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Am186™CC/CH/CU Microcontrollers User’s Manual xvii
Table 13-5 UARTs Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-19
Table 14-1 SSI Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-2
Table 14-2 SSI Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-3
Table 15-1 HDLC/TSA/GCI Multiplexed Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-4
Table 15-2 HDLC Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-6
Table 16-1 HDLC/TSA/GCI Multiplexed Signals (Same as Table 15-1). . . . . . . . . . . . . . . . . .16-5
Table 16-2 TSA Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-7
Table 16-3 Timing Parameters Per Device (Supported PCM Codecs in GCI Mode) . . . . . . .16-14
Table 17-1 HDLC/TSA/GCI Multiplexed Signals (Same as Table 15-1). . . . . . . . . . . . . . . . . .17-3
Table 17-2 GCI Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-5
Table 17-3 GCI Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-13
Table 17-4 Converted GCI Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-14
Table 17-5 TIC Bus Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-16
Table 18-1 USB Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-3
Table 18-2 USB PLL Mode Pinstraps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-6
Table 18-3 USB Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-7
Table 18-4 USB Endpoints Used with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-20
Table 18-5 USB Commands Handled by Device Software. . . . . . . . . . . . . . . . . . . . . . . . . . .18-27
Table 18-6 USB Commands Handled by USB Peripheral Controller Hardware. . . . . . . . . . .18-28
Table 18-7 Control Endpoint Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-31
Table 18-8 Interrupt Endpoint Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-31
Table 18-9 Data Endpoints A–D Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-32
Table A-1 Am186CC/CH/CU Microcontrollers Register Summary . . . . . . . . . . . . . . . . . . . . . .A-2

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xviii Am186™CC/CH/CU Microcontrollers User’s Manual

Am186™CC/CH/CU Microcontrollers User’s Manual xix
PREFACE
INTRODUCTION
COMM86 FAMILY
The Am186™CC communications controller, Am186CH HDLC microcontroller, and
Am186CU USB microcontroller, the first members of the AMD Comm86™ family, are cost-
effective, high-performance embedded microcontroller solutions for communications
applications. These highly integrated microcontrollers enable customers to save system
costs and increase performance over 8-bit microcontrollers and other 16-bit
microcontrollers.
All of these microcontrollers offer the advantages of the x86 development environment’s
widelyavailablenativedevelopment tools,applications,and system software.Additionally,
the microcontrollers use the industry-standard 186 instruction set that is part of the AMD
E86™ family, which continually offers instruction-set-compatible upgrades. Built into each
of the microcontrollers is a wide range of communications features required in many
communications applications.
PURPOSE OF THIS MANUAL
Thismanual describesthe technicalfeaturesandprogramminginterfaceoftheAm186CC,
Am186CH, and Am186CU microcontrollers.
Intended Audience
The Am186CC/CH/CU Microcontrollers User’s Manual , order #21914, is intended for
computer software and hardware engineers and system architects who are designing or
are considering designing systems based on one of these controllers.
Overview of this Manual
This manual is organized into the following chapters:
■Chapter 1, “Architectural Overview,” provides an overview of the features of the
microcontrollers, including a block diagram and sample application diagrams.
■Chapter 2, “Configuration Basics,” provides basic information about configuring the
microcontrollers, including discussions of the registers, memory organization, address
generation, I/O space, peripheral control block, instruction set, segments, data types,
and addressing modes.
■Chapter 3, “System Overview,” contains descriptions of the microcontrollers’ system
configuration registers, initialization and processor reset, signals, bus interface, and
clock control.
■Chapter 4, “Emulator Support,” describes the various features available in the
microcontrollers to facilitate the design and operation of In-Circuit Emulators, and
discusses common concerns shared among emulator developers.
■Chapter 5, “Chip Selects,” describes the six chip selects provided for use with memory
devices and the eight provided for use with peripherals in either memory or I/O space.
■Chapter 6, “DRAM Controller,” discusses the fully integrated DRAM controller that
provides a glueless interface to 40-, 50-, 60-, and 70-ns Extended Data Out (EDO)
DRAM.

Introduction
xx Am186™CC/CH/CU Microcontrollers User’s Manual
■Chapter 7, “Interrupts,” describes the microcontrollers’ support for interrupts, both
maskableandnonmaskable.Itdiscussesinterruptsequenceandpriorityaswellashow
to configure the maskable interrupt sources through the interrupt channels. It also
describes the nonmaskable interrupts.
■Chapter 8,“DMAController,”describeshowtousetheDMAchannels(general-purpose
and SmartDMA channels) to transfer data between memory and internal and external
peripherals.
■Chapter 9,“ProgrammableI/OSignals,”discussestheuserprogrammableinput/output
signals (PIOs).
■Chapter 10, “Programmable Timers,” tells how to use the programmable timers for the
following tasks: counting or timing external events, generating nonrepetitive or variable-
duty-cyclewaveforms,generatinginterrupts,supportingreal-timecodingandtime-delay
applications through polling, prescaling the other timer, requesting DMA, or measuring
pulse widths (as a PWD).
■Chapter 11, “Watchdog Timer,” describes how to use the watchdog timer to generate
nonmaskable interrupts (NMIs), microcontroller resets, and system resets when the
programmable time-out value is reached.
■Chapter 12, “Serial Communications Overview,” discusses the serial communications
features of the microcontrollers and their trade-offs, and provides a brief overview of
serial communications.
■Chapter 13, “Asynchronous Serial Ports (UARTs),” describes how to use the UART and
High-Speed UART for asynchronous serial data transfer.
■Chapter 14,“SynchronousSerialPort(SSI),”discusseshowtousetheSSIsynchronous
serial port to provide half-duplex, bidirectional communications between the
microcontrollers and other system components
■Chapter 15, “High-Level Data Link Control (HDLC),” providesa brief overview of HDLC
and describes how to configure the HDLC channels to support data movement in a
variety of applications.
■Chapter 16, “HDLC External Serial Interface Configuration (TSAs),” describes how to
usethetime-divisionmultiplexfeaturestoconfiguretheHDLCexternalserialinterfaces.
Each Time-Slot Assigner (TSA) can be programmed to select between raw DCE and
dedicated PCM Highway external interfaces, as well as to multiplex GCI/PCM Highway
data.
■Chapter 17, “General Circuit Interface (GCI),” discusses how to configure the GCI
controller for a GCI interface on HDLC Channel A, or multiplexed GCI/PCM Highway
interfaces to the other channels
■Chapter 18, “Universal Serial Bus (USB),” covers the highly flexible integrated USB
peripheral controller and how to implement a variety of microcontroller-based USB
peripheral devices for telephony, audio, or other high-end applications.
■Appendix A, “Register Summary,” provides a summary of all the microcontroller
peripheral control block (PCB) registers, listed in offset order.
■The Glossary provides definitions of significant terms used in this manual.
■The Index contains extensive references to make it easier to find specific information.
CHCC
CHCC
CC
CUCC