GigaDevice Semiconductor GD32F1 0 Series User manual

GigaDevice Semiconductor Inc.
GD32F1x0
Arm® Cortex®-M3 32-bit MCU
For GD32F130xx,GD32F150xx
User Manual
Revision 3.7
(Jun. 2023)

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Table of Contents
Table of Contents.................................................................................................................2
List of Figures ....................................................................................................................15
List of Tables ......................................................................................................................21
1. System and memory architecture ............................................................................23
1.1. ARM Cortex-M3 processor......................................................................................23
1.2. Systemarchitecture................................................................................................24
1.3. Memory map............................................................................................................25
1.3.1. Bit-banding............................................................................................................28
1.3.2. On-chip SRAM memory ..........................................................................................28
1.3.3. On-chip Flash memory............................................................................................29
1.4. Boot configuration..................................................................................................29
1.5. Systemconfiguration registers (SYSCFG).............................................................31
1.5.1. System configuration register 0 (SYSCFG_CFG0) ......................................................31
1.5.2. EXTI sources selection register 0 (SYSCFG_EXTISS0) ...............................................32
1.5.3. EXTI sources selection register 1 (SYSCFG_EXTISS1) ...............................................33
1.5.4. EXTI sources selection register 2 (SYSCFG_EXTISS2) ...............................................34
1.5.5. EXTI sources selection register 3 (SYSCFG_EXTISS3) ...............................................36
1.5.6. System configuration register 2 (SYSCFG_CFG2) ......................................................37
1.6. Device electronic signature....................................................................................38
1.6.1. Memory density information.....................................................................................38
1.6.2. Unique device ID (96 bits) .......................................................................................39
2. Flash me mory controller (FMC) ................................................................................41
2.1. Overview..................................................................................................................41
2.2. Characteristics........................................................................................................41
2.3. Function overview...................................................................................................41
2.3.1. Flash memory architecture ......................................................................................41
2.3.2. Read operations ....................................................................................................42
2.3.3. Unlock the FMC_CTL register..................................................................................42
2.3.4. Page erase ...........................................................................................................42
2.3.5. Mass erase...........................................................................................................43
2.3.6. Main flash programming..........................................................................................45
2.3.7. Option bytes erase.................................................................................................46
2.3.8. Option bytes programming.......................................................................................47
2.3.9. Option bytes description..........................................................................................47
2.3.10. Page erase/Program protection................................................................................48

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2.3.11. Security protection .................................................................................................49
2.4. Register definition...................................................................................................50
2.4.1. Wait state register (FMC_WS)..................................................................................50
2.4.2. Unlock key register (FMC_KEY)...............................................................................50
2.4.3. Option bytes unlock key register (FMC_OBKEY).........................................................51
2.4.4. Status register (FMC_STAT) ....................................................................................51
2.4.5. Control register (FMC_CTL).....................................................................................52
2.4.6. Address register (FMC_ADDR) ................................................................................53
2.4.7. Option bytes status register (FMC_OBSTAT)..............................................................54
2.4.8. Write protection register (FMC_WP)..........................................................................54
2.4.9. Wait state enable register (FMC_WSEN) ...................................................................55
2.4.10. Product ID register (FMC_PID).................................................................................55
3. Power management unit (PMU) ................................................................................57
3.1. Overview..................................................................................................................57
3.2. Characteristics........................................................................................................57
3.3. Function overview...................................................................................................57
3.3.1. Backup domain......................................................................................................59
3.3.2. VDD / VDDA power domain.........................................................................................59
3.3.3. VDD domain...........................................................................................................60
3.3.4. 1.2V power domain ................................................................................................61
3.3.5. Power saving modes ..............................................................................................62
3.4. Register definition...................................................................................................64
3.4.1. Control register (PMU_CTL) ....................................................................................64
3.4.2. Power control/status register (PMU_CS)....................................................................65
4. Reset and clock unit (RCU) .......................................................................................67
4.1. Reset control unit (RCTL) .......................................................................................67
4.1.1. Overview ..............................................................................................................67
4.1.2. Function overview ..................................................................................................67
4.2. Clock control unit (CCTL) .......................................................................................68
4.2.1. Overview ..............................................................................................................68
4.2.2. Characteristics.......................................................................................................70
4.2.3. Function overview ..................................................................................................70
4.3. Register definition...................................................................................................74
4.3.1. Control register 0 (RCU_CTL0) ................................................................................74
4.3.2. Configuration register 0 (RCU_CFG0).......................................................................75
4.3.3. Interrupt register (RCU_INT) ....................................................................................79
4.3.4. APB2 reset register (RCU_APB2RST).......................................................................82
4.3.5. APB1 reset register (RCU_APB1RST).......................................................................83
4.3.6. AHB enable register (RCU_AHBEN).........................................................................85
4.3.7. APB2 enable register (RCU_APB2EN)......................................................................87

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4.3.8. APB1 enable register (RCU_APB1EN)......................................................................88
4.3.9. Backup domain control register (RCU_BDCTL)...........................................................90
4.3.10. Reset source /clock register (RCU_RSTSCK).............................................................92
4.3.11. AHB reset register (RCU_AHBRST)..........................................................................93
4.3.12. Configuration register 1 (RCU_CFG1).......................................................................94
4.3.13. Configuration register 2 (RCU_CFG2).......................................................................95
4.3.14. Control register 1 (RCU_CTL1) ................................................................................96
4.3.15. APB1 additional enable register (RCU_ADDAPB1EN) .................................................97
4.3.16. APB1 additional reset register (RCU_ADDAPB1RST)..................................................97
4.3.17. Voltage key register (RCU_VKEY)............................................................................98
4.3.18. Deep-sleep mode voltage register (RCU_DSV)...........................................................98
4.3.19. Power down voltage select register (RCU_PDVSEL)...................................................99
5. Interrupt / event controller (EXTI)...........................................................................100
5.1. Overview................................................................................................................100
5.2. Characteristics......................................................................................................100
5.3. Interrupts function overview.................................................................................100
5.4. External interrupt and event block diagram.........................................................103
5.5. External interrupt and event function overview ...................................................103
5.6. Register definition.................................................................................................106
5.6.1. Interrupt Enable register (EXTI_INTEN)...................................................................106
5.6.2. Event enable register (EXTI_EVEN)........................................................................106
5.6.3. Rising edge trigger enable register (EXTI_RTEN)......................................................107
5.6.4. Falling edge trigger enable register (EXTI_FTEN) .....................................................107
5.6.5. Software interrupt event register (EXTI_SWIEV).......................................................108
5.6.6. Pending register (EXTI_PD)...................................................................................109
6. General-purpose I/Os (GPIO)................................................................................... 110
6.1. Overview................................................................................................................ 110
6.2. Characiteristics..................................................................................................... 110
6.3. Function overview................................................................................................. 110
6.3.1. GPIO pin configuration.......................................................................................... 111
6.3.2. Alternate functions (AF).........................................................................................112
6.3.3. Additional functions ..............................................................................................112
6.3.4. Input configuration................................................................................................112
6.3.5. Output configuration.............................................................................................113
6.3.6. Analog configuration.............................................................................................113
6.3.7. Alternate function (AF) configuration .......................................................................114
6.3.8. GPIO locking function...........................................................................................115
6.3.9. GPIO single cycle toggle function ...........................................................................115
6.4. Register definition................................................................................................. 116

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6.4.1. Port control register (GPIOx_CTL, x=A..D,F)............................................................116
6.4.2. Port output mode register (GPIOx_OMODE, x=A..D,F) ..............................................117
6.4.3. Port output speed register (GPIOx_OSPD, x=A..D,F).................................................119
6.4.4. Port pull-up/down register (GPIOx_PUD, x=A..D,F)...................................................121
6.4.5. Port input status register (GPIOx_ISTAT, x=A..D,F) ...................................................122
6.4.6. Port output control register (GPIOx_OCTL, x=A..D,F)................................................123
6.4.7. Port bit operate register (GPIOx_BOP, x=A..D,F) ......................................................123
6.4.8. Port configuration lock register (GPIOx_LOCK, x=A, B)..............................................124
6.4.9. Alternate function selected register0 (GPIOx_AFSEL0, x=A, B, C)...............................125
6.4.10. Alternate function selected register1 (GPIOx_AFSEL1, x=A,B,C).................................126
6.4.11. Bit clear register (GPIOx_BC, x=A..D,F) ..................................................................127
7. Cyclic redundancy checks management unit (CRC)...........................................128
7.1. Overview................................................................................................................128
7.2. Characteristics......................................................................................................128
7.3. Function overview.................................................................................................129
7.4. Register definition.................................................................................................131
7.4.1. Data Register (CRC_DATA)...................................................................................131
7.4.2. Free Data Register (CRC_FDATA)..........................................................................131
7.4.3. Control Register (CRC_CTL) .................................................................................132
7.4.4. Initialization Data Register (CRC_IDATA).................................................................132
8. Direct me mory access controller (DMA) ...............................................................134
8.1. Overview................................................................................................................134
8.2. Characteristics......................................................................................................134
8.3. Block diagram.......................................................................................................135
8.4. Function overview.................................................................................................135
8.4.1. DMA operation.....................................................................................................135
8.4.2. Peripheral handshake...........................................................................................137
8.4.3. Arbitration...........................................................................................................137
8.4.4. Address generation ..............................................................................................138
8.4.5. Circular mode......................................................................................................138
8.4.6. Memory to memory mode......................................................................................138
8.4.7. Channel configuration...........................................................................................138
8.4.8. Interrupt..............................................................................................................139
8.4.9. DMA request mapping ..........................................................................................140
8.5. Register definition.................................................................................................143
8.5.1. Interrupt flag register (DMA_INTF)..........................................................................143
8.5.2. Interrupt flag clear register (DMA_INTC) ..................................................................143
8.5.3. Channel x control register (DMA_CHxCTL) ..............................................................144
8.5.4. Channel x counter register (DMA_CHxCNT).............................................................146
8.5.5. Channel x peripheral base address register (DMA_CHxPADDR) .................................147

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8.5.6. Channel x memory base address register (DMA_CHxMADDR)...................................147
9. Debug (DBG)..............................................................................................................149
9.1. Overview................................................................................................................149
9.2. Serial Wire Debug port overview..........................................................................149
9.2.1. Pin assignment ....................................................................................................149
9.2.2. JEDEC-106 ID code.............................................................................................149
9.3. Debug hold function overview..............................................................................150
9.3.1. Debug support for power saving mode ....................................................................150
9.3.2. Debug support for TIMER, I2C, RTC, WWDGT and FWDGT.......................................150
9.4. DBG registers........................................................................................................151
9.4.1. ID code register (DBG_ID).....................................................................................151
9.4.2. Control register 0(DBG_CTL0) ...............................................................................151
9.4.3. Control register 1 (DBG_CTL1) ..............................................................................153
10. Analog to digital converter (ADC) .......................................................................155
10.1. Overview............................................................................................................155
10.2. Characteristics...................................................................................................155
10.3. Pins and internal signals...................................................................................156
10.4. Function overview.............................................................................................157
10.4.1. Foreground calibration function ..............................................................................157
10.4.2. Dual clock domain architecture...............................................................................158
10.4.3. ADCON enable....................................................................................................158
10.4.4. Routine sequence................................................................................................158
10.4.5. Operation modes .................................................................................................158
10.4.6. Conversion result threshold monitor function............................................................161
10.4.7. Data storage mode...............................................................................................161
10.4.8. Sample time configuration.....................................................................................162
10.4.9. External trigger configuration .................................................................................163
10.4.10. DMA request....................................................................................................163
10.4.11. ADC internal channels .......................................................................................163
10.4.12. Battery voltage monitoring..................................................................................164
10.4.13. ADC interrupts..................................................................................................164
10.5. Register definition.............................................................................................165
10.5.1. Status register (ADC_STAT) ..................................................................................165
10.5.2. Control register 0 (ADC_CTL0) ..............................................................................165
10.5.3. Control register 1 (ADC_CTL1) ..............................................................................167
10.5.4. Sampling time register 0 (ADC_SAMPT0)................................................................168
10.5.5. Sampling time register 1 (ADC_SAMPT1)................................................................169
10.5.6. Watchdog high threshold register (ADC_WDHT).......................................................170
10.5.7. Watchdog low threshold register (ADC_WDLT).........................................................171
10.5.8. Routine sequence register 0 (ADC_RSQ0) ..............................................................171

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10.5.9. Routine sequence register 1 (ADC_RSQ1) ..............................................................172
10.5.10. Routine sequence register 2 (ADC_RSQ2) ...........................................................172
10.5.11. Routine data register (ADC_RDATA)....................................................................173
11. Digital-to-analog converter (DAC) .......................................................................173
11.1. Overview ............................................................................................................173
11.2. Characteristic.....................................................................................................174
11.3. Function overview .............................................................................................175
11.3.1. DAC enable.........................................................................................................175
11.3.2. DAC output buffer ................................................................................................175
11.3.3. DAC data configuration.........................................................................................175
11.3.4. DAC trigger.........................................................................................................175
11.3.5. DAC workflow......................................................................................................176
11.3.6. DAC output calculate............................................................................................176
11.3.7. DMA function.......................................................................................................176
11.4. Register definition .............................................................................................177
11.4.1. Control register (DAC_CTL)...................................................................................177
11.4.2. Software trigger register (DAC_SWT)......................................................................178
11.4.3. DAC0 12-bit right-aligned data holding register (DAC0_R12DH)..................................178
11.4.4. DAC0 12-bit left-aligned data holding register (DAC0_L12DH) ....................................179
11.4.5. DAC0 8-bit right-aligned data holding register (DAC0_R8DH) .....................................179
11.4.6. DAC0 data output register (DAC0_DO)....................................................................180
11.4.7. Status register (DAC_STAT) ..................................................................................180
12. Comparator (CMP) .................................................................................................182
12.1. Overview ............................................................................................................182
12.2. Characteristics...................................................................................................182
12.3. Function overview .............................................................................................182
12.3.1. CMP clock and reset.............................................................................................183
12.3.2. CMP I/O configure................................................................................................183
12.3.3. CMP operating mode............................................................................................184
12.3.4. CMP hysteresis....................................................................................................184
12.3.5. CMP register write protection.................................................................................184
12.4. Register definition .............................................................................................185
12.4.1. Control/status register (CMP_CS)...........................................................................185
13. Watchdog timer (WDGT) .......................................................................................189
13.1. Free watchdog timer (FWDGT) ..........................................................................189
13.1.1. Overview ............................................................................................................189
13.1.2. Characteristics.....................................................................................................189
13.1.3. Function overview ................................................................................................189
13.1.4. Register definition ................................................................................................192

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13.2. Window watchdog timer (WWDGT) ...................................................................196
13.2.1. Overview ............................................................................................................196
13.2.2. Characteristics.....................................................................................................196
13.2.3. Function overview ................................................................................................196
13.2.4. Register definition ................................................................................................199
14. Real-time clock(RTC).............................................................................................201
14.1. Overview ............................................................................................................201
14.2. Characteristics...................................................................................................201
14.3. Function overview .............................................................................................202
14.3.1. Block diagram......................................................................................................202
14.3.2. Clock source and prescalers..................................................................................202
14.3.3. Shadow registers introduction................................................................................203
14.3.4. Configurable and field maskable alarm ....................................................................203
14.3.5. RTC initialization and configuration.........................................................................204
14.3.6. Calendar reading .................................................................................................205
14.3.7. Resetting the RTC................................................................................................206
14.3.8. RTC shift function.................................................................................................206
14.3.9. RTC reference clock detection ...............................................................................207
14.3.10. RTC smooth digital calibration ............................................................................208
14.3.11. Time-stamp function..........................................................................................210
14.3.12. Tamper detection..............................................................................................210
14.3.13. Calibration clock output......................................................................................211
14.3.14. Alarm output ....................................................................................................211
14.3.15. RTC power saving mode management.................................................................212
14.3.16. RTC interrupts..................................................................................................212
14.4. Register definition .............................................................................................213
14.4.1. Time register (RTC_TIME).....................................................................................213
14.4.2. Date register (RTC_DATE) ....................................................................................213
14.4.3. Control register (RTC_CTL) ...................................................................................214
14.4.4. Status register (RTC_STAT)...................................................................................216
14.4.5. Prescaler register (RTC_PSC) ...............................................................................218
14.4.6. Alarm 0 time and date register (RTC_ALRM0TD)......................................................219
14.4.7. Write protection key register (RTC_WPK) ................................................................220
14.4.8. Sub second register (RTC_SS) ..............................................................................220
14.4.9. Shift function control register (RTC_SHIFTCTL)........................................................221
14.4.10. Time of time stamp register (RTC_TTS) ...............................................................221
14.4.11. Date of time stamp register (RTC_DTS) ...............................................................222
14.4.12. Sub second of time stamp register (RTC_SSTS) ...................................................223
14.4.13. High resolution frequency compensation register (RTC_HRFC) ...............................223
14.4.14. Tamper register (RTC_TAMP).............................................................................224
14.4.15. Alarm 0 sub second register (RTC_ALRM0SS)......................................................226
14.4.16. Backup registers (RTC_BKPx) (x=0..4) ................................................................227

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15. Timer (TIMERx).......................................................................................................229
15.1. Advanced timer (TIMERx,x=0)...........................................................................230
15.1.1. Overview ............................................................................................................230
15.1.2. Characteristics.....................................................................................................230
15.1.3. Block diagram......................................................................................................231
15.1.4. Function overview ................................................................................................231
15.1.5. TIMERx registers(x=0)..........................................................................................258
15.2. General level0 timer (TIMERx, x=1, 2)................................................................285
15.2.1. Overview ............................................................................................................285
15.2.2. Characteristics.....................................................................................................285
15.2.3. Block diagram......................................................................................................285
15.2.4. Function overview ................................................................................................286
15.2.5. TIMERx registers(x=1, 2).......................................................................................299
15.3. General level2 timer (TIMERx, x=13) .................................................................324
15.3.1. Overview ............................................................................................................324
15.3.2. Characteristics.....................................................................................................324
15.3.3. Block diagram......................................................................................................324
15.3.4. Function overview ................................................................................................325
15.3.5. TIMERx registers(x=13) ........................................................................................333
15.4. General level3 timer (TIMERx, x=14) .................................................................343
15.4.1. Overview ............................................................................................................343
15.4.2. Characteristics.....................................................................................................343
15.4.3. Block diagram......................................................................................................343
15.4.4. Function overview ................................................................................................344
15.4.5. TIMERx registers(x=14) ........................................................................................360
15.5. General level4 timer (TIMERx, x=15,16).............................................................379
15.5.1. Overview ............................................................................................................379
15.5.2. Characteristics.....................................................................................................379
15.5.3. Block diagram......................................................................................................379
15.5.4. Function overview ................................................................................................380
15.5.5. TIMERx registers(x=15,16)....................................................................................394
15.6. Basic timer (TIMERx, x=5)..................................................................................410
15.6.1. Overview ............................................................................................................410
15.6.2. Characteristics.....................................................................................................410
15.6.3. Block diagram......................................................................................................410
15.6.4. Function overview ................................................................................................410
15.6.5. TIMERx registers(x=5)..........................................................................................415
16. Infrared ray port (IFRP) .........................................................................................420
16.1. Overview............................................................................................................420
16.2. Characteristics...................................................................................................420

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16.3. Function overview.............................................................................................420
17. Universal synchronous asynchronous receiver transmitter (USART)..........422
17.1. Overview ............................................................................................................422
17.2. Characteristics...................................................................................................422
17.3. Function overview.............................................................................................423
17.3.1. USART frame format ............................................................................................424
17.3.2. Baud rate generation............................................................................................425
17.3.3. USART transmitter ...............................................................................................426
17.3.4. USART receiver ...................................................................................................427
17.3.5. Use DMA for data buffer access .............................................................................428
17.3.6. Hardware flow control...........................................................................................430
17.3.7. Multi-processor communication..............................................................................431
17.3.8. LIN mode............................................................................................................432
17.3.9. Synchronous mode ..............................................................................................433
17.3.10. IrDA SIR ENDEC mode .....................................................................................434
17.3.11. Half-duplex communication mode........................................................................435
17.3.12. Smartcard (ISO7816-3) mode.............................................................................435
17.3.13. ModBus communication.....................................................................................437
17.3.14. Wakeup from deep-sleep mode...........................................................................438
17.3.15. USART interrupts..............................................................................................438
17.4. Register definition .............................................................................................440
17.4.1. Control register 0 (USART_CTL0)...........................................................................440
17.4.2. Control register 1 (USART_CTL1)...........................................................................442
17.4.3. Control register 2 (USART_CTL2)...........................................................................445
17.4.4. Baud rate generator register (USART_BAUD) ..........................................................448
17.4.5. Prescaler and guard time configuration register (USART_GP).....................................448
17.4.6. Receiver timeout register (USART_RT) ...................................................................449
17.4.7. Command register (USART_CMD) .........................................................................450
17.4.8. Status register (USART_STAT) ..............................................................................451
17.4.9. Interrupt status clear register (USART_INTC) ...........................................................454
17.4.10. Receive data register (USART_RDATA) ...............................................................456
17.4.11. Transmit data register (USART_TDATA)...............................................................456
18. Inter-integrated circuit interface (I2C).................................................................457
18.1. Overview............................................................................................................457
18.2. Characteristics...................................................................................................457
18.3. Function overview.............................................................................................457
18.3.1. SDA and SCL lines .............................................................................................458
18.3.2. Data validation...................................................................................................459
18.3.3. START and STOP signal......................................................................................459
18.3.4. Clock synchronization........................................................................................459

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18.3.5. Arbitration .........................................................................................................460
18.3.6. I2C communication flow .....................................................................................460
18.3.7. Programming model...........................................................................................461
18.3.8. SCL line stretching.............................................................................................470
18.3.9. Use DMA for data transfer...................................................................................471
18.3.10. Packet error checking .....................................................................................471
18.3.11. SMBus support...............................................................................................471
18.3.12. Status, errors and interrupts............................................................................473
18.4. Register definition .............................................................................................474
18.4.1. Control register 0 (I2C_CTL0)..............................................................................474
18.4.2. Control register 1 (I2C_CTL1)..............................................................................476
18.4.3. Slave address register 0 (I2C_SADDR0)...............................................................477
18.4.4. Slave address register 1 (I2C_SADDR1)...............................................................477
18.4.5. Transfer buffer register (I2C_DATA) .....................................................................478
18.4.6. Transfer status register 0 (I2C_STAT0).................................................................478
18.4.7. Transfer status register 1 (I2C_STAT1).................................................................481
18.4.8. Clock configure register (I2C_CKCFG).................................................................482
18.4.9. Rise time register (I2C_RT) .................................................................................483
19. Serial peripheral interface/Inter-IC sound (SPI/I2S)..........................................483
19.1. Overview............................................................................................................483
19.2. Characteristics...................................................................................................484
19.2.1. SPI characteristics ...............................................................................................484
19.2.2. I2S characteristics................................................................................................484
19.3. SPI function overview........................................................................................484
19.3.1. SPI block diagram................................................................................................484
19.3.2. SPI signal description ...........................................................................................485
19.3.3. SPI clock timing and data format ............................................................................485
19.3.4. NSS function.......................................................................................................486
19.3.5. SPI operation modes ............................................................................................487
19.3.6. DMA function.......................................................................................................491
19.3.7. CRC function.......................................................................................................492
19.3.8. SPI interrupts ......................................................................................................492
19.4. I2S function overview........................................................................................494
19.4.1. I2S block diagram...............................................................................................494
19.4.2. I2S signal description.........................................................................................494
19.4.3. I2S audio standards............................................................................................494
19.4.4. I2S clock............................................................................................................503
19.4.5. Operation...........................................................................................................503
19.4.6. DMA function.....................................................................................................508
19.4.7. I2S interrupts .....................................................................................................508
19.5. Register definition .............................................................................................510

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19.5.1. Control register 0 (SPI_CTL0) ................................................................................510
19.5.2. Control register 1 (SPI_CTL1)................................................................................512
19.5.3. Status register (SPI_STAT)....................................................................................513
19.5.4. Data register (SPI_DATA)......................................................................................514
19.5.5. CRC polynomial register (SPI_CRCPOLY)...............................................................515
19.5.6. RX CRC register (SPI_RCRC) ...............................................................................515
19.5.7. TX CRC register (SPI_TCRC) ................................................................................516
19.5.8. I2S control register (SPI_I2SCTL)...........................................................................516
19.5.9. I2S clock prescaler register (SPI_I2SPSC)...............................................................518
20. HDMI-CEC controller(HDMI-CEC)........................................................................519
20.1. Overview............................................................................................................519
20.2. Characteristics...................................................................................................519
20.3. Function overview.............................................................................................520
20.3.1. CEC bus pin........................................................................................................520
20.3.2. Message description.............................................................................................520
20.3.3. Bit timing description.............................................................................................521
20.3.4. Arbitration...........................................................................................................522
20.3.5. SFT option bit description......................................................................................523
20.3.6. Error definition.....................................................................................................523
20.3.7. HDMI-CEC interrupt .............................................................................................527
20.4. Register definition .............................................................................................528
20.4.1. Control register (CEC_CTL)...................................................................................528
20.4.2. Configuration register (CEC_CFG)..........................................................................529
20.4.3. Transmit data register (CEC_TDATA)......................................................................530
20.4.4. Receive data register (CEC_RDATA) ......................................................................531
20.4.5. Interrupt Flag Register (CEC_INTF) ........................................................................531
20.4.6. Interrupt enable register (CEC_INTEN)....................................................................533
21. Touch sensing interface (TSI) ..............................................................................536
21.1. Overview............................................................................................................536
21.2. Characteristics...................................................................................................536
21.3. Function Overview.............................................................................................536
21.3.1. TSI block diagram................................................................................................536
21.3.2. Touch sensing technique overview..........................................................................536
21.3.3. Charge transfer sequence.....................................................................................537
21.3.4. Charge transfer sequence FSM..............................................................................539
21.3.5. Clock and duration time of states............................................................................541
21.3.6. PIN mode control of TSI........................................................................................542
21.3.7. Analog switch (ASW) and I/O hysteresis mode .........................................................542
21.3.8. TSI operation flow................................................................................................542
21.3.9. TSI flags and interrupts .........................................................................................543

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21.3.10. TSI GPIOs .......................................................................................................543
21.4. Registers definition............................................................................................545
21.4.1. Control register (TSI_CTL).....................................................................................545
21.4.2. Interrupt enable register (TSI_INTEN) .....................................................................547
21.4.3. Interrupt flag clear register (TSI_INTC) ....................................................................547
21.4.4. Interrupt flag register (TSI_INTF) ............................................................................548
21.4.5. Pin hysteresis mode register (TSI_PHM) .................................................................549
21.4.6. Analog switch register (TSI_ASW)..........................................................................549
21.4.7. Sample configuration register (TSI_SAMPCFG)........................................................550
21.4.8. Channel configuration register (TSI_CHCFG)...........................................................550
21.4.9. Group control register (TSI_GCTL) .........................................................................551
21.4.10. Group x cycle number registers (TSI_GxCYCN) (x = 0…5)......................................551
22. Universal Serial Bus full-speed device interface (USBD)................................553
22.1. Overview............................................................................................................553
22.2. Main features.....................................................................................................553
22.3. Block diagram....................................................................................................553
22.4. Signal description..............................................................................................554
22.5. Clock configuration ...........................................................................................554
22.6. Function overview.............................................................................................554
22.6.1. USB endpoints.....................................................................................................554
22.6.2. Operation procedure.............................................................................................557
22.6.3. USB events and interrupts.....................................................................................560
22.6.4. Operation guide...................................................................................................561
22.7. Register definition .............................................................................................564
22.7.1. USBD control register (USBD_CTL)........................................................................564
22.7.2. USBD interrupt flag register (USBD_INTF)...............................................................565
22.7.3. USBD status register (USBD_STAT) .......................................................................566
22.7.4. USBD device address register (USBD_DADDR).......................................................567
22.7.5. USBD buffer address register (USBD_BADDR) ........................................................568
22.7.6. USBD endpoint x control and status register (USBD_EPxCS), x=[0..7] .........................568
22.7.7. USBD endpoint x transmission buffer address register (USBD_EPxTBADDR), x=[0..7]...570
22.7.8. USBD endpoint x transmission buffer byte count register (USBD_EPxTBCNT), x=[0..7] ..571
22.7.9. USBD endpoint x reception buffer address register (USBD_EPxRBADDR), x=[0..7].....571
22.7.10. USBD endpoint x reception buffer byte count register (USBD_EPxRBCNT), x=[0..7].572
23. Appendix .................................................................................................................573
23.1. List of abbreviations used in register ...............................................................573
23.2. List of terms.......................................................................................................573
23.3. Available peripherals.........................................................................................574

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24. Revision history .....................................................................................................575

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List of Figures
Figure 1-1. The structure of the Cortex®-M3 processor ......................................................................24
Figure 1-2. Series system architecture of GD32F130xx and GD32F150xx devices................25
Figure 2-1. Process of page erase operation...........................................................................................43
Figure 2-2. Process of the mass erase operation ..................................................................................44
Figure 2-3. Process of the word programming operation ..................................................................46
Figure 3-1. Power supply overview ..............................................................................................................58
Figure 3-2. Waveform of the POR/PDR .......................................................................................................60
Figure 3-3. Waveform of LVD threshold......................................................................................................61
Figure 4-1. The system reset circuit.............................................................................................................68
Figure 4-2. Clock tree..........................................................................................................................................69
Figure 4-3. HXTAL clock source.....................................................................................................................70
Figure 5-1. Block diagram of EXTI..............................................................................................................103
Figure 6-1. Basic structure of a general-pupose I/O...........................................................................111
Figure 6-2. Basic structure of Input configuration ..............................................................................113
Figure 6-3. Basic structure of Output configuration...........................................................................113
Figure 6-4. Basic structure of Analog configuration..........................................................................114
Figure 6-5. Basic structure of Alternate function configuration....................................................115
Figure 7-1. Block Diagram of CRC management unit.........................................................................129
Figure 8-1. Block diagram of DMA..............................................................................................................135
Figure 8-2. Handshake mechanism............................................................................................................137
Figure 8-3. DMA interrupt logic....................................................................................................................139
Figure 8-4. DMA request mapping..............................................................................................................141
Figure 10-1. ADC module block diagram.................................................................................................157
Figure 10-2. Single operation mode...........................................................................................................158
Figure 10-3. Continuous operation mode................................................................................................159
Figure 10-4. Scan operation mode, continuous disable ...................................................................160
Figure 10-5. Scan operation mode, continuous enable.....................................................................160
Figure 10-6. Discontinuous operation mode..........................................................................................161
Figure 10-7. Data storage mode of 12-bit resolution ..........................................................................162
Figure 10-8. Data storage mode of 10-bit resolution..........................................................................162
Figure 10-9. Data storage mode of 8-bit resolution.............................................................................162
Figure 10-10. Data storage mode of 6-bit resolution..........................................................................162
Figure 11-1. DAC block diagram..................................................................................................................174
Figure 12-1. CMP block diagram..................................................................................................................183
Figure 12-2. CMP hysteresis..........................................................................................................................184
Figure 13-1. Free watchdog timer block diagram.................................................................................190
Figure 13-2. Window watchdog timer block diagram.........................................................................197
Figure 13-3. Window watchdog timer timing diagram .......................................................................198
Figure 14-1. Block diagram of RTC.............................................................................................................202
Figure 15-1. Advanced timer block diagram...........................................................................................231

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Figure 15-2. Timing chart of internal clock divided by 1...................................................................232
Figure 15-3. Timing chart of PSC value change from 0 to 2............................................................233
Figure 15-4. Timing chart of up counting mode, PSC=0/2...............................................................234
Figure 15-5. Timing chart of up counting mode, change TIMERx_CAR on the go................234
Figure 15-6. Timing chart of down counting mode, PSC=0/2.........................................................235
Figure 15-7. Timing chart of down counting mode, change TIMERx_CAR on the go..........236
Figure 15-8. Center-aligned counter timechart.....................................................................................237
Figure 15-9. Repetition counter timing chart of center-aligned counting mode ....................238
Figure 15-10. Repetition counter timing chart of up counting mode ..........................................238
Figure 15-11. Repetition counter timing chart of down counting mode.....................................239
Figure 15-12. Channel input capture principle......................................................................................240
Figure 15-13. Channel output compare principle (with complementary output, x=0, 1, 2)241
Figure 15-14. Channel output compare principle (CH3_O) ..............................................................241
Figure 15-15. Output-compare under three modes.............................................................................243
Figure 15-16. EAPWM timechart..................................................................................................................244
Figure 15-17. CAPWM timechart..................................................................................................................244
Figure 15-18. Channel output complementary PWM with dead-time insertion.......................247
Figure 15-19. Output behavior in response to a break(The break high active).......................248
Figure 15-20. Example of counter operation in quadrature decoder interface mode ..........249
Figure 15-21. Example of quadrature decoder interface mode with CI0FE0 polarity inverted
...........................................................................................................................................................................249
Figure 15-22. Hall sensor is used to BLDC motor................................................................................250
Figure 15-23. Hall sensor timing between two timers........................................................................251
Figure 15-24. Restart mode............................................................................................................................252
Figure 15-25. Pause mode..............................................................................................................................252
Figure 15-26. Event mode...............................................................................................................................253
Figure 15-27. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60 ......................254
Figure 15-28. TIMER0 Master/Slave mode timer example ................................................................254
Figure 15-29. Triggering TIMER0 with Enable of TIMER2 .................................................................256
Figure 15-30. Triggering TIMER0 and TIMER2 with TIMER2’s CI0 input ....................................257
Figure 15-31. General Level 0 timer block diagram.............................................................................286
Figure 15-32. Timing chart of internal clock divided by 1................................................................287
Figure 15-33. Timing chart of PSC value change from 0 to 2.........................................................288
Figure 15-34. Timing chart of up counting mode, PSC=0/2.............................................................289
Figure 15-35. Timing chart of up counting mode, change TIMERx_CAR on the go.............289
Figure 15-36. Timing chart of down counting mode, PSC=0/2.......................................................290
Figure 15-37. Timing chart of down counting mode, change TIMERx_CAR on the go.......291
Figure 15-38. Center-aligned counter timechart...................................................................................292
Figure 15-39. Channel input capture principle......................................................................................293
Figure 15-40. Channel output compare principle (x=0,1,2,3) ..........................................................294
Figure 15-41. Output-compare under three modes.............................................................................295
Figure 15-42. Timing chart of EAPWM......................................................................................................296
Figure 15-43. Timing chart of CAPWM......................................................................................................296
Figure 15-44. General level2 timer block diagram...............................................................................325

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Figure 15-45. Timing chart of internal clock divided by 1................................................................326
Figure 15-46. Timing chart of PSC value change from 0 to 2.........................................................326
Figure 15-47. Timing chart of up counting mode, PSC=0/2.............................................................327
Figure 15-48. Timing chart of up counting mode, change TIMERx_CAR on the go.............328
Figure 15-49. Channel input capture principle......................................................................................329
Figure 15-50. Channel output compare principle.................................................................................330
Figure 15-51. Output-compare under three modes.............................................................................331
Figure 15-52. PWM mode timechart...........................................................................................................332
Figure 15-53. General level3 timer block diagram...............................................................................344
Figure 15-54. Timing chart of internal clock divided by 1................................................................345
Figure 15-55. Timing chart of PSC value change from 0 to 2.........................................................346
Figure 15-56. Timing chart of up counting mode, PSC=0/2.............................................................347
Figure 15-57. Timing chart of up counting mode, change TIMERx_CAR on the go.............347
Figure 15-58. Repetition counter timing chart of up counting mode ..........................................348
Figure 15-59. Channel input capture principle......................................................................................349
Figure 15-60. Channel output compare principle (with complementary output, x=0)..........350
Figure 15-61. Channel output compare principle (CH1_O)..............................................................350
Figure 15-62. Output-compare under three modes.............................................................................352
Figure 15-63. PWM mode timechart...........................................................................................................353
Figure 15-64. Complementary output with dead-time insertion. ...................................................355
Figure 15-65. Output behavior in response to a break(The break high active).......................356
Figure 15-66. Restart mode............................................................................................................................357
Figure 15-67. Pause mode..............................................................................................................................357
Figure 15-68. Event mode...............................................................................................................................358
Figure 15-69. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99 ...................................359
Figure 15-70. General level4 timer block diagram...............................................................................380
Figure 15-71. Timing chart of internal clock divided by 1................................................................381
Figure 15-72. Timing chart of PSC value change from 0 to 2.........................................................381
Figure 15-73. Timing chart of up counting mode, PSC=0/2.............................................................382
Figure 15-74. Timing chart of up counting mode, change TIMERx_CAR on the go.............383
Figure 15-75. Repetition counter timing chart of up counting mode ..........................................384
Figure 15-76. Channel input capture principle......................................................................................385
Figure 15-77. Output-compare under three modes.............................................................................387
Figure 15-78. PWM mode timechart...........................................................................................................388
Figure 15-79. Channel output complementary PWM with dead-time insertion.......................390
Figure 15-80. Output behavior in response to a break(The break high active).......................391
Figure 15-81. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60 ......................392
Figure 15-82. Basic timer block diagram.................................................................................................410
Figure 15-83. Timing chart of internal clock divided by 1................................................................411
Figure 15-84. Timing chart of PSC value change from 0 to 2.........................................................412
Figure 15-85. Timing chart of up counting mode, PSC=0/2.............................................................413
Figure 15-86. Timing chart of up counting mode, change TIMERx_CAR on the go.............413
Figure 16-1. IFRP output timechart 1.........................................................................................................420
Figure 16-2. IFRP output timechart 2.........................................................................................................421

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Figure 16-3. IFRP output timechart 3.........................................................................................................421
Figure 17-1. USART module block diagram............................................................................................424
Figure 17-2. USART character frame (8 bits data and 1 stop bit)..................................................425
Figure 17-3. USART transmit procedure ..................................................................................................427
Figure 17-4. Oversampling method of a receive frame bit (OSB=0) ............................................428
Figure 17-5. Configuration step when using DMA for USART transmission ...........................429
Figure 17-6. Configuration step when using DMA for USART reception...................................430
Figure 17-7. Hardware flow control between two USARTs ..............................................................430
Figure 17-8. Hardware flow control ............................................................................................................431
Figure 17-9. Break frame occurs during idle state ..............................................................................432
Figure 17-10. Break frame occurs during a frame ...............................................................................433
Figure 17-11. Example of USART in synchronous mode..................................................................433
Figure 17-12. 8-bit format USART synchronous waveform (CLEN=1) ........................................434
Figure 17-13. IrDA SIR ENDEC module.....................................................................................................434
Figure 17-14. IrDA data modulation............................................................................................................435
Figure 17-15. ISO7816-3 frame format.......................................................................................................436
Figure 17-16. USART interrupt mapping diagram................................................................................439
Figure 18-1. I2C module block diagram....................................................................................................458
Figure 18-2. Data validation...........................................................................................................................459
Figure 18-3. START and STOP signal........................................................................................................459
Figure 18-4. Clock synchronization............................................................................................................460
Figure 18-5. SDA line arbitration..................................................................................................................460
Figure 18-6. I2C communication flow with 7-bit address..................................................................461
Figure 18-7. I2C communication flow with 10-bit address (Master Transmit) .........................461
Figure 18-8. I2C communication flow with 10-bit address (Master Receive)...........................461
Figure 18-9. Programming model for slave transmitting (10-bit address mode) ...................463
Figure 18-10. Programming model for slave receiving (10-bit address mode).......................464
Figure 18-11. Programming model for master transmitting (10-bit address mode)..............466
Figure 18-12. Programming model for master receiving using Solution A (10-bit address
mode)..............................................................................................................................................................468
Figure 18-13. Programming model for master receiving mode using solution B (10-bit
address mode)............................................................................................................................................469
Figure 19-1. Block diagram of SPI..............................................................................................................484
Figure 19-2. SPI timing diagram in normal mode.................................................................................486
Figure 19-3. A typical full-duplex connection........................................................................................488
Figure 19-4. A typical simplex connection (Master: receive, Slave: transmit) ........................489
Figure 19-5. A typical simplex connection (Master: transmit only, Slave: receive)..............489
Figure 19-6. A typical bidirectional connection....................................................................................489
Figure 19-7. Block diagram of I2S...............................................................................................................494
Figure 19-8. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0)...........495
Figure 19-9. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1)...........495
Figure 19-10. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) ........495
Figure 19-11. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ........496
Figure 19-12. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ........496

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Figure 19-13. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ........496
Figure 19-14. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) ........496
Figure 19-15. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) ........497
Figure 19-16. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0) ....497
Figure 19-17. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) ....497
Figure 19-18. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0)....497
Figure 19-19. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ....497
Figure 19-20. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ....498
Figure 19-21. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ....498
Figure 19-22. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) ....498
Figure 19-23. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1)....498
Figure 19-24. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) .....498
Figure 19-25. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1).....499
Figure 19-26. LSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) .....499
Figure 19-27. LSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) .....499
Figure 19-28. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=0)..................................................................................................................................499
Figure 19-29. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=1)..................................................................................................................................500
Figure 19-30. PCM standard short frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=0)..................................................................................................................................500
Figure 19-31. PCM standard short frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=1)..................................................................................................................................500
Figure 19-32. PCM standard short frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=0)..................................................................................................................................500
Figure19-33. PCM standard short frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=1)..................................................................................................................................500
Figure 19-34. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=0)..................................................................................................................................501
Figure 19-35. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=1)..................................................................................................................................501
Figure 19-36. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=0)..................................................................................................................................501
Figure19-37. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=1)..................................................................................................................................501
Figure 19-38. PCM standard long frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=0)..................................................................................................................................501
Figure 19-39. PCM standard long frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=1)..................................................................................................................................501
Figure 19-40. PCM standard long frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=0)..................................................................................................................................502
Figure 19-41. PCM standard long frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=1)..................................................................................................................................502
Figure 19-42. PCM standard long frame synchronization mode timing diagram (DTLEN=00,

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CHLEN=1, CKPL=0)..................................................................................................................................502
Figure 19-43. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=1)..................................................................................................................................502
Figure 19-44. Block diagram of I2S clock generator...........................................................................503
Figure 19-45. I2S initialization sequence.................................................................................................505
Figure 19-46. I2S master reception disabling sequence...................................................................507
Figure 20-1. HDMI-CEC Controller block diagram ...............................................................................520
Figure 20-2. Message Structure ...................................................................................................................520
Figure 20-3. Start Bit Timing..........................................................................................................................521
Figure 20-4. Data Bit Timing..........................................................................................................................521
Figure 20-5. The process of CEC line arbitration.................................................................................522
Figure 20-6. The free time of signal............................................................................................................522
Figure 20-7. Erro bit period............................................................................................................................524
Figure 20-8. The timing of Bit Period Long Error .................................................................................525
Figure 20-9. Transmission error detection..............................................................................................526
Figure 21-1. Block diagram of TSI module..............................................................................................536
Figure 21-2. Block diagram of sample pin and channel pin............................................................537
Figure 21-3. Voltage of a sample pin during charge -transfer sequence ....................................539
Figure 21-4. FSM flow of a charge-transfer sequence .......................................................................540
Figure 22-1. USBD block diagram...............................................................................................................553
Figure 22-2. An example with buffer descriptor table usage (USBD_BADDR = 0) ................556