GigaDevice Semiconductor GD32F1 0 Series User manual

GigaDevice Semiconductor Inc.
GD32F1x0
Arm® Cortex®-M3 32-bit MCU
For GD32F130xx,GD32F150xx
User Manual
Revision 3.7
(Jun. 2023)

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Table of Contents
Table of Contents.................................................................................................................2
List of Figures ....................................................................................................................15
List of Tables ......................................................................................................................21
1. System and memory architecture ............................................................................23
1.1. ARM Cortex-M3 processor......................................................................................23
1.2. Systemarchitecture................................................................................................24
1.3. Memory map............................................................................................................25
1.3.1. Bit-banding............................................................................................................28
1.3.2. On-chip SRAM memory ..........................................................................................28
1.3.3. On-chip Flash memory............................................................................................29
1.4. Boot configuration..................................................................................................29
1.5. Systemconfiguration registers (SYSCFG).............................................................31
1.5.1. System configuration register 0 (SYSCFG_CFG0) ......................................................31
1.5.2. EXTI sources selection register 0 (SYSCFG_EXTISS0) ...............................................32
1.5.3. EXTI sources selection register 1 (SYSCFG_EXTISS1) ...............................................33
1.5.4. EXTI sources selection register 2 (SYSCFG_EXTISS2) ...............................................34
1.5.5. EXTI sources selection register 3 (SYSCFG_EXTISS3) ...............................................36
1.5.6. System configuration register 2 (SYSCFG_CFG2) ......................................................37
1.6. Device electronic signature....................................................................................38
1.6.1. Memory density information.....................................................................................38
1.6.2. Unique device ID (96 bits) .......................................................................................39
2. Flash me mory controller (FMC) ................................................................................41
2.1. Overview..................................................................................................................41
2.2. Characteristics........................................................................................................41
2.3. Function overview...................................................................................................41
2.3.1. Flash memory architecture ......................................................................................41
2.3.2. Read operations ....................................................................................................42
2.3.3. Unlock the FMC_CTL register..................................................................................42
2.3.4. Page erase ...........................................................................................................42
2.3.5. Mass erase...........................................................................................................43
2.3.6. Main flash programming..........................................................................................45
2.3.7. Option bytes erase.................................................................................................46
2.3.8. Option bytes programming.......................................................................................47
2.3.9. Option bytes description..........................................................................................47
2.3.10. Page erase/Program protection................................................................................48

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2.3.11. Security protection .................................................................................................49
2.4. Register definition...................................................................................................50
2.4.1. Wait state register (FMC_WS)..................................................................................50
2.4.2. Unlock key register (FMC_KEY)...............................................................................50
2.4.3. Option bytes unlock key register (FMC_OBKEY).........................................................51
2.4.4. Status register (FMC_STAT) ....................................................................................51
2.4.5. Control register (FMC_CTL).....................................................................................52
2.4.6. Address register (FMC_ADDR) ................................................................................53
2.4.7. Option bytes status register (FMC_OBSTAT)..............................................................54
2.4.8. Write protection register (FMC_WP)..........................................................................54
2.4.9. Wait state enable register (FMC_WSEN) ...................................................................55
2.4.10. Product ID register (FMC_PID).................................................................................55
3. Power management unit (PMU) ................................................................................57
3.1. Overview..................................................................................................................57
3.2. Characteristics........................................................................................................57
3.3. Function overview...................................................................................................57
3.3.1. Backup domain......................................................................................................59
3.3.2. VDD / VDDA power domain.........................................................................................59
3.3.3. VDD domain...........................................................................................................60
3.3.4. 1.2V power domain ................................................................................................61
3.3.5. Power saving modes ..............................................................................................62
3.4. Register definition...................................................................................................64
3.4.1. Control register (PMU_CTL) ....................................................................................64
3.4.2. Power control/status register (PMU_CS)....................................................................65
4. Reset and clock unit (RCU) .......................................................................................67
4.1. Reset control unit (RCTL) .......................................................................................67
4.1.1. Overview ..............................................................................................................67
4.1.2. Function overview ..................................................................................................67
4.2. Clock control unit (CCTL) .......................................................................................68
4.2.1. Overview ..............................................................................................................68
4.2.2. Characteristics.......................................................................................................70
4.2.3. Function overview ..................................................................................................70
4.3. Register definition...................................................................................................74
4.3.1. Control register 0 (RCU_CTL0) ................................................................................74
4.3.2. Configuration register 0 (RCU_CFG0).......................................................................75
4.3.3. Interrupt register (RCU_INT) ....................................................................................79
4.3.4. APB2 reset register (RCU_APB2RST).......................................................................82
4.3.5. APB1 reset register (RCU_APB1RST).......................................................................83
4.3.6. AHB enable register (RCU_AHBEN).........................................................................85
4.3.7. APB2 enable register (RCU_APB2EN)......................................................................87

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4.3.8. APB1 enable register (RCU_APB1EN)......................................................................88
4.3.9. Backup domain control register (RCU_BDCTL)...........................................................90
4.3.10. Reset source /clock register (RCU_RSTSCK).............................................................92
4.3.11. AHB reset register (RCU_AHBRST)..........................................................................93
4.3.12. Configuration register 1 (RCU_CFG1).......................................................................94
4.3.13. Configuration register 2 (RCU_CFG2).......................................................................95
4.3.14. Control register 1 (RCU_CTL1) ................................................................................96
4.3.15. APB1 additional enable register (RCU_ADDAPB1EN) .................................................97
4.3.16. APB1 additional reset register (RCU_ADDAPB1RST)..................................................97
4.3.17. Voltage key register (RCU_VKEY)............................................................................98
4.3.18. Deep-sleep mode voltage register (RCU_DSV)...........................................................98
4.3.19. Power down voltage select register (RCU_PDVSEL)...................................................99
5. Interrupt / event controller (EXTI)...........................................................................100
5.1. Overview................................................................................................................100
5.2. Characteristics......................................................................................................100
5.3. Interrupts function overview.................................................................................100
5.4. External interrupt and event block diagram.........................................................103
5.5. External interrupt and event function overview ...................................................103
5.6. Register definition.................................................................................................106
5.6.1. Interrupt Enable register (EXTI_INTEN)...................................................................106
5.6.2. Event enable register (EXTI_EVEN)........................................................................106
5.6.3. Rising edge trigger enable register (EXTI_RTEN)......................................................107
5.6.4. Falling edge trigger enable register (EXTI_FTEN) .....................................................107
5.6.5. Software interrupt event register (EXTI_SWIEV).......................................................108
5.6.6. Pending register (EXTI_PD)...................................................................................109
6. General-purpose I/Os (GPIO)................................................................................... 110
6.1. Overview................................................................................................................ 110
6.2. Characiteristics..................................................................................................... 110
6.3. Function overview................................................................................................. 110
6.3.1. GPIO pin configuration.......................................................................................... 111
6.3.2. Alternate functions (AF).........................................................................................112
6.3.3. Additional functions ..............................................................................................112
6.3.4. Input configuration................................................................................................112
6.3.5. Output configuration.............................................................................................113
6.3.6. Analog configuration.............................................................................................113
6.3.7. Alternate function (AF) configuration .......................................................................114
6.3.8. GPIO locking function...........................................................................................115
6.3.9. GPIO single cycle toggle function ...........................................................................115
6.4. Register definition................................................................................................. 116

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6.4.1. Port control register (GPIOx_CTL, x=A..D,F)............................................................116
6.4.2. Port output mode register (GPIOx_OMODE, x=A..D,F) ..............................................117
6.4.3. Port output speed register (GPIOx_OSPD, x=A..D,F).................................................119
6.4.4. Port pull-up/down register (GPIOx_PUD, x=A..D,F)...................................................121
6.4.5. Port input status register (GPIOx_ISTAT, x=A..D,F) ...................................................122
6.4.6. Port output control register (GPIOx_OCTL, x=A..D,F)................................................123
6.4.7. Port bit operate register (GPIOx_BOP, x=A..D,F) ......................................................123
6.4.8. Port configuration lock register (GPIOx_LOCK, x=A, B)..............................................124
6.4.9. Alternate function selected register0 (GPIOx_AFSEL0, x=A, B, C)...............................125
6.4.10. Alternate function selected register1 (GPIOx_AFSEL1, x=A,B,C).................................126
6.4.11. Bit clear register (GPIOx_BC, x=A..D,F) ..................................................................127
7. Cyclic redundancy checks management unit (CRC)...........................................128
7.1. Overview................................................................................................................128
7.2. Characteristics......................................................................................................128
7.3. Function overview.................................................................................................129
7.4. Register definition.................................................................................................131
7.4.1. Data Register (CRC_DATA)...................................................................................131
7.4.2. Free Data Register (CRC_FDATA)..........................................................................131
7.4.3. Control Register (CRC_CTL) .................................................................................132
7.4.4. Initialization Data Register (CRC_IDATA).................................................................132
8. Direct me mory access controller (DMA) ...............................................................134
8.1. Overview................................................................................................................134
8.2. Characteristics......................................................................................................134
8.3. Block diagram.......................................................................................................135
8.4. Function overview.................................................................................................135
8.4.1. DMA operation.....................................................................................................135
8.4.2. Peripheral handshake...........................................................................................137
8.4.3. Arbitration...........................................................................................................137
8.4.4. Address generation ..............................................................................................138
8.4.5. Circular mode......................................................................................................138
8.4.6. Memory to memory mode......................................................................................138
8.4.7. Channel configuration...........................................................................................138
8.4.8. Interrupt..............................................................................................................139
8.4.9. DMA request mapping ..........................................................................................140
8.5. Register definition.................................................................................................143
8.5.1. Interrupt flag register (DMA_INTF)..........................................................................143
8.5.2. Interrupt flag clear register (DMA_INTC) ..................................................................143
8.5.3. Channel x control register (DMA_CHxCTL) ..............................................................144
8.5.4. Channel x counter register (DMA_CHxCNT).............................................................146
8.5.5. Channel x peripheral base address register (DMA_CHxPADDR) .................................147

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8.5.6. Channel x memory base address register (DMA_CHxMADDR)...................................147
9. Debug (DBG)..............................................................................................................149
9.1. Overview................................................................................................................149
9.2. Serial Wire Debug port overview..........................................................................149
9.2.1. Pin assignment ....................................................................................................149
9.2.2. JEDEC-106 ID code.............................................................................................149
9.3. Debug hold function overview..............................................................................150
9.3.1. Debug support for power saving mode ....................................................................150
9.3.2. Debug support for TIMER, I2C, RTC, WWDGT and FWDGT.......................................150
9.4. DBG registers........................................................................................................151
9.4.1. ID code register (DBG_ID).....................................................................................151
9.4.2. Control register 0(DBG_CTL0) ...............................................................................151
9.4.3. Control register 1 (DBG_CTL1) ..............................................................................153
10. Analog to digital converter (ADC) .......................................................................155
10.1. Overview............................................................................................................155
10.2. Characteristics...................................................................................................155
10.3. Pins and internal signals...................................................................................156
10.4. Function overview.............................................................................................157
10.4.1. Foreground calibration function ..............................................................................157
10.4.2. Dual clock domain architecture...............................................................................158
10.4.3. ADCON enable....................................................................................................158
10.4.4. Routine sequence................................................................................................158
10.4.5. Operation modes .................................................................................................158
10.4.6. Conversion result threshold monitor function............................................................161
10.4.7. Data storage mode...............................................................................................161
10.4.8. Sample time configuration.....................................................................................162
10.4.9. External trigger configuration .................................................................................163
10.4.10. DMA request....................................................................................................163
10.4.11. ADC internal channels .......................................................................................163
10.4.12. Battery voltage monitoring..................................................................................164
10.4.13. ADC interrupts..................................................................................................164
10.5. Register definition.............................................................................................165
10.5.1. Status register (ADC_STAT) ..................................................................................165
10.5.2. Control register 0 (ADC_CTL0) ..............................................................................165
10.5.3. Control register 1 (ADC_CTL1) ..............................................................................167
10.5.4. Sampling time register 0 (ADC_SAMPT0)................................................................168
10.5.5. Sampling time register 1 (ADC_SAMPT1)................................................................169
10.5.6. Watchdog high threshold register (ADC_WDHT).......................................................170
10.5.7. Watchdog low threshold register (ADC_WDLT).........................................................171
10.5.8. Routine sequence register 0 (ADC_RSQ0) ..............................................................171

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10.5.9. Routine sequence register 1 (ADC_RSQ1) ..............................................................172
10.5.10. Routine sequence register 2 (ADC_RSQ2) ...........................................................172
10.5.11. Routine data register (ADC_RDATA)....................................................................173
11. Digital-to-analog converter (DAC) .......................................................................173
11.1. Overview ............................................................................................................173
11.2. Characteristic.....................................................................................................174
11.3. Function overview .............................................................................................175
11.3.1. DAC enable.........................................................................................................175
11.3.2. DAC output buffer ................................................................................................175
11.3.3. DAC data configuration.........................................................................................175
11.3.4. DAC trigger.........................................................................................................175
11.3.5. DAC workflow......................................................................................................176
11.3.6. DAC output calculate............................................................................................176
11.3.7. DMA function.......................................................................................................176
11.4. Register definition .............................................................................................177
11.4.1. Control register (DAC_CTL)...................................................................................177
11.4.2. Software trigger register (DAC_SWT)......................................................................178
11.4.3. DAC0 12-bit right-aligned data holding register (DAC0_R12DH)..................................178
11.4.4. DAC0 12-bit left-aligned data holding register (DAC0_L12DH) ....................................179
11.4.5. DAC0 8-bit right-aligned data holding register (DAC0_R8DH) .....................................179
11.4.6. DAC0 data output register (DAC0_DO)....................................................................180
11.4.7. Status register (DAC_STAT) ..................................................................................180
12. Comparator (CMP) .................................................................................................182
12.1. Overview ............................................................................................................182
12.2. Characteristics...................................................................................................182
12.3. Function overview .............................................................................................182
12.3.1. CMP clock and reset.............................................................................................183
12.3.2. CMP I/O configure................................................................................................183
12.3.3. CMP operating mode............................................................................................184
12.3.4. CMP hysteresis....................................................................................................184
12.3.5. CMP register write protection.................................................................................184
12.4. Register definition .............................................................................................185
12.4.1. Control/status register (CMP_CS)...........................................................................185
13. Watchdog timer (WDGT) .......................................................................................189
13.1. Free watchdog timer (FWDGT) ..........................................................................189
13.1.1. Overview ............................................................................................................189
13.1.2. Characteristics.....................................................................................................189
13.1.3. Function overview ................................................................................................189
13.1.4. Register definition ................................................................................................192

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13.2. Window watchdog timer (WWDGT) ...................................................................196
13.2.1. Overview ............................................................................................................196
13.2.2. Characteristics.....................................................................................................196
13.2.3. Function overview ................................................................................................196
13.2.4. Register definition ................................................................................................199
14. Real-time clock(RTC).............................................................................................201
14.1. Overview ............................................................................................................201
14.2. Characteristics...................................................................................................201
14.3. Function overview .............................................................................................202
14.3.1. Block diagram......................................................................................................202
14.3.2. Clock source and prescalers..................................................................................202
14.3.3. Shadow registers introduction................................................................................203
14.3.4. Configurable and field maskable alarm ....................................................................203
14.3.5. RTC initialization and configuration.........................................................................204
14.3.6. Calendar reading .................................................................................................205
14.3.7. Resetting the RTC................................................................................................206
14.3.8. RTC shift function.................................................................................................206
14.3.9. RTC reference clock detection ...............................................................................207
14.3.10. RTC smooth digital calibration ............................................................................208
14.3.11. Time-stamp function..........................................................................................210
14.3.12. Tamper detection..............................................................................................210
14.3.13. Calibration clock output......................................................................................211
14.3.14. Alarm output ....................................................................................................211
14.3.15. RTC power saving mode management.................................................................212
14.3.16. RTC interrupts..................................................................................................212
14.4. Register definition .............................................................................................213
14.4.1. Time register (RTC_TIME).....................................................................................213
14.4.2. Date register (RTC_DATE) ....................................................................................213
14.4.3. Control register (RTC_CTL) ...................................................................................214
14.4.4. Status register (RTC_STAT)...................................................................................216
14.4.5. Prescaler register (RTC_PSC) ...............................................................................218
14.4.6. Alarm 0 time and date register (RTC_ALRM0TD)......................................................219
14.4.7. Write protection key register (RTC_WPK) ................................................................220
14.4.8. Sub second register (RTC_SS) ..............................................................................220
14.4.9. Shift function control register (RTC_SHIFTCTL)........................................................221
14.4.10. Time of time stamp register (RTC_TTS) ...............................................................221
14.4.11. Date of time stamp register (RTC_DTS) ...............................................................222
14.4.12. Sub second of time stamp register (RTC_SSTS) ...................................................223
14.4.13. High resolution frequency compensation register (RTC_HRFC) ...............................223
14.4.14. Tamper register (RTC_TAMP).............................................................................224
14.4.15. Alarm 0 sub second register (RTC_ALRM0SS)......................................................226
14.4.16. Backup registers (RTC_BKPx) (x=0..4) ................................................................227

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15. Timer (TIMERx).......................................................................................................229
15.1. Advanced timer (TIMERx,x=0)...........................................................................230
15.1.1. Overview ............................................................................................................230
15.1.2. Characteristics.....................................................................................................230
15.1.3. Block diagram......................................................................................................231
15.1.4. Function overview ................................................................................................231
15.1.5. TIMERx registers(x=0)..........................................................................................258
15.2. General level0 timer (TIMERx, x=1, 2)................................................................285
15.2.1. Overview ............................................................................................................285
15.2.2. Characteristics.....................................................................................................285
15.2.3. Block diagram......................................................................................................285
15.2.4. Function overview ................................................................................................286
15.2.5. TIMERx registers(x=1, 2).......................................................................................299
15.3. General level2 timer (TIMERx, x=13) .................................................................324
15.3.1. Overview ............................................................................................................324
15.3.2. Characteristics.....................................................................................................324
15.3.3. Block diagram......................................................................................................324
15.3.4. Function overview ................................................................................................325
15.3.5. TIMERx registers(x=13) ........................................................................................333
15.4. General level3 timer (TIMERx, x=14) .................................................................343
15.4.1. Overview ............................................................................................................343
15.4.2. Characteristics.....................................................................................................343
15.4.3. Block diagram......................................................................................................343
15.4.4. Function overview ................................................................................................344
15.4.5. TIMERx registers(x=14) ........................................................................................360
15.5. General level4 timer (TIMERx, x=15,16).............................................................379
15.5.1. Overview ............................................................................................................379
15.5.2. Characteristics.....................................................................................................379
15.5.3. Block diagram......................................................................................................379
15.5.4. Function overview ................................................................................................380
15.5.5. TIMERx registers(x=15,16)....................................................................................394
15.6. Basic timer (TIMERx, x=5)..................................................................................410
15.6.1. Overview ............................................................................................................410
15.6.2. Characteristics.....................................................................................................410
15.6.3. Block diagram......................................................................................................410
15.6.4. Function overview ................................................................................................410
15.6.5. TIMERx registers(x=5)..........................................................................................415
16. Infrared ray port (IFRP) .........................................................................................420
16.1. Overview............................................................................................................420
16.2. Characteristics...................................................................................................420

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16.3. Function overview.............................................................................................420
17. Universal synchronous asynchronous receiver transmitter (USART)..........422
17.1. Overview ............................................................................................................422
17.2. Characteristics...................................................................................................422
17.3. Function overview.............................................................................................423
17.3.1. USART frame format ............................................................................................424
17.3.2. Baud rate generation............................................................................................425
17.3.3. USART transmitter ...............................................................................................426
17.3.4. USART receiver ...................................................................................................427
17.3.5. Use DMA for data buffer access .............................................................................428
17.3.6. Hardware flow control...........................................................................................430
17.3.7. Multi-processor communication..............................................................................431
17.3.8. LIN mode............................................................................................................432
17.3.9. Synchronous mode ..............................................................................................433
17.3.10. IrDA SIR ENDEC mode .....................................................................................434
17.3.11. Half-duplex communication mode........................................................................435
17.3.12. Smartcard (ISO7816-3) mode.............................................................................435
17.3.13. ModBus communication.....................................................................................437
17.3.14. Wakeup from deep-sleep mode...........................................................................438
17.3.15. USART interrupts..............................................................................................438
17.4. Register definition .............................................................................................440
17.4.1. Control register 0 (USART_CTL0)...........................................................................440
17.4.2. Control register 1 (USART_CTL1)...........................................................................442
17.4.3. Control register 2 (USART_CTL2)...........................................................................445
17.4.4. Baud rate generator register (USART_BAUD) ..........................................................448
17.4.5. Prescaler and guard time configuration register (USART_GP).....................................448
17.4.6. Receiver timeout register (USART_RT) ...................................................................449
17.4.7. Command register (USART_CMD) .........................................................................450
17.4.8. Status register (USART_STAT) ..............................................................................451
17.4.9. Interrupt status clear register (USART_INTC) ...........................................................454
17.4.10. Receive data register (USART_RDATA) ...............................................................456
17.4.11. Transmit data register (USART_TDATA)...............................................................456
18. Inter-integrated circuit interface (I2C).................................................................457
18.1. Overview............................................................................................................457
18.2. Characteristics...................................................................................................457
18.3. Function overview.............................................................................................457
18.3.1. SDA and SCL lines .............................................................................................458
18.3.2. Data validation...................................................................................................459
18.3.3. START and STOP signal......................................................................................459
18.3.4. Clock synchronization........................................................................................459